coreboot-gerrit November 2018

coreboot-gerrit@coreboot.org

1 participants
1699 discussions

Change in coreboot[master]: src/cpu: Remove dead sourced lines
by Elyes HAOUAS (Code Review) 12 Nov '18

12 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29584 Change subject: src/cpu: Remove dead sourced lines ...................................................................... src/cpu: Remove dead sourced lines Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/Kconfig M src/cpu/intel/Kconfig M src/cpu/via/Kconfig M src/soc/intel/Kconfig 4 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29584/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 8c8c831..5f7e0f9 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -80,6 +80,5 @@ source src/cpu/amd/agesa/family12/Kconfig source src/cpu/amd/agesa/family14/Kconfig -source src/cpu/amd/agesa/family15/Kconfig source src/cpu/amd/agesa/family15tn/Kconfig source src/cpu/amd/agesa/family16kb/Kconfig diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index a1f9dde..26b9347 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -14,12 +14,9 @@ source src/cpu/intel/fsp_model_206ax/Kconfig source src/cpu/intel/fsp_model_406dx/Kconfig source src/cpu/intel/model_2065x/Kconfig -source src/cpu/intel/model_f0x/Kconfig -source src/cpu/intel/model_f1x/Kconfig source src/cpu/intel/model_f2x/Kconfig source src/cpu/intel/model_f3x/Kconfig source src/cpu/intel/model_f4x/Kconfig -source src/cpu/intel/ep80579/Kconfig source src/cpu/intel/haswell/Kconfig # Sockets/Slots source src/cpu/intel/slot_1/Kconfig diff --git a/src/cpu/via/Kconfig b/src/cpu/via/Kconfig index 5c38c91..d9a9230 100644 --- a/src/cpu/via/Kconfig +++ b/src/cpu/via/Kconfig @@ -1,3 +1 @@ -source src/cpu/via/c3/Kconfig -source src/cpu/via/c7/Kconfig source src/cpu/via/nano/Kconfig diff --git a/src/soc/intel/Kconfig b/src/soc/intel/Kconfig index 2c24596..c447046 100644 --- a/src/soc/intel/Kconfig +++ b/src/soc/intel/Kconfig @@ -8,7 +8,6 @@ source "src/soc/intel/fsp_baytrail/Kconfig" source "src/soc/intel/fsp_broadwell_de/Kconfig" source "src/soc/intel/quark/Kconfig" -source "src/soc/intel/sch/Kconfig" source "src/soc/intel/skylake/Kconfig" source "src/soc/intel/icelake/Kconfig" -- To view, visit https://review.coreboot.org/29584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I836ff09da17373d47daf21c98e5ab975836cd47e Gerrit-Change-Number: 29584 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file"
by Elyes HAOUAS (Code Review) 12 Nov '18

12 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29583 Change subject: mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file" ...................................................................... mb/emulation/qemu-i440fx/Makefile.inc: Fix "No newline at end of file" Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/emulation/qemu-i440fx/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29583/1 diff --git a/src/mainboard/emulation/qemu-i440fx/Makefile.inc b/src/mainboard/emulation/qemu-i440fx/Makefile.inc index c986667..ecc049e 100644 --- a/src/mainboard/emulation/qemu-i440fx/Makefile.inc +++ b/src/mainboard/emulation/qemu-i440fx/Makefile.inc @@ -2,4 +2,4 @@ ramstage-y += northbridge.c ramstage-y += fw_cfg.c romstage-y += memory.c -ramstage-y += memory.c \ No newline at end of file +ramstage-y += memory.c -- To view, visit https://review.coreboot.org/29583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I79e9b95059f16c53767c89cfaef1e89182be9c62 Gerrit-Change-Number: 29583 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: siemens/mc_apl4: Enable SDCARD
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29561 ) Change subject: siemens/mc_apl4: Enable SDCARD ...................................................................... siemens/mc_apl4: Enable SDCARD This mainboard also has a SD slot. Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29561 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index d03623a..2562bf6 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -84,7 +84,7 @@ device pci 19.1 off end # - SPI 1 device pci 19.2 off end # - SPI 2 device pci 1a.0 off end # - PWM - device pci 1b.0 off end # - SDCARD + device pci 1b.0 on end # - SDCARD device pci 1c.0 on end # - eMMC device pci 1d.0 off end # - UFS device pci 1e.0 off end # - SDIO -- To view, visit https://review.coreboot.org/29561 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id56bc1be60ec8c2be0e5543d1d8851610b7248e0 Gerrit-Change-Number: 29561 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove external RTC from I2C0
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29560 ) Change subject: siemens/mc_apl4: Remove external RTC from I2C0 ...................................................................... siemens/mc_apl4: Remove external RTC from I2C0 This mainboard also has an external RTC chip, but not on this bus. The topic is currently in clarification and will be published with a later patch. In a first step we enable all I2C busses. Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29560 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 7 insertions(+), 21 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 61e8c71..d03623a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -68,27 +68,13 @@ device pci 14.1 on end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI - device pci 16.0 on # - I2C 0 - # Enable external RTC chip - chip drivers/i2c/rx6110sa - register "pmon_sampling" = "PMON_SAMPL_256_MS" - register "bks_on" = "0" - register "bks_off" = "1" - register "iocut_en" = "1" - register "set_user_date" = "1" - register "user_year" = "04" - register "user_month" = "07" - register "user_day" = "01" - register "user_weekday" = "4" - device i2c 0x32 on end # RTC RX6110 SA - end - end - device pci 16.1 off end # - I2C 1 - device pci 16.2 off end # - I2C 2 - device pci 16.3 off end # - I2C 3 - device pci 17.0 off end # - I2C 4 - device pci 17.1 off end # - I2C 5 - device pci 17.2 off end # - I2C 6 + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 device pci 17.3 on end # - I2C 7 device pci 18.0 on end # - UART 0 device pci 18.1 on end # - UART 1 -- To view, visit https://review.coreboot.org/29560 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I9ec9631ed15ab30cc6a4594531521f4a1419ad00 Gerrit-Change-Number: 29560 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl4: Enable all PCIe root ports
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29559 ) Change subject: siemens/mc_apl4: Enable all PCIe root ports ...................................................................... siemens/mc_apl4: Enable all PCIe root ports Enable all PCIe root ports for this mainboard. Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29559 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 8c219af..61e8c71 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -60,12 +60,12 @@ device pci 0e.0 off end # - Audio device pci 11.0 on end # - ISH device pci 12.0 on end # - SATA - device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY - device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY - device pci 13.2 off end # - RP 4 - PCIe-A 2 - device pci 13.3 off end # - RP 5 - PCIe-A 3 - device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge - device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 13.0 on end # - RP 2 - PCIe A 0 + device pci 13.1 on end # - RP 3 - PCIe A 1 + device pci 13.2 on end # - RP 4 - PCIe-A 2 + device pci 13.3 on end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 + device pci 14.1 on end # - RP 1 - PCIe-B 1 device pci 15.0 on end # - XHCI device pci 15.1 off end # - XDCI device pci 16.0 on # - I2C 0 -- To view, visit https://review.coreboot.org/29559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I7f6feb2f0d4c45f32d9454838e67e1a244b2712b Gerrit-Change-Number: 29559 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl4: Remove reduced clock rate for I2C0
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29558 ) Change subject: siemens/mc_apl4: Remove reduced clock rate for I2C0 ...................................................................... siemens/mc_apl4: Remove reduced clock rate for I2C0 There is no device on I2C0 which requires a lower clock rate. Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29558 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 0 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index a2a2ba1..8c219af 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -47,18 +47,6 @@ # 0:HS400(Default), 1:HS200, 2:DDR50 register "emmc_host_max_speed" = "2" - # Intel Common SoC Config - #+-------------------+---------------------------+ - #| Field | Value | - #+-------------------+---------------------------+ - #| I2C0 | Proximity Sensor | - #+-------------------+---------------------------+ - register "common_soc_config" = "{ - .i2c[0] = { - .speed = I2C_SPEED_STANDARD - }, - }" - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 off end # - DPTF -- To view, visit https://review.coreboot.org/29558 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib7c4e3251545b2d32368dd56206e3b4844a24800 Gerrit-Change-Number: 29558 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl4: Disable CLKREQ of PCIe root ports
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29556 ) Change subject: siemens/mc_apl4: Disable CLKREQ of PCIe root ports ...................................................................... siemens/mc_apl4: Disable CLKREQ of PCIe root ports All PCIe root ports of this mainboard do not have an associated CLKREQ signal. Therefore the ports are marked with "CLKREQ_DISABLED". Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29556 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb 1 file changed, 6 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index f3e8a77..a2a2ba1 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -6,11 +6,12 @@ register "sci_irq" = "SCIS_IRQ10" - # Disable unused clkreq of PCIe root ports - register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge - register "pcie_rp_clkreq_pin[1]" = "2" # FPGA - register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY - register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + # Disable all clkreq of PCIe root ports as SMARC interface do not + # have this pins. + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" -- To view, visit https://review.coreboot.org/29556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I834b3b0c77223d81c950e27ccfff8e9aeece2aa4 Gerrit-Change-Number: 29556 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29549 ) Change subject: siemens/mc_apl3: Disable PCI clock outputs on XIO bridges ...................................................................... siemens/mc_apl3: Disable PCI clock outputs on XIO bridges On this mainboard there are legacy PCI device, which are connected to different PCIe root ports via PCIe-2-PCI bridges. This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridges. Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29549 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 17 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 3a87a4f..c436b02 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -40,11 +40,6 @@ */ pcr_write16(PID_ITSS, 0x314c, 0x2103); - /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ - dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); - if (dev) - pci_write_config8(dev, 0xd8, 0x3e); - /* Enable CLKRUN_EN for power gating LPC */ lpc_enable_pci_clk_cntl(); @@ -62,6 +57,23 @@ cmd = pci_read_config16(dev, PCI_COMMAND); cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); + + /* Disable clock outputs 0 and 2-4 (CLKOUT) for upstream + * XIO2001 PCIe to PCI Bridge. + */ + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x1d); + } + + /* Disable clock outputs 2-5 (CLKOUT) for another XIO2001 PCIe to PCI + * Bridge on this mainboard. + */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403f, 0); + if (dev) { + struct device *parent = dev->bus->dev; + if (parent && parent->device == PCI_DEVICE_ID_TI_XIO2001) + pci_write_config8(parent, 0xd8, 0x3c); } /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). -- To view, visit https://review.coreboot.org/29549 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2212c1080b72a656b5c8e68b040108a7adbec608 Gerrit-Change-Number: 29549 Gerrit-PatchSet: 6 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29530 ) Change subject: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register ...................................................................... siemens/mc_apl3: Set Full Reset Bit into Reset Control Register This mainboard provides customer hardware reset button. A feature of this button is that it holds the APL in reset state as long as the reset button is pressed. After releasing the reset button the APL should restart again without the need for a power cycle. When Bit 3 in Reset Control Register (I/O port CF9h) is set to 1 and then the reset button is pressed the PCH will drive SLP_S3 active (low). Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29530 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index f41fe73..3a87a4f 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -14,6 +14,7 @@ */ #include <bootstate.h> +#include <cf9_reset.h> #include <console/console.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -62,6 +63,13 @@ cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + + /* Set Full Reset Bit in Reset Control Register (I/O port CF9h). + * When Bit 3 is set to 1 and then the reset button is pressed the PCH + * will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard + * to generate the right reset timing. + */ + outb(FULL_RST, RST_CNT); } static void wait_for_legacy_dev(void *unused) -- To view, visit https://review.coreboot.org/29530 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b Gerrit-Change-Number: 29530 Gerrit-PatchSet: 3 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: siemens/mc_apl3: Set bus master bit for on-board PCI device
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29528 ) Change subject: siemens/mc_apl3: Set bus master bit for on-board PCI device ...................................................................... siemens/mc_apl3: Set bus master bit for on-board PCI device There is an on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29528 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 10 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index bfcf38e..f41fe73 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -15,6 +15,7 @@ #include <bootstate.h> #include <console/console.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <gpio.h> @@ -31,6 +32,7 @@ void variant_mainboard_final(void) { struct device *dev = NULL; + uint16_t cmd = 0; /* PIR6 register mapping for PCIe root ports * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# @@ -52,6 +54,14 @@ * offset 0x341C bit [3:0]. */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* Set Master Enable for on-board PCI device. */ + dev = dev_find_device(PCI_VENDOR_ID_SIEMENS, 0x403e, 0); + if (dev) { + cmd = pci_read_config16(dev, PCI_COMMAND); + cmd |= PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, cmd); + } } static void wait_for_legacy_dev(void *unused) -- To view, visit https://review.coreboot.org/29528 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I1ef4a7774d4ca75c230063debbc63d03486fed6f Gerrit-Change-Number: 29528 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2018