coreboot-gerrit November 2018

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Change in coreboot[master]: siemens/mc_apl3: Remove the correction of the Tx signal for SATA
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29527 ) Change subject: siemens/mc_apl3: Remove the correction of the Tx signal for SATA ...................................................................... siemens/mc_apl3: Remove the correction of the Tx signal for SATA For this mainboard the correction of transmit voltage swing from SATA interface is not necessary. Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29527 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 0 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index ade923a..bfcf38e 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -52,14 +52,6 @@ * offset 0x341C bit [3:0]. */ pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); - - /* - * Correct the SATA transmit signal via the High Speed I/O Transmit - * Control Register 3. - * Bit [23:16] set the output voltage swing for TX line. - * The value 0x4a sets the swing level to 0.58 V. - */ - pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); } static void wait_for_legacy_dev(void *unused) -- To view, visit https://review.coreboot.org/29527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I900d0d44b88585c223182d85c78cf3ff1e3e9159 Gerrit-Change-Number: 29527 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices
by Werner Zeh (Code Review) 12 Nov '18

12 Nov '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/29513 ) Change subject: siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices ...................................................................... siemens/mc_apl3: Adjust Legacy IRQ routing for PCI devices On this mainboard there is a legacy PCI device, which is connected to the PCIe root port via a PCIe-2-PCI bridge. This device only supports legacy interrupt routing. For this reason we have to adjust the PIR6 register (0x314c) which is responsible for PCIe device 13h and 14h. This means that the interrupt routing will also be the same for both PCIe devices. The bridge is connected to PCIe root port 2 and 3 over two lanes (Device 13.0 and 13.1). The following routing is required: INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#->PIRQC# Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29513 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 1 file changed, 3 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index ccf3ab8..ade923a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -32,11 +32,10 @@ { struct device *dev = NULL; - /* - * PIR6 register mapping for PCIe root ports - * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + /* PIR6 register mapping for PCIe root ports + * INTA#->PIRQD#, INTB#->PIRQA#, INTC#->PIRQB#, INTD#-> PIRQC# */ - pcr_write16(PID_ITSS, 0x314c, 0x0321); + pcr_write16(PID_ITSS, 0x314c, 0x2103); /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); -- To view, visit https://review.coreboot.org/29513 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I5028c26769a2122b1c609ad7789c9949e3cb7a87 Gerrit-Change-Number: 29513 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
by Furquan Shaikh (Code Review) 12 Nov '18

12 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29553 ) Change subject: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz ...................................................................... Patch Set 3: > Patch Set 3: Code-Review+2 Please don't score your own CLs. -- To view, visit https://review.coreboot.org/29553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Gerrit-Change-Number: 29553 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Nov 2018 07:19:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz
by Furquan Shaikh (Code Review) 12 Nov '18

12 Nov '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29553 ) Change subject: mb/google/poppy/variant/atlas: I2C: run trackpad at 1MHz ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/29553 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iaf42ba7b8818b7cd9c8dcc657823dac705659d38 Gerrit-Change-Number: 29553 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: caveh jalali <caveh(a)chromium.org> Gerrit-Comment-Date: Mon, 12 Nov 2018 07:19:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Get rid of duplicated includes
by Elyes HAOUAS (Code Review) 11 Nov '18

11 Nov '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29582 to look at the new patch set (#2). Change subject: src: Get rid of duplicated includes ...................................................................... src: Get rid of duplicated includes Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/pirq_routing.c M src/lib/prog_loaders.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/opencellular/elgon/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/traf_ctrl.c M src/security/vboot/secdata_tpm.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/sor.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/nvidia/mcp55/lpc.c 87 files changed, 6 insertions(+), 109 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29582/2 -- To view, visit https://review.coreboot.org/29582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Gerrit-Change-Number: 29582 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Get rid of duplicated includes
by Elyes HAOUAS (Code Review) 11 Nov '18

11 Nov '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29582 Change subject: src: Get rid of duplicated includes ...................................................................... src: Get rid of duplicated includes Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/pirq_routing.c M src/lib/prog_loaders.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bimini_fam10/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c M src/mainboard/amd/serengeti_cheetah_fam10/romstage.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/apple/macbook21/mainboard.c M src/mainboard/asus/kcma-d8/romstage.c M src/mainboard/asus/kfsn4-dre/get_bus_conf.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/romstage.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/hp/dl165_g6_fam10/romstage.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/lenovo/x60/dock.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/opencellular/elgon/mainboard.c M src/mainboard/packardbell/ms2290/mainboard.c M src/mainboard/pcengines/apu2/romstage.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/mainboard/via/epia-m850/romstage.c M src/northbridge/amd/amdmct/mct_ddr3/s3utils.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/gm45/acpi.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/i945/acpi.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/raminit.c M src/northbridge/intel/x4x/acpi.c M src/northbridge/via/vx900/early_vx900.h M src/northbridge/via/vx900/raminit_ddr3.c M src/northbridge/via/vx900/traf_ctrl.c M src/security/vboot/secdata_tpm.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/include/soc/pci_devs.h M src/soc/intel/baytrail/acpi.c M src/soc/intel/baytrail/southcluster.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/intel/broadwell/lpc.c M src/soc/intel/broadwell/refcode.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/denverton_ns/systemagent.c M src/soc/intel/fsp_baytrail/acpi.c M src/soc/intel/fsp_baytrail/northcluster.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/include/soc/pci_devs.h M src/soc/nvidia/tegra124/display.c M src/soc/nvidia/tegra210/sor.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/smihandler.c M src/southbridge/intel/common/spi.c M src/southbridge/intel/fsp_rangeley/early_init.c M src/southbridge/intel/fsp_rangeley/lpc.c M src/southbridge/intel/fsp_rangeley/soc.h M src/southbridge/intel/fsp_rangeley/spi.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/smihandler.c M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/nvidia/mcp55/lpc.c 87 files changed, 4 insertions(+), 113 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29582/1 diff --git a/src/arch/x86/pirq_routing.c b/src/arch/x86/pirq_routing.c index 7aa50d7..f705944 100644 --- a/src/arch/x86/pirq_routing.c +++ b/src/arch/x86/pirq_routing.c @@ -18,7 +18,6 @@ #include <arch/pirq_routing.h> #include <string.h> #include <device/pci.h> -#include <arch/pirq_routing.h> void __weak pirq_assign_irqs(const unsigned char pirq[CONFIG_MAX_PIRQ_LINKS]) { diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 5004a7f..a9c9add 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -29,7 +29,6 @@ #include <stage_cache.h> #include <symbols.h> #include <timestamp.h> -#include <cbfs.h> #include <fit_payload.h> /* Only can represent up to 1 byte less than size_t. */ diff --git a/src/mainboard/advansus/a785e-i/romstage.c b/src/mainboard/advansus/a785e-i/romstage.c index 281a59a..96c2a1c 100644 --- a/src/mainboard/advansus/a785e-i/romstage.c +++ b/src/mainboard/advansus/a785e-i/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 51bc5d5..31d7c5c 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -30,7 +30,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 4da9747..4aceeea 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/amd/lamar/mptable.c b/src/mainboard/amd/lamar/mptable.c index ed16923..27f3a1c 100644 --- a/src/mainboard/amd/lamar/mptable.c +++ b/src/mainboard/amd/lamar/mptable.c @@ -23,7 +23,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_pci_util.h> #include <drivers/generic/ioapic/chip.h> -#include <arch/ioapic.h> #include <southbridge/amd/pi/hudson/amd_pci_int_defs.h> #include <northbridge/amd/pi/00630F01/pci_devs.h> diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 136e392..7f811c5 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/fintek/f81216h/f81216h.h> diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index e9f3111..77885d4 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -32,7 +32,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 4ad0f6d..3cd8b73 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c index 374420d..fee0109 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mainboard.c @@ -13,7 +13,6 @@ #include <device/device.h> #include <arch/acpi.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include "mainboard.h" diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 622784b..0433840 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -31,7 +31,6 @@ #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> #include <spd.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index fbb9238..c27543c 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -30,7 +30,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/apple/macbook21/mainboard.c b/src/mainboard/apple/macbook21/mainboard.c index eb963ee..49d3427 100644 --- a/src/mainboard/apple/macbook21/mainboard.c +++ b/src/mainboard/apple/macbook21/mainboard.c @@ -21,7 +21,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <northbridge/intel/i945/i945.h> #include <arch/x86/include/arch/acpigen.h> diff --git a/src/mainboard/asus/kcma-d8/romstage.c b/src/mainboard/asus/kcma-d8/romstage.c index ec76c45..9e2dd79 100644 --- a/src/mainboard/asus/kcma-d8/romstage.c +++ b/src/mainboard/asus/kcma-d8/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c index 4b23ca5..5c8c75e 100644 --- a/src/mainboard/asus/kfsn4-dre/get_bus_conf.c +++ b/src/mainboard/asus/kfsn4-dre/get_bus_conf.c @@ -26,7 +26,6 @@ #include <stdlib.h> #include <cpu/amd/multicore.h> #include <cpu/amd/amdfam10_sysconf.h> -#include <stdlib.h> /* * Global variables for MB layouts and these will be shared by irqtable, diff --git a/src/mainboard/asus/kfsn4-dre/romstage.c b/src/mainboard/asus/kfsn4-dre/romstage.c index 6045274..6d15f51 100644 --- a/src/mainboard/asus/kfsn4-dre/romstage.c +++ b/src/mainboard/asus/kfsn4-dre/romstage.c @@ -38,7 +38,6 @@ #include <southbridge/amd/common/reset.h> #include <southbridge/nvidia/ck804/early_smbus.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 9b72a79..190beba 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 4184586..f33b671 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -31,7 +31,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index d7538c8..1cb77d6 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -32,7 +32,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 512c08e..54ec940 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -31,7 +31,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/avalue/eax-785e/romstage.c b/src/mainboard/avalue/eax-785e/romstage.c index 49352ca..96a6703 100644 --- a/src/mainboard/avalue/eax-785e/romstage.c +++ b/src/mainboard/avalue/eax-785e/romstage.c @@ -29,7 +29,6 @@ #include <console/console.h> #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 576a3ee..eefda26 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -29,7 +29,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index ce896f2..fd0d928 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -25,7 +25,6 @@ #include <soc/uart.h> #include <console/console.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/timer.h> #include <soc/cpu.h> #include <soc/sdram.h> diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 87bfaba..c69bf81 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -28,7 +28,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 0b9e07d..91c7623 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -28,7 +28,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index 8dbdfb0..e81e4d9 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -31,7 +31,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/ite/common/ite.h> diff --git a/src/mainboard/google/jecht/smihandler.c b/src/mainboard/google/jecht/smihandler.c index 8243354..b9a84bf 100644 --- a/src/mainboard/google/jecht/smihandler.c +++ b/src/mainboard/google/jecht/smihandler.c @@ -25,8 +25,6 @@ #include <soc/gpio.h> #include <soc/iomap.h> #include <soc/nvs.h> -#include <soc/pm.h> -#include <soc/smm.h> #include "onboard.h" int mainboard_io_trap_handler(int smif) diff --git a/src/mainboard/hp/dl165_g6_fam10/romstage.c b/src/mainboard/hp/dl165_g6_fam10/romstage.c index 5af01c1..f972872 100644 --- a/src/mainboard/hp/dl165_g6_fam10/romstage.c +++ b/src/mainboard/hp/dl165_g6_fam10/romstage.c @@ -38,7 +38,6 @@ #include <lib.h> #include <spd.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 815cf34..6d6f148 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -31,7 +31,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/jetway/pa78vm5/romstage.c b/src/mainboard/jetway/pa78vm5/romstage.c index 440d703..4dfd71e 100644 --- a/src/mainboard/jetway/pa78vm5/romstage.c +++ b/src/mainboard/jetway/pa78vm5/romstage.c @@ -32,7 +32,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <superio/fintek/common/fintek.h> diff --git a/src/mainboard/lenovo/x60/dock.c b/src/mainboard/lenovo/x60/dock.c index f55428e..b94d818 100644 --- a/src/mainboard/lenovo/x60/dock.c +++ b/src/mainboard/lenovo/x60/dock.c @@ -18,7 +18,6 @@ #include <device/device.h> #include <arch/io.h> #include <delay.h> -#include <arch/io.h> #include "dock.h" #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nsc/pc87392/pc87392.h> diff --git a/src/mainboard/msi/ms9652_fam10/romstage.c b/src/mainboard/msi/ms9652_fam10/romstage.c index 3d22439..5ff2ac2 100644 --- a/src/mainboard/msi/ms9652_fam10/romstage.c +++ b/src/mainboard/msi/ms9652_fam10/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index 45a7155..d140bc1 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -24,14 +24,12 @@ #include <soc/uart.h> #include <console/console.h> #include <soc/clock.h> -#include <soc/gpio.h> #include <soc/timer.h> #include <soc/cpu.h> #include <soc/sdram.h> #include <soc/spi.h> #include <spi_flash.h> #include <fmap.h> -#include <libbdk-hal/bdk-config.h> static void mainboard_print_info(void) { diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 2691b67..77a626d 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -23,7 +23,6 @@ #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/bd82x6x/pch.h> #include <ec/acpi/ec.h> diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 3c5eed6..55a89fb 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -31,7 +31,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5104d/nct5104d.h> diff --git a/src/mainboard/supermicro/h8dmr_fam10/romstage.c b/src/mainboard/supermicro/h8dmr_fam10/romstage.c index 3fb3ca0..73f5857 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/romstage.c +++ b/src/mainboard/supermicro/h8dmr_fam10/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/supermicro/h8qme_fam10/romstage.c b/src/mainboard/supermicro/h8qme_fam10/romstage.c index 5ea0f64..42ad6ab 100644 --- a/src/mainboard/supermicro/h8qme_fam10/romstage.c +++ b/src/mainboard/supermicro/h8qme_fam10/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> diff --git a/src/mainboard/supermicro/h8scm_fam10/romstage.c b/src/mainboard/supermicro/h8scm_fam10/romstage.c index 11da86e..6a4a5f8 100644 --- a/src/mainboard/supermicro/h8scm_fam10/romstage.c +++ b/src/mainboard/supermicro/h8scm_fam10/romstage.c @@ -31,7 +31,6 @@ #include <timestamp.h> #include <cpu/amd/model_10xxx_rev.h> #include <lib.h> -#include <cpu/x86/lapic.h> #include <commonlib/loglevel.h> #include <cpu/x86/bist.h> #include <cpu/amd/msr.h> diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 99d58f8..4c2b4c5 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -31,7 +31,6 @@ #include <spd.h> #include <cpu/amd/model_10xxx_rev.h> #include <delay.h> -#include <cpu/x86/lapic.h> #include <cpu/amd/car.h> #include <cpu/amd/msr.h> #include <superio/winbond/common/winbond.h> diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index e75a679..db03103 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <device/pnp_def.h> -#include <arch/io.h> #include <console/console.h> #include <lib.h> #include <cpu/x86/bist.h> diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c index 6fd5b36..eb39c81 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c @@ -30,8 +30,6 @@ #include <spi_flash.h> #include <pc80/mc146818rtc.h> #include <inttypes.h> -#include <console/console.h> -#include <string.h> #include "mct_d.h" #include "mct_d_gcc.h" diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f6cb285..7a24d11 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include <assert.h> #include <northbridge/amd/agesa/agesa_helper.h> diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index fb3610d..826ce3e 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -33,7 +33,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include <northbridge/amd/agesa/agesa_helper.h> #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 7125e1e..804ce6e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -35,7 +35,6 @@ #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include <northbridge/amd/agesa/agesa_helper.h> #if IS_ENABLED(CONFIG_BINARYPI_LEGACY_WRAPPER) diff --git a/src/northbridge/intel/fsp_rangeley/acpi.c b/src/northbridge/intel/fsp_rangeley/acpi.c index c8e6d45..23044b7 100644 --- a/src/northbridge/intel/fsp_rangeley/acpi.c +++ b/src/northbridge/intel/fsp_rangeley/acpi.c @@ -24,7 +24,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include "northbridge.h" diff --git a/src/northbridge/intel/gm45/acpi.c b/src/northbridge/intel/gm45/acpi.c index d208eed..1fd7a46 100644 --- a/src/northbridge/intel/gm45/acpi.c +++ b/src/northbridge/intel/gm45/acpi.c @@ -23,7 +23,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbmem.h> -#include <arch/acpigen.h> #include <cpu/cpu.h> #include "gm45.h" diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 405eb5d..a738905 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -25,7 +25,6 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> -#include <cbmem.h> #include <cpu/intel/smm/gen1/smi.h> #include "chip.h" #include "gm45.h" diff --git a/src/northbridge/intel/i945/acpi.c b/src/northbridge/intel/i945/acpi.c index 990d3de..c959966 100644 --- a/src/northbridge/intel/i945/acpi.c +++ b/src/northbridge/intel/i945/acpi.c @@ -23,7 +23,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbmem.h> -#include <arch/acpigen.h> #include <cpu/cpu.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index de55cc3..bec0c58 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -22,7 +22,6 @@ #include <device/pci_ids.h> #include <stdlib.h> #include <string.h> -#include <cbmem.h> #include <cpu/cpu.h> #include <arch/acpi.h> #include "i945.h" diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 71d9853..ed93daa 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -23,7 +23,6 @@ #include <spd.h> #include <string.h> #include <halt.h> -#include <lib.h> #include "raminit.h" #include "i945.h" #include "chip.h" diff --git a/src/northbridge/intel/x4x/acpi.c b/src/northbridge/intel/x4x/acpi.c index 678486c..12bdf65 100644 --- a/src/northbridge/intel/x4x/acpi.c +++ b/src/northbridge/intel/x4x/acpi.c @@ -24,7 +24,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <cbmem.h> -#include <arch/acpigen.h> #include <cpu/cpu.h> #include "x4x.h" diff --git a/src/northbridge/via/vx900/early_vx900.h b/src/northbridge/via/vx900/early_vx900.h index 11c561a..55b6c69 100644 --- a/src/northbridge/via/vx900/early_vx900.h +++ b/src/northbridge/via/vx900/early_vx900.h @@ -23,7 +23,6 @@ #include <arch/io.h> #include <cbmem.h> #include <stdint.h> -#include <arch/io.h> /* North Module devices */ #define HOST_CTR PCI_DEV(0, 0, 0) diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 17a87bb..1d05fa7 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -17,7 +17,6 @@ #include "early_vx900.h" #include "raminit.h" #include <arch/io.h> -#include <arch/io.h> #include <console/console.h> #include <device/pci_ids.h> #include <delay.h> diff --git a/src/northbridge/via/vx900/traf_ctrl.c b/src/northbridge/via/vx900/traf_ctrl.c index 8bdf25c..c2b4a48 100644 --- a/src/northbridge/via/vx900/traf_ctrl.c +++ b/src/northbridge/via/vx900/traf_ctrl.c @@ -17,8 +17,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <console/console.h> -#include <device/pci.h> -#include <device/pci_ids.h> #include <drivers/generic/ioapic/chip.h> #include "vx900.h" diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index c62f18b..f639e35 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -47,7 +47,6 @@ #include <stdio.h> #define VBDEBUG(format, args...) printf(format, ## args) #else -#include <console/console.h> #define VBDEBUG(format, args...) \ printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) #endif diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 0bf76f7..53a9913 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -33,7 +33,6 @@ #include <soc/ecam0.h> #include <console/uart.h> #include <libbdk-hal/bdk-pcie.h> -#include <soc/ecam0.h> #include <device/pci.h> #include <libbdk-hal/bdk-qlm.h> #include <libbdk-hal/bdk-config.h> diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index e70bfa3..7df2324 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -34,7 +34,6 @@ #include <intelblocks/xdci.h> #include <fsp/api.h> #include <fsp/util.h> -#include <intelblocks/acpi.h> #include <intelblocks/cpulib.h> #include <intelblocks/itss.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 37d0fab..ad726f8 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -23,7 +23,6 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) #define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index cdf3abf..4e85b32 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -21,7 +21,6 @@ #include <cbmem.h> #include <console/console.h> #include <cpu/x86/smm.h> -#include <console/console.h> #include <types.h> #include <string.h> #include <arch/cpu.h> diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 0ef70d0..05bf192 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -36,7 +36,6 @@ #include <soc/ramstage.h> #include <soc/spi.h> #include "chip.h" -#include <arch/acpi.h> #include <arch/acpigen.h> #include <cpu/cpu.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 03f9ac0..31c7142 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -22,7 +22,6 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> -#include <cbmem.h> #include <chip.h> #include <cpu/x86/mtrr.h> #include <console/console.h> diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c index ff7ff81..71560c2 100644 --- a/src/soc/intel/broadwell/lpc.c +++ b/src/soc/intel/broadwell/lpc.c @@ -41,9 +41,7 @@ #include <soc/ramstage.h> #include <soc/rcba.h> #include <soc/intel/broadwell/chip.h> -#include <arch/acpi.h> #include <arch/acpigen.h> -#include <cpu/cpu.h> static void pch_enable_ioapic(struct device *dev) { diff --git a/src/soc/intel/broadwell/refcode.c b/src/soc/intel/broadwell/refcode.c index 7eb548e..6d192cc 100644 --- a/src/soc/intel/broadwell/refcode.c +++ b/src/soc/intel/broadwell/refcode.c @@ -22,7 +22,6 @@ #include <program_loading.h> #include <rmodule.h> #include <stage_cache.h> -#include <string.h> #include <soc/pei_data.h> #include <soc/pei_wrapper.h> #include <soc/pm.h> diff --git a/src/soc/intel/cannonlake/include/soc/pci_devs.h b/src/soc/intel/cannonlake/include/soc/pci_devs.h index 63a59db..77ae746 100644 --- a/src/soc/intel/cannonlake/include/soc/pci_devs.h +++ b/src/soc/intel/cannonlake/include/soc/pci_devs.h @@ -25,7 +25,6 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) #define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else diff --git a/src/soc/intel/denverton_ns/systemagent.c b/src/soc/intel/denverton_ns/systemagent.c index 6b72a0c..f41714f 100644 --- a/src/soc/intel/denverton_ns/systemagent.c +++ b/src/soc/intel/denverton_ns/systemagent.c @@ -27,7 +27,6 @@ #include <string.h> #include <cbmem.h> #include <romstage_handoff.h> -#include <delay.h> #include <timer.h> #include <soc/iomap.h> diff --git a/src/soc/intel/fsp_baytrail/acpi.c b/src/soc/intel/fsp_baytrail/acpi.c index 97c8d5b..4d21fe3 100644 --- a/src/soc/intel/fsp_baytrail/acpi.c +++ b/src/soc/intel/fsp_baytrail/acpi.c @@ -35,14 +35,12 @@ #include <string.h> #include <soc/iomap.h> #include <soc/lpc.h> -#include <soc/pci_devs.h> #include <soc/pmc.h> #include <soc/irq.h> #include <soc/iosf.h> #include <arch/io.h> #include <soc/msr.h> #include <soc/pattrs.h> -#include <soc/pmc.h> #include <cpu/cpu.h> #include <cbmem.h> diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index f909121..93cd2f2 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -24,7 +24,6 @@ #include <soc/iosf.h> #include <soc/pci_devs.h> #include <soc/ramstage.h> -#include <device/pci.h> #include <cbmem.h> #include <soc/baytrail.h> #include <drivers/intel/fsp1_0/fsp_util.h> diff --git a/src/soc/intel/icelake/include/soc/pci_devs.h b/src/soc/intel/icelake/include/soc/pci_devs.h index 9b9e434..94f1d0d 100644 --- a/src/soc/intel/icelake/include/soc/pci_devs.h +++ b/src/soc/intel/icelake/include/soc/pci_devs.h @@ -24,7 +24,6 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) #define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 7cc6de5..8a78348 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -20,13 +20,9 @@ #include <fsp/api.h> #include <arch/acpi.h> #include <arch/io.h> -#include <chip.h> -#include <bootstate.h> #include <console/console.h> #include <device/device.h> -#include <device/pci.h> #include <device/pci_ids.h> -#include <fsp/api.h> #include <fsp/util.h> #include <intelblocks/chip.h> #include <intelblocks/itss.h> diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 25a9610..a2fa52a 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -24,7 +24,6 @@ #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/smbus.h> -#include <stdint.h> static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { diff --git a/src/soc/intel/skylake/include/soc/pci_devs.h b/src/soc/intel/skylake/include/soc/pci_devs.h index bc6c9cb..1fc3621 100644 --- a/src/soc/intel/skylake/include/soc/pci_devs.h +++ b/src/soc/intel/skylake/include/soc/pci_devs.h @@ -25,7 +25,6 @@ #if !defined(__SIMPLE_DEVICE__) #include <device/device.h> -#include <device/pci_def.h> #define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot)) #define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func)) #else diff --git a/src/soc/nvidia/tegra124/display.c b/src/soc/nvidia/tegra124/display.c index c90e392..e61c40d 100644 --- a/src/soc/nvidia/tegra124/display.c +++ b/src/soc/nvidia/tegra124/display.c @@ -30,7 +30,6 @@ #include <soc/nvidia/tegra/pwm.h> #include <stdint.h> #include <stdlib.h> -#include <stdlib.h> #include <string.h> #include "chip.h" diff --git a/src/soc/nvidia/tegra210/sor.c b/src/soc/nvidia/tegra210/sor.c index a00bdad..6b6216c 100644 --- a/src/soc/nvidia/tegra210/sor.c +++ b/src/soc/nvidia/tegra210/sor.c @@ -24,7 +24,6 @@ #include <delay.h> #include <soc/addressmap.h> #include <device/device.h> -#include <stdlib.h> #include <string.h> #include <cpu/cpu.h> #include <boot/tables.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 67f1de6..07a4d8a 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -32,7 +32,6 @@ #include <cpu/x86/smm.h> #include <cbmem.h> #include <string.h> -#include <cpu/x86/smm.h> #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index da1c7e4..73d11de 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -31,13 +31,8 @@ #include <delay.h> #include <elog.h> #include <halt.h> - -#ifdef __SMM__ -#include <arch/io.h> -#else # include <device/device.h> # include <device/pci.h> -#endif #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 1a59dc4..419c0ab 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -31,13 +31,8 @@ #include <delay.h> #include <elog.h> #include <halt.h> - -#ifdef __SMM__ -#include <arch/io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif +#include <device/device.h> +#include <device/pci.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index a108840..03d2687 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -28,7 +28,6 @@ #include "nvs.h" #include <northbridge/intel/sandybridge/sandybridge.h> -#include <arch/io.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 31cdb33..71655bc 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -37,7 +37,6 @@ #ifdef __SMM__ -#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ @@ -52,7 +51,6 @@ pci_write_config32(dev, reg, val) #else /* !__SMM__ */ #include <device/device.h> -#include <device/pci.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/fsp_rangeley/early_init.c b/src/southbridge/intel/fsp_rangeley/early_init.c index ba4ebe0..1ef8cb2 100644 --- a/src/southbridge/intel/fsp_rangeley/early_init.c +++ b/src/southbridge/intel/fsp_rangeley/early_init.c @@ -22,7 +22,6 @@ #include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <version.h> -#include <device/pci_def.h> #include "pci_devs.h" #include "soc.h" diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index 88cc73f..f490b58 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -29,7 +29,6 @@ #include <elog.h> #include <string.h> #include <cbmem.h> -#include <arch/acpi.h> #include <arch/acpigen.h> #include "soc.h" #include "irq.h" diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0917201..ffadee4 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -62,7 +62,6 @@ int soc_silicon_supported(int type, int rev); void soc_enable(struct device *dev); -#include <arch/acpi.h> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); #if IS_ENABLED(CONFIG_ELOG) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 98ae708..9754806 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -29,7 +29,6 @@ static int ich_status_poll(u16 bitmask, int wait_til_set); #ifdef __SMM__ -#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 0d75350..e082b73 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -30,13 +30,8 @@ #include <string.h> #include <delay.h> #include <elog.h> - -#ifdef __SMM__ -#include <arch/io.h> -#else -# include <device/device.h> -# include <device/pci.h> -#endif +#include <device/device.h> +#include <device/pci.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 4da76cf..b70273c 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -34,7 +34,6 @@ */ #include <northbridge/intel/nehalem/nehalem.h> #include <southbridge/intel/common/gpio.h> -#include <arch/io.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 9e0ce8a..d22913c 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -33,7 +33,6 @@ #include "nvs.h" #include "pch.h" #include <arch/acpigen.h> -#include <cbmem.h> #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/rtc.h> diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 5850ab5..a02be81 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -174,7 +174,6 @@ #if !defined(__PRE_RAM__) && !defined(__SMM__) #include <device/device.h> -#include <arch/acpi.h> #include "chip.h" void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); diff --git a/src/southbridge/nvidia/mcp55/lpc.c b/src/southbridge/nvidia/mcp55/lpc.c index b6bb1f8..3ac6464 100644 --- a/src/southbridge/nvidia/mcp55/lpc.c +++ b/src/southbridge/nvidia/mcp55/lpc.c @@ -33,7 +33,6 @@ #include <arch/acpi.h> #include <stdlib.h> #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) -#include <arch/acpi.h> #include <arch/acpigen.h> #endif #include <cpu/amd/powernow.h> -- To view, visit https://review.coreboot.org/29582 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I252a1cd77bf647477edb7dddadb7e527de872439 Gerrit-Change-Number: 29582 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: LinuxBoot: refactor payload
by Marcello Sylvester Bauer (Code Review) 11 Nov '18

11 Nov '18

Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29581 to look at the new patch set (#5). Change subject: LinuxBoot: refactor payload ...................................................................... LinuxBoot: refactor payload Clean and refactor the structure of the LinuxBoot payload integration. Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/targets/linux.mk M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.inc 5 files changed, 193 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29581/5 -- To view, visit https://review.coreboot.org/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 5 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: LinuxBoot: refactor payload
by Marcello Sylvester Bauer (Code Review) 11 Nov '18

11 Nov '18

Marcello Sylvester Bauer has posted comments on this change. ( https://review.coreboot.org/29581 ) Change subject: LinuxBoot: refactor payload ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/29581/3/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/29581/3/payloads/external/LinuxBoot/Makefil… PS3, Line 18: > $(top) Done -- To view, visit https://review.coreboot.org/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 4 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 11 Nov 2018 18:58:35 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: LinuxBoot: refactor payload
by Marcello Sylvester Bauer (Code Review) 11 Nov '18

11 Nov '18

Hello Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29581 to look at the new patch set (#4). Change subject: LinuxBoot: refactor payload ...................................................................... LinuxBoot: refactor payload Clean and refactor the structure of the LinuxBoot payload integration. Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Signed-off-by: Marcello Sylvester Bauer <info(a)marcellobauer.com> --- M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Makefile A payloads/external/LinuxBoot/targets/linux.mk M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.inc 5 files changed, 193 insertions(+), 97 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29581/4 -- To view, visit https://review.coreboot.org/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 4 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: LinuxBoot: refactor payload
by Philipp Deppenwiese (Code Review) 11 Nov '18

11 Nov '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29581 ) Change subject: LinuxBoot: refactor payload ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/29581/3/payloads/external/LinuxBoot/Makefile File payloads/external/LinuxBoot/Makefile: https://review.coreboot.org/#/c/29581/3/payloads/external/LinuxBoot/Makefil… PS3, Line 18: TOP=../../.. $(top) -- To view, visit https://review.coreboot.org/29581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41d0275a5f7efb920e881f43b0acda29f41ee221 Gerrit-Change-Number: 29581 Gerrit-PatchSet: 3 Gerrit-Owner: Marcello Sylvester Bauer <info(a)marcellobauer.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Sun, 11 Nov 2018 18:37:12 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit November 2018