coreboot-gerrit October 2018

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Change in coreboot[master]: Use macros instead of magic numbers
by Peter Lemenkov (Code Review) 09 Oct '18

09 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28976 to look at the new patch set (#2). Change subject: Use macros instead of magic numbers ...................................................................... Use macros instead of magic numbers Apparently coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Also removed some board names from comments since these functions sometimes are very similar, so no need to add extra difference between them. Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 8 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28976/2 -- To view, visit https://review.coreboot.org/28976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Gerrit-Change-Number: 28976 Gerrit-PatchSet: 2 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Philipp Deppenwiese (Code Review) 09 Oct '18

09 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28774 ) Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... payloads: Only show supported payloads in menuconfig Some payloads don't depend on their supported platforms, which makes them visible in menuconfig even if they are not supported (yet). Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Signed-off-by: Philipp Hug <philipp(a)hug.cx> Reviewed-on: https://review.coreboot.org/28774 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M payloads/Kconfig M payloads/external/FILO/Kconfig.name M payloads/external/linux/Kconfig.name M payloads/external/tianocore/Kconfig.name 4 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Philipp Deppenwiese: Looks good to me, approved diff --git a/payloads/Kconfig b/payloads/Kconfig index 8e05df3..c7a7ba6 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,6 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" + depends on ARCH_ARM64 select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -41,6 +42,7 @@ config PAYLOAD_BAYOU bool "Bayou" + depends on ARCH_X86 help Select this option if you want to set bayou as your primary payload. diff --git a/payloads/external/FILO/Kconfig.name b/payloads/external/FILO/Kconfig.name index ca94343..28a41dc 100644 --- a/payloads/external/FILO/Kconfig.name +++ b/payloads/external/FILO/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_FILO bool "FILO" + depends on ARCH_X86 help Select this option if you want to build a coreboot image with a FILO payload. If you don't know what this is diff --git a/payloads/external/linux/Kconfig.name b/payloads/external/linux/Kconfig.name index ae1d906..63621d8 100644 --- a/payloads/external/linux/Kconfig.name +++ b/payloads/external/linux/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_LINUX bool "A Linux payload" + depends on ARCH_X86 || ARCH_ARM help Select this option if you have a Linux bzImage which coreboot should run as soon as the basic hardware initialization diff --git a/payloads/external/tianocore/Kconfig.name b/payloads/external/tianocore/Kconfig.name index e57925f..a56d248 100644 --- a/payloads/external/tianocore/Kconfig.name +++ b/payloads/external/tianocore/Kconfig.name @@ -1,5 +1,6 @@ config PAYLOAD_TIANOCORE bool "Tianocore coreboot payload package" + depends on ARCH_X86 help Select this option if you want to build a coreboot image with a Tianocore payload. If you don't know what this is -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: payloads: Only show supported payloads in menuconfig
by Philipp Deppenwiese (Code Review) 09 Oct '18

09 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28774 ) Change subject: payloads: Only show supported payloads in menuconfig ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/28774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia1ec0f0ca0b6521d0c024500c67326337f3d744f Gerrit-Change-Number: 28774 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 11:29:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Use macros instead of magic numbers
by Peter Lemenkov (Code Review) 09 Oct '18

09 Oct '18

Peter Lemenkov has uploaded this change for review. ( https://review.coreboot.org/28976 Change subject: Use macros instead of magic numbers ...................................................................... Use macros instead of magic numbers Coreboot still uses magic numbers instead of macros in some Lenovo mainboards. Let's use macros instead. Also removed some board names from comments since these functions sometimes are very similar, so no need to add extra difference between them. Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> --- M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 8 files changed, 26 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/28976/1 diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 0f6ffed..1122e1c 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -25,16 +25,21 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + /* EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse, FDD, LPT */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + FDD_LPC_EN | LPT_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1611); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0x040069); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x0c0701); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x000000); } void mainboard_rcba_config(void) { - RCBA32(0x3414) = 0x00000000; + RCBA32(BUC) = 0; } const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 0, -1 }, diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 7e002d4..8447fef 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -32,18 +32,18 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); + pci_write_config16(PCH_LPC_DEV, LPC_EN, MC_LPC_EN | KBC_LPC_EN); + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x00000); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc0701); + pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0xc0069); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0xc06a1); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Memory map KB9012 EC registers */ pci_write_config32( - PCI_DEV(0, 0x1f, 0), 0x98, + PCH_LPC_DEV, 0x98, CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0); + pci_write_config16(PCH_LPC_DEV, 0xd8, 0xffc0); /* Enable external USB port power. */ if (IS_ENABLED(CONFIG_USBDEBUG)) @@ -53,7 +53,7 @@ void mainboard_rcba_config(void) { /* Disable devices. */ - RCBA32(0x3414) = 0x00000020; + RCBA32(BUC) = 0x00000020; } const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 0 }, diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 4fcd651..8769f01 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -63,7 +63,7 @@ void pch_enable_lpc(void) { - /* T520 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 88e07c1..ac8c514 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -55,7 +55,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index a34d1db..bd1c6a3 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -36,7 +36,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8752949..b6efbd7 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -45,7 +45,7 @@ static void pch_enable_lpc(void) { - /* X201 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 96e0284..fb25f79 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -36,7 +36,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 1ddaedf..91b90d2 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -34,7 +34,7 @@ void pch_enable_lpc(void) { - /* X230 EC Decode Range Port60/64, Port62/66 */ + /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); -- To view, visit https://review.coreboot.org/28976 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a Gerrit-Change-Number: 28976 Gerrit-PatchSet: 1 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com>

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Change in coreboot[master]: dynamic UART initialization for cavium cn8100
by Patrick Rudolph (Code Review) 09 Oct '18

09 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28975 ) Change subject: dynamic UART initialization for cavium cn8100 ...................................................................... Patch Set 1: (4 comments) Tested on hardware ? https://review.coreboot.org/#/c/28975/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28975/1//COMMIT_MSG@7 PS1, Line 7: dynamic UART initialization for cavium cn8100 Add prefix: soc/cavium: https://review.coreboot.org/#/c/28975/1//COMMIT_MSG@8 PS1, Line 8: missing commit body https://review.coreboot.org/#/c/28975/1/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/28975/1/src/soc/cavium/cn81xx/soc.c@395 PS1, Line 395: struct device *child; struct device *dev; https://review.coreboot.org/#/c/28975/1/src/soc/cavium/cn81xx/soc.c@397 PS1, Line 397: child = dev_find_slot(1, PCI_DEVFN(8, i)); Add comment: using device enable state from devicetree.cb ? -- To view, visit https://review.coreboot.org/28975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Gerrit-Change-Number: 28975 Gerrit-PatchSet: 1 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Oct 2018 11:17:23 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: dynamic UART initialization for cavium cn8100
by Jens Drenhaus (Code Review) 09 Oct '18

09 Oct '18

Jens Drenhaus has uploaded this change for review. ( https://review.coreboot.org/28975 Change subject: dynamic UART initialization for cavium cn8100 ...................................................................... dynamic UART initialization for cavium cn8100 Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/opencellular/elgon/mainboard.c M src/soc/cavium/cn81xx/soc.c 3 files changed, 27 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28975/1 diff --git a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c index 28a3ee3..ce896f2 100644 --- a/src/mainboard/cavium/cn8100_sff_evb/mainboard.c +++ b/src/mainboard/cavium/cn8100_sff_evb/mainboard.c @@ -83,12 +83,6 @@ { size_t i; - /* Init UARTs */ - for (i = 0; i < 4; i++) { - if (!uart_is_enabled(i)) - uart_setup(i, 0); - } - /* Init timer */ soc_timer_init(); diff --git a/src/mainboard/opencellular/elgon/mainboard.c b/src/mainboard/opencellular/elgon/mainboard.c index dc06bdc..45a7155 100644 --- a/src/mainboard/opencellular/elgon/mainboard.c +++ b/src/mainboard/opencellular/elgon/mainboard.c @@ -101,12 +101,6 @@ { size_t i; - /* Init UARTs */ - for (i = 0; i < 4; i++) { - if (!uart_is_enabled(i)) - uart_setup(i, 0); - } - /* Init timer */ soc_timer_init(); diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index d9eb052..2e9d837 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -24,6 +24,7 @@ #include <soc/clock.h> #include <soc/sdram.h> #include <soc/timer.h> +#include <soc/uart.h> #include <stddef.h> #include <stdlib.h> #include <string.h> @@ -207,6 +208,21 @@ printk(BIOS_ERR, "%s: Node not found. OS might miss-behave !\n", __func__); + /* Remove unused UART entries */ + for (i = 0; i < 4; i++) { + char path[32]; + const uint64_t addr = UAAx_PF_BAR0(i); + /* Remove the node */ + snprintf(path, sizeof(path), "soc@0/serial@%llx", addr); + dt_node = dt_find_node_by_path(tree->root, path, NULL, NULL, 0); + if (!dt_node || uart_is_enabled(i)) { + printk(BIOS_INFO, "%s: ignoring %s\n", __func__, path); + continue; + } + printk(BIOS_INFO, "%s: Removing node %s\n", __func__, path); + list_remove(&dt_node->list_node); + } + /* Remove unused PEM entries */ for (i = 0; i < 8; i++) { char path[32]; @@ -374,6 +390,17 @@ } } + /* Init UARTs */ + size_t i; + struct device *child; + for (i = 0; i <= 3; i++) { + child = dev_find_slot(1, PCI_DEVFN(8, i)); + if (child && child->enabled) { + if (!uart_is_enabled(i)) + uart_setup(i, 0); + } + } + if (IS_ENABLED(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE)) soc_init_atf(); } -- To view, visit https://review.coreboot.org/28975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Gerrit-Change-Number: 28975 Gerrit-PatchSet: 1 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD
by Furquan Shaikh (Code Review) 09 Oct '18

09 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/28974 ) Change subject: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Gerrit-Change-Number: 28974 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 09 Oct 2018 06:43:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD
by Chris Zhou (Code Review) 09 Oct '18

09 Oct '18

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/28974 Change subject: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD ...................................................................... mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9) BUG=b:112679174 TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- A src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex M src/mainboard/google/poppy/variants/nami/Makefile.inc 2 files changed, 33 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/28974/1 diff --git a/src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex b/src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex new file mode 100644 index 0000000..03547a9 --- /dev/null +++ b/src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex @@ -0,0 +1,32 @@ +23 11 0C 03 85 21 00 08 00 60 00 03 01 03 00 00 +00 00 07 0D F8 0F 00 00 6E 6E 6E 11 00 6E F0 0A +20 08 00 05 00 A8 1B 28 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 16 36 0B 35 +16 36 0B 35 00 00 16 36 0B 35 16 36 0B 35 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 E7 D6 89 02 +0F 11 1F 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 66 CB +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +80 CE 00 00 00 00 00 00 00 4D 34 37 31 41 31 4B +34 34 42 4D 30 2D 43 52 43 20 20 20 20 00 80 CE +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index b02b7d4..ae33c27 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -10,7 +10,7 @@ SPD_SOURCES += hynix_dimm_H5AN8G6NAFR-UHC # 0b0110 SPD_SOURCES += samsung_dimm_K4A4G165WE-BCRC # 0b0111 SPD_SOURCES += samsung_dimm_K4A8G165WC-BCTD # 0b1000 -SPD_SOURCES += empty_ddr4 # 0b1001 +SPD_SOURCES += samsung_dimm_K4AAG165WB-MCRC # 0b1001 SPD_SOURCES += empty_ddr4 # 0b1010 SPD_SOURCES += empty_ddr4 # 0b1011 SPD_SOURCES += empty_ddr4 # 0b1100 -- To view, visit https://review.coreboot.org/28974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Gerrit-Change-Number: 28974 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com>

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Change in coreboot[master]: mb/google/octopus: STYLUS EMR PEN I2C bus 0 CLK frequency(401KHz)over...
by Peichao Li (Code Review) 09 Oct '18

09 Oct '18

Peichao Li has uploaded this change for review. ( https://review.coreboot.org/28973 Change subject: mb/google/octopus: STYLUS EMR PEN I2C bus 0 CLK frequency(401KHz)over spec(＜400KHz) ...................................................................... mb/google/octopus: STYLUS EMR PEN I2C bus 0 CLK frequency(401KHz)over spec(＜400KHz) Need to tune I2C bus 0 clock frequency under the 400KHz Bug=b:117297214 TEST=flash coreboot to the DUT and measure I2C bus 0 clock frequency whether under 400KHz Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Signed-off-by: Peichao.Wang <peichao.wang(a)bitland.corp-partner.google.com> --- M src/mainboard/google/octopus/variants/phaser/overridetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/28973/1 diff --git a/src/mainboard/google/octopus/variants/phaser/overridetree.cb b/src/mainboard/google/octopus/variants/phaser/overridetree.cb index 2f6915e..3a208ea 100644 --- a/src/mainboard/google/octopus/variants/phaser/overridetree.cb +++ b/src/mainboard/google/octopus/variants/phaser/overridetree.cb @@ -20,8 +20,8 @@ }, .i2c[0] = { .speed = I2C_SPEED_FAST, - .rise_time_ns = 152, - .fall_time_ns = 30, + .rise_time_ns = 66, + .fall_time_ns = 90, }, .i2c[5] = { .speed = I2C_SPEED_FAST, -- To view, visit https://review.coreboot.org/28973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9 Gerrit-Change-Number: 28973 Gerrit-PatchSet: 1 Gerrit-Owner: Peichao Li <peichao.wang(a)bitland.corp-partner.google.com>

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Change in coreboot[master]: riscv: add physical memory protection (PMP) support
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28569 ) Change subject: riscv: add physical memory protection (PMP) support ...................................................................... Patch Set 8: (9 comments) https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c File src/arch/riscv/pmp.c: https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@82 PS8, Line 82: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@87 PS8, Line 87: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@92 PS8, Line 92: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@97 PS8, Line 97: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@106 PS8, Line 106: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@111 PS8, Line 111: new = (old & ~((uintptr_t)0xff << shift)) | ((cfg & 0xff) << shift); line over 80 characters https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@117 PS8, Line 117: die("write_pmpcfg failure!"); Prefer using '"%s...", __func__' to using 'write_pmpcfg', this function's name, in a string https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@123 PS8, Line 123: switch(idx) { space required before the open parenthesis '(' https://review.coreboot.org/#/c/28569/8/src/arch/riscv/pmp.c@214 PS8, Line 214: die("write_pmpaddr failure"); Prefer using '"%s...", __func__' to using 'write_pmpaddr', this function's name, in a string -- To view, visit https://review.coreboot.org/28569 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2e9e0c94e6518f63ade7680a3ce68bacfae219d4 Gerrit-Change-Number: 28569 Gerrit-PatchSet: 8 Gerrit-Owner: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Shawn Chang <citypw(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 04:15:52 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit October 2018