coreboot-gerrit October 2018

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Change in coreboot[master]: mediatek/mt8183: Add DDR driver of software impedance part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28837 Change subject: mediatek/mt8183: Add DDR driver of software impedance part ...................................................................... mediatek/mt8183: Add DDR driver of software impedance part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 132 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28837/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 3cd845d..e9b5f42 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -21,6 +21,7 @@ verstage-y += ../common/wdt.c romstage-y += ../common/cbmem.c emi.c +romstage-y += dramc_pi_basic_api.c romstage-y += memory.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c new file mode 100644 index 0000000..4c95814 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <delay.h> +#include <soc/emi.h> +#include <soc/dramc_register.h> +#include <soc/dramc_pi_api.h> + +static void sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) +{ + u8 vref_sel = 0; + + if (term_option == 1) { + vref_sel = IMP_LP4X_TERM_VREF_SEL; + } else { + if (impcal_stage == IMPCAL_STAGE_DRVP) + vref_sel = IMP_DRVP_LP4X_UNTERM_VREF_SEL; + else if (impcal_stage == IMPCAL_STAGE_DRVN) + vref_sel = IMP_DRVN_LP4X_UNTERM_VREF_SEL; + else + vref_sel = IMP_TRACK_LP4X_UNTERM_VREF_SEL; + } + + dramc_dbg("[%s] IMP_VREF_SEL 0x%x\n", __func__, vref_sel); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x3f << 8, vref_sel << 8); +} + +void dramc_sw_impedance(const struct sdram_params *params) +{ + u32 broadcast_bak = dramc_get_broadcast(); + u8 term = 0, ca_term = ODT_OFF, dq_term = ODT_ON; + u32 sw_impedance[2][4] = { {0}, {0} }; + + for (term = 0; term < 2; term++) + for (u8 i = 0; i < 4; i++) + sw_impedance[term][i] = params->impedance[term][i]; + + sw_impedance[ODT_OFF][2] = sw_impedance[ODT_ON][2]; + sw_impedance[ODT_OFF][3] = sw_impedance[ODT_ON][3]; + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0xFF, 0x3); + + /* Set IMP_VREF_SEL value for DRVP */ + sw_imp_cal_vref_sel(dq_term, IMPCAL_STAGE_DRVP); + + /* DQ */ + clrsetbits_le32(&ch[0].ao.shu[0].drving[0], (0x1F << 5) | (0x1F << 0), + (sw_impedance[dq_term][0] << 5) | + (sw_impedance[dq_term][1] << 0)); + clrsetbits_le32(&ch[0].ao.shu[0].drving[1], + (0x1F << 25)|(0x1F << 20) | (1 << 31), + (sw_impedance[dq_term][0] << 25) | + (sw_impedance[dq_term][1] << 20) | (!dq_term << 31)); + clrsetbits_le32(&ch[0].ao.shu[0].drving[2], (0x1F << 5) | (0x1F << 0), + (sw_impedance[dq_term][2] << 5) | + (sw_impedance[dq_term][3] << 0)); + clrsetbits_le32(&ch[0].ao.shu[0].drving[3], (0x1F << 25) | (0x1F << 20), + (sw_impedance[dq_term][2] << 25) | + (sw_impedance[dq_term][3] << 20)); + + /* DQS */ + for (u8 i = 0; i <= 2; i += 2) { + clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + (0x1F << 25) | (0x1F << 20), + (sw_impedance[dq_term][i] << 25) | + (sw_impedance[dq_term][i + 1] << 20)); + clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + (0x1F << 15) | (0x1F << 10), + (sw_impedance[dq_term][i] << 15) | + (sw_impedance[dq_term][i + 1] << 10)); + } + + /* CMD & CLK */ + for (u8 i = 1; i <= 3; i += 2) { + clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + (0x1F << 15) | (0x1F << 10), + (sw_impedance[ca_term][i - 1] << 15) | + (sw_impedance[ca_term][i] << 10)); + clrsetbits_le32(&ch[0].ao.shu[0].drving[i], + (0x1F << 5) | (0x1F << 0), + (sw_impedance[ca_term][i - 1] << 5) | + (sw_impedance[ca_term][i] << 0)); + } + + /* RG_TX_*RCKE_DRVP/RG_TX_*RCKE_DRVN doesn't set, so set 0xA first */ + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 17, + sw_impedance[ca_term][0] << 17); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[11], 0x1f << 22, + sw_impedance[ca_term][1] << 22); + /* DRVP[4:0] = RG_TX_ARCMD_PU_PRE<1:0>, RG_TX_ARCLK_DRVN_PRE<2:0> */ + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[3], + SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_MASK, + (((8 >> 3) & 0x3) << SHU1_CA_CMD3_RG_TX_ARCMD_PU_PRE_SHIFT)); + clrsetbits_le32(&ch[0].phy.shu[0].ca_cmd[0], + SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_MASK, + ((8 & 0x7) << SHU1_CA_CMD0_RG_TX_ARCLK_DRVN_PRE_SHIFT)); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + clrsetbits_le32(&ch[0].phy.shu[0].ca_dll[1], 0x1F << 16, 0x9 << 16); + clrsetbits_le32(&ch[1].phy.shu[0].ca_dll[1], 0x1F << 16, 0x9 << 16); + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + for (term = 0; term < 2; term++) { + dramc_show("term=%d, Reg: DRVP=%d, DRVN=%d, ODTN=%d\n", + term, sw_impedance[term][0], + sw_impedance[term][1], sw_impedance[term][3]); + } + dramc_set_broadcast(broadcast_bak); +} + diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 7008ccc..37997aa 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -287,6 +287,7 @@ dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); + dramc_sw_impedance(params); dramc_init(); emi_init2(params); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index e24bd6c..af96316 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -39,6 +39,11 @@ #define DRAMC_BROADCAST_OFF 0x0 #define MAX_BACKUP_REG_CNT 32 +#define IMP_LP4X_TERM_VREF_SEL 0x1b +#define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a +#define IMP_DRVN_LP4X_UNTERM_VREF_SEL 0x16 +#define IMP_TRACK_LP4X_UNTERM_VREF_SEL 0x1a + enum dram_te_op { TE_OP_WRITE_READ_CHECK = 0, TE_OP_READ_CHECK @@ -132,4 +137,5 @@ void dramc_get_rank_size(u64 *dram_rank_size); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); +void dramc_sw_impedance(const struct sdram_params *params); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/28837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3 Gerrit-Change-Number: 28837 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mediatek/mt8183: using a array do dram init sequence
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28836 Change subject: mediatek/mt8183: using a array do dram init sequence ...................................................................... mediatek/mt8183: using a array do dram init sequence the init sequence of dram just setting the register value only, not have logic processing, so can replace by using a array to config those settings. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Iacd3ce909ba7a0bdf699c5bfcb2b97f383d7bb6f Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/emi.c A src/soc/mediatek/mt8183/include/soc/dramc_init_setting.h 2 files changed, 1,155 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/28836/1 diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 6c36feb..7008ccc 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -18,6 +18,7 @@ #include <soc/infracfg.h> #include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_init_setting.h> struct emi_regs *emi_regs = (void *)EMI_BASE; const u8 phy_mapping[CHANNEL_MAX][16] = { @@ -273,6 +274,12 @@ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 31)); } +static void dramc_init(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_settings); i++) + write32(init_settings[i].addr, init_settings[i].value); +} + static void init_dram(const struct sdram_params *params) { global_option_init(params); @@ -281,6 +288,7 @@ dramc_set_broadcast(DRAMC_BROADCAST_ON); dramc_init_pre_settings(); + dramc_init(); emi_init2(params); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_init_setting.h b/src/soc/mediatek/mt8183/include/soc/dramc_init_setting.h new file mode 100644 index 0000000..e1dfa41 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_init_setting.h @@ -0,0 +1,1147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRAMC_INIT_SETTING_H_ +#define _DRAMC_INIT_SETTING_H_ + +struct value_map { + u32 *addr; + u32 value; +}; + +struct value_map init_settings[] = { + {(void *)0x100010b4, 0x00000000}, + {(void *)0x1022a04c, 0x20712000}, + {(void *)0x1023204c, 0x20712000}, + {(void *)0x1022a024, 0x00100480}, + {(void *)0x10232024, 0x00100480}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228308, 0x00000003}, + {(void *)0x10230308, 0x00000003}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x10228284, 0x00000101}, + {(void *)0x10228284, 0x00000101}, + {(void *)0x1022829c, 0x38010000}, + {(void *)0x10228278, 0x00000000}, + {(void *)0x1022827c, 0x00000000}, + {(void *)0x10228274, 0x00000000}, + {(void *)0x1022828c, 0x006003BF}, + {(void *)0x10228294, 0x333F3F00}, + {(void *)0x10228d84, 0x0000001F}, + {(void *)0x10228c1c, 0x00000010}, + {(void *)0x10228c9c, 0x00000000}, + {(void *)0x10228d90, 0xE57800FF}, + {(void *)0x10228d98, 0xE57800FF}, + {(void *)0x10228db8, 0x00000000}, + {(void *)0x10228dd0, 0x00000000}, + {(void *)0x102281a0, 0x00000000}, + {(void *)0x102280a0, 0x00000000}, + {(void *)0x10228120, 0x00000000}, + {(void *)0x102280bc, 0x10000000}, + {(void *)0x1022813c, 0x10000000}, + {(void *)0x102281c0, 0x00000000}, + {(void *)0x102285f0, 0x10000022}, + {(void *)0x10228670, 0x10000022}, + {(void *)0x102285f0, 0x10000222}, + {(void *)0x10228670, 0x10000222}, + {(void *)0x10228608, 0x20000000}, + {(void *)0x10228808, 0x20000000}, + {(void *)0x10228c14, 0x0030000E}, + {(void *)0x10228604, 0x00020002}, + {(void *)0x10228608, 0xB0800000}, + {(void *)0x10228804, 0x00020002}, + {(void *)0x10228808, 0xB0800000}, + {(void *)0x10228688, 0x20000000}, + {(void *)0x10228888, 0x20000000}, + {(void *)0x10228c94, 0x0030000E}, + {(void *)0x10228684, 0x00020002}, + {(void *)0x10228688, 0xB0800000}, + {(void *)0x10228884, 0x00020002}, + {(void *)0x10228888, 0xB0800000}, + {(void *)0x102285f0, 0x00000222}, + {(void *)0x10228670, 0x00000222}, + {(void *)0x102280bc, 0x10000001}, + {(void *)0x10228e1c, 0x001F1F00}, + {(void *)0x10228f1c, 0x001F1F00}, + {(void *)0x102280a8, 0x00001010}, + {(void *)0x102280ac, 0x00110E10}, + {(void *)0x102280b0, 0x010310C0}, + {(void *)0x102280ac, 0x02110E00}, + {(void *)0x1022813c, 0x10000001}, + {(void *)0x10228e6c, 0x001F1F00}, + {(void *)0x10228f6c, 0x001F1F00}, + {(void *)0x10228128, 0x00001010}, + {(void *)0x1022812c, 0x00110E10}, + {(void *)0x10228130, 0x010310C0}, + {(void *)0x1022812c, 0x02110E00}, + {(void *)0x102281a4, 0x0000008C}, + {(void *)0x102281b0, 0x00020000}, + {(void *)0x10228008, 0x00000011}, + {(void *)0x102280a4, 0x00000008}, + {(void *)0x10228124, 0x00000008}, + {(void *)0x10228da0, 0x00040000}, + {(void *)0x10228da4, 0x00000000}, + {(void *)0x10228dac, 0x00000000}, + {(void *)0x10228da8, 0x00040000}, + {(void *)0x1022800c, 0x000C0000}, + {(void *)0x10228d80, 0x00000003}, + {(void *)0x10228184, 0x00200000}, + {(void *)0x102280a4, 0x0000040E}, + {(void *)0x10228124, 0x0000040E}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228d34, 0x00666009}, + {(void *)0x10230d34, 0x00666009}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x10228c34, 0xC0778608}, + {(void *)0x10228cb4, 0xC0778608}, + {(void *)0x10228d14, 0x00000000}, + {(void *)0x10228d00, 0x00104010}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228d18, 0x000000C0}, + {(void *)0x10230d18, 0x00000040}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x10228c18, 0x00000040}, + {(void *)0x10228c98, 0x00000040}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228270, 0x00050909}, + {(void *)0x10230270, 0x00090909}, + {(void *)0x10228d38, 0x00090004}, + {(void *)0x10230d38, 0x00090001}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x10228c38, 0x00000001}, + {(void *)0x10228cb8, 0x00000001}, + {(void *)0x10228004, 0x00000000}, + {(void *)0x10228284, 0x0000000F}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228d18, 0x000604C0}, + {(void *)0x10230d18, 0x00060440}, + {(void *)0x10228d38, 0x0004E104}, + {(void *)0x10228c18, 0x00060440}, + {(void *)0x10228c38, 0x00022401}, + {(void *)0x10228c98, 0x00060440}, + {(void *)0x10228cb8, 0x00022401}, + {(void *)0x10230d38, 0x0004E101}, + {(void *)0x10230c18, 0x00060440}, + {(void *)0x10230c38, 0x00022401}, + {(void *)0x10230c98, 0x00060440}, + {(void *)0x10230cb8, 0x00022401}, + {(void *)0x10228d90, 0xE5780000}, + {(void *)0x10228d98, 0xE5780000}, + {(void *)0x10228270, 0x00050909}, + {(void *)0x10228308, 0x00000003}, + {(void *)0x10228d00, 0x00144010}, + {(void *)0x1022a210, 0x00000000}, + {(void *)0x10228d34, 0x00698619}, + {(void *)0x10228d38, 0x0004E104}, + {(void *)0x10228d18, 0x000604C0}, + {(void *)0x102280b4, 0x00000055}, + {(void *)0x10228134, 0x00000055}, + {(void *)0x102281b4, 0x00000055}, + {(void *)0x102281a0, 0x00200000}, + {(void *)0x10228284, 0x0000000F}, + {(void *)0x10228c18, 0x00060440}, + {(void *)0x10228c98, 0x00060440}, + {(void *)0x10228d18, 0x000604C0}, + {(void *)0x1022800c, 0x000C0000}, + {(void *)0x10228000, 0x00000000}, + {(void *)0x10228004, 0x00000000}, + {(void *)0x10228188, 0x00000000}, + {(void *)0x10228088, 0x00000000}, + {(void *)0x10228108, 0x00000000}, + {(void *)0x10228088, 0x880AEC00}, + {(void *)0x10228108, 0x880AEC00}, + {(void *)0x10228188, 0x880BAC00}, + {(void *)0x10228180, 0x00000000}, + {(void *)0x10228080, 0x00000000}, + {(void *)0x10228100, 0x00000000}, + {(void *)0x10228da0, 0x00040000}, + {(void *)0x10228da8, 0x00040000}, + {(void *)0x10228d94, 0x7B000002}, + {(void *)0x10228d9c, 0x7B000002}, + {(void *)0x10228180, 0x00000002}, + {(void *)0x10228080, 0x00000002}, + {(void *)0x10228100, 0x00000002}, + {(void *)0x10228184, 0x00200000}, + {(void *)0x10228084, 0x00000000}, + {(void *)0x10228104, 0x00000000}, + {(void *)0x10228c18, 0x02860440}, + {(void *)0x10228c98, 0x02860440}, + {(void *)0x10228d18, 0x028604C0}, + {(void *)0x10228180, 0x0000000A}, + {(void *)0x10228080, 0x0000000A}, + {(void *)0x10228100, 0x0000000A}, + {(void *)0x10228000, 0x80000000}, + {(void *)0x10228004, 0x80000000}, + {(void *)0x1022800c, 0x004D0000}, + {(void *)0x10228c18, 0x06860440}, + {(void *)0x10228c98, 0x06860440}, + {(void *)0x10228d18, 0x068604C0}, + {(void *)0x1022818c, 0x000BA000}, + {(void *)0x1022808c, 0x0002E800}, + {(void *)0x1022810c, 0x0002E800}, + {(void *)0x10228188, 0x00000800}, + {(void *)0x10228088, 0x00000800}, + {(void *)0x10228108, 0x00000800}, + {(void *)0x10228188, 0x00000800}, + {(void *)0x10228088, 0x00000000}, + {(void *)0x10228108, 0x00000000}, + {(void *)0x10228284, 0x0000001F}, + {(void *)0x10228188, 0x00000801}, + {(void *)0x10228088, 0x00000001}, + {(void *)0x10228108, 0x00000001}, + {(void *)0x102281a0, 0x00000000}, + {(void *)0x102280b4, 0x00000040}, + {(void *)0x10228134, 0x00000040}, + {(void *)0x102281b4, 0x00000040}, + {(void *)0x1022a024, 0x00100400}, + {(void *)0x10232024, 0x00100400}, + {(void *)0x10228d94, 0x7B000003}, + {(void *)0x10228d9c, 0x7B000003}, + {(void *)0x10228db8, 0x00000002}, + {(void *)0x10228dd0, 0x00000002}, + {(void *)0x10228db8, 0x02080002}, + {(void *)0x10228dd0, 0x02080002}, + {(void *)0x10228dbc, 0x0C030000}, + {(void *)0x10228dd4, 0x0C030000}, + {(void *)0x10230d90, 0x00000000}, + {(void *)0x10230d98, 0x00000000}, + {(void *)0x10230270, 0x00090909}, + {(void *)0x10230308, 0x00000003}, + {(void *)0x10230d00, 0x00144010}, + {(void *)0x10232210, 0x00000000}, + {(void *)0x10230d34, 0xC0778609}, + {(void *)0x10230d38, 0x0004E101}, + {(void *)0x10230d18, 0x00060440}, + {(void *)0x102300b4, 0x00000055}, + {(void *)0x10230134, 0x00000055}, + {(void *)0x102301b4, 0x00000055}, + {(void *)0x102301a0, 0x00200000}, + {(void *)0x10230284, 0x0000000F}, + {(void *)0x10230c18, 0x00060440}, + {(void *)0x10230c98, 0x00060440}, + {(void *)0x10230d18, 0x00060440}, + {(void *)0x1023000c, 0x00000000}, + {(void *)0x10230000, 0x00000000}, + {(void *)0x10230004, 0x00000000}, + {(void *)0x10230188, 0x00000000}, + {(void *)0x10230088, 0x00000000}, + {(void *)0x10230108, 0x00000000}, + {(void *)0x10230088, 0x880AEC00}, + {(void *)0x10230108, 0x880AEC00}, + {(void *)0x10230188, 0x880BAC00}, + {(void *)0x10230180, 0x00000000}, + {(void *)0x10230080, 0x00000000}, + {(void *)0x10230100, 0x00000000}, + {(void *)0x10230da0, 0x00040000}, + {(void *)0x10230da8, 0x00040000}, + {(void *)0x10230d94, 0x7B000000}, + {(void *)0x10230d9c, 0x7B000000}, + {(void *)0x10230180, 0x00000002}, + {(void *)0x10230080, 0x00000002}, + {(void *)0x10230100, 0x00000002}, + {(void *)0x10230184, 0x00200000}, + {(void *)0x10230084, 0x00000000}, + {(void *)0x10230104, 0x00000000}, + {(void *)0x10230c18, 0x02860440}, + {(void *)0x10230c98, 0x02860440}, + {(void *)0x10230d18, 0x02860440}, + {(void *)0x10230180, 0x0000000A}, + {(void *)0x10230080, 0x0000000A}, + {(void *)0x10230100, 0x0000000A}, + {(void *)0x10230000, 0x80000000}, + {(void *)0x10230004, 0x80000000}, + {(void *)0x1023000c, 0x00410000}, + {(void *)0x10230c18, 0x06860440}, + {(void *)0x10230c98, 0x06860440}, + {(void *)0x10230d18, 0x06860440}, + {(void *)0x1023018c, 0x0003A000}, + {(void *)0x1023008c, 0x0002E800}, + {(void *)0x1023010c, 0x0002E800}, + {(void *)0x10230188, 0x00000800}, + {(void *)0x10230088, 0x00000800}, + {(void *)0x10230108, 0x00000800}, + {(void *)0x10230188, 0x00000800}, + {(void *)0x10230088, 0x00000000}, + {(void *)0x10230108, 0x00000000}, + {(void *)0x10230284, 0x0000001F}, + {(void *)0x10230188, 0x00000801}, + {(void *)0x10230088, 0x00000001}, + {(void *)0x10230108, 0x00000001}, + {(void *)0x102301a0, 0x00000000}, + {(void *)0x102300b4, 0x00000040}, + {(void *)0x10230134, 0x00000040}, + {(void *)0x102301b4, 0x00000040}, + {(void *)0x1022a024, 0x00100400}, + {(void *)0x10232024, 0x00100400}, + {(void *)0x10230d94, 0x00000001}, + {(void *)0x10230d9c, 0x00000001}, + {(void *)0x10230db8, 0x00000002}, + {(void *)0x10230dd0, 0x00000002}, + {(void *)0x10230db8, 0x02080000}, + {(void *)0x10230dd0, 0x02080000}, + {(void *)0x10230dbc, 0x0C030000}, + {(void *)0x10230dd4, 0x0C030000}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x1022a028, 0x20080000}, + {(void *)0x1022a024, 0x08100400}, + {(void *)0x1022a004, 0x30822201}, + {(void *)0x1022a064, 0x200007D2}, + {(void *)0x102280bc, 0x10000011}, + {(void *)0x1022813c, 0x10000011}, + {(void *)0x1022ab04, 0x0F0F0F0F}, + {(void *)0x1022a204, 0x00014310}, + {(void *)0x1022ac54, 0x80200608}, + {(void *)0x1022a8a8, 0x14A5294A}, + {(void *)0x1022a8ac, 0x14A5294A}, + {(void *)0x1022a8b0, 0x14A5294A}, + {(void *)0x1022a8b4, 0x14A5294A}, + {(void *)0x1022a0dc, 0x0001D00A}, + {(void *)0x1022a210, 0x00000001}, + {(void *)0x1022a000, 0x04109000}, + {(void *)0x1022a208, 0x70000010}, + {(void *)0x1022a208, 0x50000010}, + {(void *)0x1022a03c, 0x020C0000}, + {(void *)0x102280bc, 0x10100011}, + {(void *)0x1022813c, 0x10100011}, + {(void *)0x102281c0, 0x00000000}, + {(void *)0x1022829c, 0xB901020F}, + {(void *)0x102282a0, 0x8100908C}, + {(void *)0x102302a0, 0x8100908C}, + {(void *)0x102285f0, 0x01000222}, + {(void *)0x10228670, 0x01000222}, + {(void *)0x102286f0, 0x00000000}, + {(void *)0x102281b4, 0x00000000}, + {(void *)0x102280b4, 0x00000000}, + {(void *)0x10228134, 0x00000000}, + {(void *)0x1022a840, 0xA10810BF}, + {(void *)0x1022a860, 0xC0010003}, + {(void *)0x10228c1c, 0x00008010}, + {(void *)0x10228c9c, 0x00008000}, + {(void *)0x1022a04c, 0x25712000}, + {(void *)0x1022a880, 0x00000000}, + {(void *)0x1022a884, 0x00070000}, + {(void *)0x1022a888, 0x00000000}, + {(void *)0x1022a88c, 0x00000000}, + {(void *)0x1022a890, 0x11111011}, + {(void *)0x1022a8a0, 0x33333333}, + {(void *)0x1022a8a4, 0x11114444}, + {(void *)0x1022aa2c, 0x33333333}, + {(void *)0x1022aa30, 0x33333333}, + {(void *)0x1022aa34, 0x11113333}, + {(void *)0x1022aa38, 0x11113333}, + {(void *)0x1022ab2c, 0x33333333}, + {(void *)0x1022ab30, 0x33333333}, + {(void *)0x1022ab34, 0x11113333}, + {(void *)0x1022ab38, 0x11113333}, + {(void *)0x10228e1c, 0x001A1A00}, + {(void *)0x10228f1c, 0x00141400}, + {(void *)0x10228e6c, 0x001A1A00}, + {(void *)0x10228f6c, 0x00141400}, + {(void *)0x102280bc, 0x10100031}, + {(void *)0x102280b0, 0x010350C0}, + {(void *)0x1022813c, 0x10100031}, + {(void *)0x10228130, 0x010350C0}, + {(void *)0x1022a200, 0xF0100000}, + {(void *)0x1022a048, 0x08400000}, + {(void *)0x1022a85c, 0x33210000}, + {(void *)0x1022a878, 0xC0000000}, + {(void *)0x1022a024, 0x88102400}, + {(void *)0x1022a034, 0x00731004}, + {(void *)0x1022a848, 0x9007000F}, + {(void *)0x1022a064, 0x240007D2}, + {(void *)0x1022a0d8, 0x00000040}, + {(void *)0x1022a0d4, 0x0001C110}, + {(void *)0x1022a050, 0x30000700}, + {(void *)0x1022a054, 0x6543B321}, + {(void *)0x1022a004, 0x30822001}, + {(void *)0x1022a008, 0x81080000}, + {(void *)0x1022a00c, 0x00024F13}, + {(void *)0x1022a010, 0x00000080}, + {(void *)0x1022a020, 0x00000009}, + {(void *)0x1022a038, 0x80000106}, + {(void *)0x1022a040, 0x3000000C}, + {(void *)0x1022a04c, 0x25714001}, + {(void *)0x1022a858, 0x64400000}, + {(void *)0x1022aa04, 0x00001919}, + {(void *)0x1022ab04, 0x00001B1B}, + {(void *)0x1022a004, 0x308A2001}, + {(void *)0x1022a058, 0x00000A56}, + {(void *)0x1022a84c, 0x00FF0000}, + {(void *)0x1022a04c, 0x65714001}, + {(void *)0x1022a048, 0x48400000}, + {(void *)0x1022a06c, 0x00020000}, + {(void *)0x1022a038, 0xC0000106}, + {(void *)0x1022a038, 0xC0000107}, + {(void *)0x1022a20c, 0x00010000}, + {(void *)0x1022a204, 0x00014F10}, + {(void *)0x1022a09c, 0x12000480}, + {(void *)0x1022a01c, 0x57000000}, + {(void *)0x1022a01c, 0x17000000}, + {(void *)0x1022a074, 0x00000068}, + {(void *)0x1022a00c, 0x000A4F13}, + {(void *)0x1022a01c, 0x07000000}, + {(void *)0x1022a034, 0x00731804}, + {(void *)0x1022a064, 0x340007D2}, + {(void *)0x1022a20c, 0x00010004}, + {(void *)0x1022a004, 0x308A2000}, + {(void *)0x1022a06c, 0x00020000}, + {(void *)0x1022a8c0, 0xA0000000}, + {(void *)0x10228c1c, 0x00008090}, + {(void *)0x10228c9c, 0x00008080}, + {(void *)0x1022a858, 0x64400000}, + {(void *)0x1022aa2c, 0x33333322}, + {(void *)0x1022aa30, 0x33333322}, + {(void *)0x1022ab2c, 0x33333322}, + {(void *)0x1022ab30, 0x33333322}, + {(void *)0x1022a204, 0x00034F10}, + {(void *)0x1022a204, 0x00014F10}, + {(void *)0x1022a200, 0xFC100001}, + {(void *)0x1022a204, 0x00014F50}, + {(void *)0x1022a8c4, 0x02009800}, + {(void *)0x1022829c, 0xB9010200}, + {(void *)0x1022a850, 0x00000100}, + {(void *)0x1022a200, 0xFC120001}, + {(void *)0x10228c1c, 0x00008090}, + {(void *)0x10228c9c, 0x00008080}, + {(void *)0x1022a850, 0x00000110}, + {(void *)0x1022a850, 0x00000112}, + {(void *)0x1022a050, 0x30000721}, + {(void *)0x1022a0c8, 0x098E0080}, + {(void *)0x1022a01c, 0x00000000}, + {(void *)0x1022a034, 0x00731814}, + {(void *)0x1022a858, 0x64300000}, + {(void *)0x1022a8c0, 0x20000000}, + {(void *)0x1022aa0c, 0x1A1A1A1A}, + {(void *)0x1022ab0c, 0x14141414}, + {(void *)0x1022aa34, 0x33333333}, + {(void *)0x1022aa38, 0x33333333}, + {(void *)0x1022ab34, 0x33333333}, + {(void *)0x1022ab38, 0x33333333}, + {(void *)0x1022ac54, 0x8120050C}, + {(void *)0x10228c1c, 0x00008090}, + {(void *)0x10228c9c, 0x00008080}, + {(void *)0x1022a8d0, 0x00000000}, + {(void *)0x1022a860, 0xC0010003}, + {(void *)0x10228c1c, 0x00008090}, + {(void *)0x10228c9c, 0x00008080}, + {(void *)0x10228608, 0x20000000}, + {(void *)0x10228808, 0x20000000}, + {(void *)0x10228688, 0x20000000}, + {(void *)0x10228888, 0x20000000}, + {(void *)0x10228d1c, 0x00000000}, + {(void *)0x102281a4, 0x0000048C}, + {(void *)0x102281c0, 0x00000020}, + {(void *)0x102281b0, 0x00024000}, + {(void *)0x102280a4, 0x000004EE}, + {(void *)0x10228124, 0x000004EE}, + {(void *)0x102281a4, 0x000004AC}, + {(void *)0x102280a4, 0x000004EC}, + {(void *)0x10228124, 0x000004EC}, + {(void *)0x102280ac, 0x82110E00}, + {(void *)0x1022812c, 0x82110E00}, + {(void *)0x102281ac, 0x80000808}, + {(void *)0x102281b0, 0x00034000}, + {(void *)0x10228268, 0x00000020}, + {(void *)0x102280b0, 0x010352C0}, + {(void *)0x10228130, 0x010352C0}, + {(void *)0x102281b0, 0x00034200}, + {(void *)0x102280b0, 0x010352C1}, + {(void *)0x10228130, 0x010352C1}, + {(void *)0x102281b0, 0x00034201}, + {(void *)0x102281b0, 0x00034241}, + {(void *)0x102280b0, 0x010352C9}, + {(void *)0x10228130, 0x010352C9}, + {(void *)0x102281b0, 0x00034249}, + {(void *)0x102280b0, 0x010352E9}, + {(void *)0x10228130, 0x010352E9}, + {(void *)0x102281b0, 0x00034269}, + {(void *)0x10228c14, 0x0030000E}, + {(void *)0x102280ac, 0x82110E00}, + {(void *)0x10228c94, 0x0030000E}, + {(void *)0x1022812c, 0x82110E00}, + {(void *)0x102280b8, 0x00000007}, + {(void *)0x10228138, 0x00000007}, + {(void *)0x102281bc, 0x00010007}, + {(void *)0x1022a204, 0x00014F70}, + {(void *)0x1022a200, 0xFC120001}, + {(void *)0x102280b0, 0x010392E9}, + {(void *)0x102280bc, 0x10100031}, + {(void *)0x102280bc, 0x10100020}, + {(void *)0x102280bc, 0x10100031}, + {(void *)0x10228130, 0x010392E9}, + {(void *)0x1022813c, 0x10100031}, + {(void *)0x1022813c, 0x10100020}, + {(void *)0x1022813c, 0x10100031}, + {(void *)0x102300b8, 0x00000007}, + {(void *)0x10230138, 0x00000007}, + {(void *)0x102301bc, 0x00010007}, + {(void *)0x10232204, 0x00014F70}, + {(void *)0x10232200, 0xFC120001}, + {(void *)0x102300b0, 0x010392E9}, + {(void *)0x102300bc, 0x10100031}, + {(void *)0x102300bc, 0x10100020}, + {(void *)0x102300bc, 0x10100031}, + {(void *)0x10230130, 0x010392E9}, + {(void *)0x1023013c, 0x10100031}, + {(void *)0x1023013c, 0x10100020}, + {(void *)0x1023013c, 0x10100031}, + {(void *)0x102281b8, 0x00080A0A}, + {(void *)0x102281b8, 0x00080A0A}, + {(void *)0x1022a8cc, 0x0000F132}, + {(void *)0x1022a8c4, 0x02A19800}, + {(void *)0x10228c14, 0x0030000E}, + {(void *)0x10228c94, 0x0030000E}, + {(void *)0x10228d14, 0x00000000}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x10228c18, 0x06860440}, + {(void *)0x10228c98, 0x06860440}, + {(void *)0x10228d18, 0x068604C0}, + {(void *)0x10230c18, 0x06860440}, + {(void *)0x10230c98, 0x06860440}, + {(void *)0x10230d18, 0x06860440}, + {(void *)0x100010b4, 0x0000001F}, + {(void *)0x1022a864, 0x81080004}, + {(void *)0x1022a048, 0x4840F000}, + {(void *)0x1022a218, 0x00020000}, + {(void *)0x1022a8cc, 0x0000F132}, + {(void *)0x10228c20, 0xFFC07FFF}, + {(void *)0x10228ca0, 0xFFC07FFF}, + {(void *)0x10228d20, 0xFFC07FFF}, + {(void *)0x102282a8, 0x15351135}, + {(void *)0x10228c1c, 0x00008090}, + {(void *)0x10228c9c, 0x00008080}, + {(void *)0x1022a03c, 0x020CFFFF}, + {(void *)0x1022ac54, 0x8120050C}, + {(void *)0x1022a0bc, 0x00080000}, + {(void *)0x1022a0d0, 0x01000000}, + {(void *)0x1022a208, 0x50000010}, + {(void *)0x1022a20c, 0x00010704}, + {(void *)0x1022a860, 0xC001000F}, + {(void *)0x10228c34, 0xC0778609}, + {(void *)0x10228cb4, 0xC0778609}, + {(void *)0x10228184, 0x00200000}, + {(void *)0x1022a00c, 0x040ACF13}, + {(void *)0x1022a048, 0x4840F000}, + {(void *)0x1022a0d8, 0x0000001A}, + {(void *)0x102280b0, 0x010392E9}, + {(void *)0x10228130, 0x010392E9}, + {(void *)0x102281b0, 0x000352E9}, + {(void *)0x1022a208, 0x50010010}, + {(void *)0x10228c1c, 0x13008090}, + {(void *)0x10228c9c, 0x13008080}, + {(void *)0x1022a874, 0x00000000}, + {(void *)0x1022a8c4, 0x02A19800}, + {(void *)0x1022aa08, 0x00000000}, + {(void *)0x1022ab08, 0x00000000}, + {(void *)0x1022a850, 0x00000112}, + {(void *)0x102328c4, 0x02A19800}, + {(void *)0x10232a08, 0x00000000}, + {(void *)0x10232b08, 0x00000000}, + {(void *)0x10232850, 0x00000112}, + {(void *)0x102280bc, 0x10100431}, + {(void *)0x1022813c, 0x10100431}, + {(void *)0x102281c0, 0x00000020}, + {(void *)0x10228c20, 0xFFC07FFF}, + {(void *)0x10228ca0, 0xFFC07FFF}, + {(void *)0x10228c38, 0x00022401}, + {(void *)0x10228cb8, 0x00022401}, + {(void *)0x1022a860, 0xC001000F}, + {(void *)0x10228c1c, 0x13008090}, + {(void *)0x10228c9c, 0x13008080}, + {(void *)0x1022a028, 0x20080000}, + {(void *)0x1022a04c, 0x75714001}, + {(void *)0x1022a058, 0x00080A56}, + {(void *)0x1022a0d0, 0x0D000000}, + {(void *)0x1022a0dc, 0x0001D10A}, + {(void *)0x1022a0e0, 0x0B80000D}, + {(void *)0x102282a8, 0x1D351135}, + {(void *)0x10228084, 0x00300000}, + {(void *)0x10228104, 0x00300000}, + {(void *)0x10228184, 0x00300000}, + {(void *)0x1022829c, 0xB1010200}, + {(void *)0x102285e8, 0x00000101}, + {(void *)0x1022a040, 0x3000008C}, + {(void *)0x1022a050, 0x300007A1}, + {(void *)0x1022a0d4, 0x0C01C1D0}, + {(void *)0x1022a0dc, 0x8001DD0A}, + {(void *)0x1022a208, 0x50010000}, + {(void *)0x1022a218, 0x00020000}, + {(void *)0x1022a024, 0x88502400}, + {(void *)0x102281d0, 0xA94011C0}, + {(void *)0x1022a024, 0x88D02400}, + {(void *)0x1022a874, 0x00000000}, + {(void *)0x1022a0a0, 0x0080110D}, + {(void *)0x1022a84c, 0x00FF0005}, + {(void *)0x1022a04c, 0x75774001}, + {(void *)0x1022a0dc, 0x8301DD0A}, + {(void *)0x1022a04c, 0x75774001}, + {(void *)0x1022a004, 0x348A2000}, + {(void *)0x1022a0d0, 0x0D426810}, + {(void *)0x1022a0a0, 0x4080110D}, + {(void *)0x1022a004, 0x348A2000}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x1022a0d4, 0x0C03C1D0}, + {(void *)0x1022a0dc, 0x8301DD0A}, + {(void *)0x102320d4, 0x0C01C1F0}, + {(void *)0x102320dc, 0x8301CD0A}, + {(void *)0x10228ea4, 0x00000000}, + {(void *)0x10228ea0, 0x00000000}, + {(void *)0x10228fa4, 0x00000000}, + {(void *)0x10228fa0, 0x00000000}, + {(void *)0x10228d0c, 0x00000400}, + {(void *)0x10228e04, 0x00110000}, + {(void *)0x10228e54, 0x00110000}, + {(void *)0x10228f04, 0x00110000}, + {(void *)0x10228f54, 0x00110000}, + {(void *)0x10228c38, 0x00022601}, + {(void *)0x10230ea4, 0x00000000}, + {(void *)0x10230ea0, 0x00000000}, + {(void *)0x10230fa4, 0x00000000}, + {(void *)0x10230fa0, 0x00000000}, + {(void *)0x10230d0c, 0x00000400}, + {(void *)0x10230e04, 0x22000000}, + {(void *)0x10230e54, 0x22000000}, + {(void *)0x10230f04, 0x22000000}, + {(void *)0x10230f54, 0x22000000}, + {(void *)0x10230c38, 0x00022501}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x102282a0, 0x8100908C}, + {(void *)0x102302a0, 0x8100908C}, + {(void *)0x1022a024, 0x88D02480}, + {(void *)0x10232024, 0x88D02480}, + {(void *)0x102282a0, 0x8100B08C}, + {(void *)0x102302a0, 0x8100B08C}, + {(void *)0x1022a038, 0xC4000107}, + {(void *)0x10232038, 0xC4000107}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000000}, + {(void *)0x1022a038, 0xC4000107}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000000}, + {(void *)0x1022a06c, 0x00020000}, + {(void *)0x1022a060, 0x00000010}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a060, 0x00000040}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a05c, 0x00000000}, + {(void *)0x1022a038, 0xC4000107}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000D00}, + {(void *)0x1022a05c, 0x00000D18}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000C18}, + {(void *)0x1022a05c, 0x00000C5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0000015D}, + {(void *)0x1022a05c, 0x00000156}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000256}, + {(void *)0x1022a05c, 0x0000020B}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000B0B}, + {(void *)0x1022a05c, 0x00000B00}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00001600}, + {(void *)0x1022a05c, 0x00001638}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000E38}, + {(void *)0x1022a05c, 0x00000E5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0000035D}, + {(void *)0x1022a05c, 0x00000330}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000D30}, + {(void *)0x1022a05c, 0x00000D58}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000C58}, + {(void *)0x1022a05c, 0x00000C5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0000015D}, + {(void *)0x1022a05c, 0x00000156}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000256}, + {(void *)0x1022a05c, 0x0000022D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000B2D}, + {(void *)0x1022a05c, 0x00000B23}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00001623}, + {(void *)0x1022a05c, 0x00001634}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000E34}, + {(void *)0x1022a05c, 0x00000E10}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000310}, + {(void *)0x1022a05c, 0x00000330}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000330}, + {(void *)0x1022a038, 0xC4000107}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x11000330}, + {(void *)0x1022a06c, 0x00020000}, + {(void *)0x1022a060, 0x00000010}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a060, 0x00000040}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a05c, 0x01000330}, + {(void *)0x1022a038, 0xC4000107}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000D30}, + {(void *)0x1022a05c, 0x01000D18}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000C18}, + {(void *)0x1022a05c, 0x01000C5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0100015D}, + {(void *)0x1022a05c, 0x01000156}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000256}, + {(void *)0x1022a05c, 0x0100020B}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000B0B}, + {(void *)0x1022a05c, 0x01000B00}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01001600}, + {(void *)0x1022a05c, 0x01001638}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000E38}, + {(void *)0x1022a05c, 0x01000E5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0100035D}, + {(void *)0x1022a05c, 0x01000330}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000D30}, + {(void *)0x1022a05c, 0x01000D58}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000C58}, + {(void *)0x1022a05c, 0x01000C5D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x0100015D}, + {(void *)0x1022a05c, 0x01000156}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000256}, + {(void *)0x1022a05c, 0x0100022D}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000B2D}, + {(void *)0x1022a05c, 0x01000B23}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01001623}, + {(void *)0x1022a05c, 0x01001634}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000E34}, + {(void *)0x1022a05c, 0x01000E10}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000310}, + {(void *)0x1022a05c, 0x01000330}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000330}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x00000D30}, + {(void *)0x1022a05c, 0x00000DD8}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000DD8}, + {(void *)0x1022a05c, 0x01000DD8}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000DD8}, + {(void *)0x1022a05c, 0x01000DD8}, + {(void *)0x1022a060, 0x00000001}, + {(void *)0x1022a060, 0x00000000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a05c, 0x01000DD8}, + {(void *)0x1022a8d8, 0x00D8000D}, + {(void *)0x1022a8dc, 0x00D8000D}, + {(void *)0x1022a8d4, 0x002D0002}, + {(void *)0x1023205c, 0x00000000}, + {(void *)0x10232038, 0xC4000107}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000000}, + {(void *)0x1023206c, 0x00020000}, + {(void *)0x10232060, 0x00000010}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232060, 0x00000040}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x1023205c, 0x00000000}, + {(void *)0x10232038, 0xC4000107}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000D00}, + {(void *)0x1023205c, 0x00000D18}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000C18}, + {(void *)0x1023205c, 0x00000C5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0000015D}, + {(void *)0x1023205c, 0x00000156}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000256}, + {(void *)0x1023205c, 0x0000020B}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000B0B}, + {(void *)0x1023205c, 0x00000B00}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00001600}, + {(void *)0x1023205c, 0x00001638}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000E38}, + {(void *)0x1023205c, 0x00000E5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0000035D}, + {(void *)0x1023205c, 0x00000330}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000D30}, + {(void *)0x1023205c, 0x00000D58}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000C58}, + {(void *)0x1023205c, 0x00000C5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0000015D}, + {(void *)0x1023205c, 0x00000156}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000256}, + {(void *)0x1023205c, 0x0000022D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000B2D}, + {(void *)0x1023205c, 0x00000B23}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00001623}, + {(void *)0x1023205c, 0x00001634}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000E34}, + {(void *)0x1023205c, 0x00000E10}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000310}, + {(void *)0x1023205c, 0x00000330}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000330}, + {(void *)0x10232038, 0xC4000107}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x11000330}, + {(void *)0x1023206c, 0x00020000}, + {(void *)0x10232060, 0x00000010}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232060, 0x00000040}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x1023205c, 0x01000330}, + {(void *)0x10232038, 0xC4000107}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000D30}, + {(void *)0x1023205c, 0x01000D18}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000C18}, + {(void *)0x1023205c, 0x01000C5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0100015D}, + {(void *)0x1023205c, 0x01000156}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000256}, + {(void *)0x1023205c, 0x0100020B}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000B0B}, + {(void *)0x1023205c, 0x01000B00}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01001600}, + {(void *)0x1023205c, 0x01001638}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000E38}, + {(void *)0x1023205c, 0x01000E5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0100035D}, + {(void *)0x1023205c, 0x01000330}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000D30}, + {(void *)0x1023205c, 0x01000D58}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000C58}, + {(void *)0x1023205c, 0x01000C5D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x0100015D}, + {(void *)0x1023205c, 0x01000156}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000256}, + {(void *)0x1023205c, 0x0100022D}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000B2D}, + {(void *)0x1023205c, 0x01000B23}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01001623}, + {(void *)0x1023205c, 0x01001634}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000E34}, + {(void *)0x1023205c, 0x01000E10}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000310}, + {(void *)0x1023205c, 0x01000330}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000330}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x00000D30}, + {(void *)0x1023205c, 0x00000DD8}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000DD8}, + {(void *)0x1023205c, 0x01000DD8}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000DD8}, + {(void *)0x1023205c, 0x01000DD8}, + {(void *)0x10232060, 0x00000001}, + {(void *)0x10232060, 0x00000000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x1023205c, 0x01000DD8}, + {(void *)0x102328d8, 0x00D8000D}, + {(void *)0x102328dc, 0x00D8000D}, + {(void *)0x102328d4, 0x002D0002}, + {(void *)0x1022a05c, 0x00000DD8}, + {(void *)0x1023205c, 0x00000DD8}, + {(void *)0x100010b4, 0x00000000}, + {(void *)0x1022a800, 0x06020C07}, + {(void *)0x1022a804, 0x10080501}, + {(void *)0x1022a808, 0x07070201}, + {(void *)0x1022a80c, 0x6164002C}, + {(void *)0x1022a810, 0x22650077}, + {(void *)0x1022a814, 0x0A000C0B}, + {(void *)0x1022a81c, 0x05030609}, + {(void *)0x1022a820, 0x000106E1}, + {(void *)0x1022a0b0, 0x0B000000}, + {(void *)0x1022aa00, 0x00000004}, + {(void *)0x1022ab00, 0x00000004}, + {(void *)0x1022a860, 0xC001004F}, + {(void *)0x1022a844, 0x34000D0F}, + {(void *)0x1022a848, 0x9007640F}, + {(void *)0x1022a8c8, 0x4E39EB36}, + {(void *)0x1022a85c, 0x33210000}, + {(void *)0x1022a024, 0x88D02440}, + {(void *)0x1022a858, 0x64300003}, + {(void *)0x1022a858, 0x64301203}, + {(void *)0x10232800, 0x06020C07}, + {(void *)0x10232804, 0x10080501}, + {(void *)0x10232808, 0x07070201}, + {(void *)0x1023280c, 0x6164002C}, + {(void *)0x10232810, 0x22650077}, + {(void *)0x10232814, 0x0A000C0B}, + {(void *)0x1023281c, 0x05030609}, + {(void *)0x10232820, 0x000106E1}, + {(void *)0x102320b0, 0x0B000000}, + {(void *)0x10232a00, 0x00000004}, + {(void *)0x10232b00, 0x00000004}, + {(void *)0x10232860, 0xC001004F}, + {(void *)0x10232844, 0x34000D0F}, + {(void *)0x10232848, 0x9007640F}, + {(void *)0x102328c8, 0x4E39EB36}, + {(void *)0x1023285c, 0x33210000}, + {(void *)0x10232024, 0x88D02440}, + {(void *)0x10232858, 0x64300003}, + {(void *)0x10232858, 0x64301203}, + {(void *)0x1022a010, 0x00000C80}, + {(void *)0x1022a01c, 0x00000000}, + {(void *)0x1022a010, 0x00000C80}, +}; + +#endif /* _DRAMC_INIT_SETTING_H_ */ -- To view, visit https://review.coreboot.org/28836 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iacd3ce909ba7a0bdf699c5bfcb2b97f383d7bb6f Gerrit-Change-Number: 28836 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add EMI init for DDR driver init
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28835 Change subject: mediatek/mt8183: Add EMI init for DDR driver init ...................................................................... mediatek/mt8183: Add EMI init for DDR driver init Add EMI config to initialize memory. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/emi.c A src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h A src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/emi.h A src/soc/mediatek/mt8183/memory.c 6 files changed, 505 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/28835/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 8fece79..3cd845d 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -21,6 +21,7 @@ verstage-y += ../common/wdt.c romstage-y += ../common/cbmem.c emi.c +romstage-y += memory.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index e37fd56..6c36feb 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -13,9 +13,278 @@ * GNU General Public License for more details. */ +#include <arch/io.h> #include <soc/emi.h> +#include <soc/infracfg.h> +#include <soc/dramc_pi_api.h> +#include <soc/dramc_register.h> + +struct emi_regs *emi_regs = (void *)EMI_BASE; +const u8 phy_mapping[CHANNEL_MAX][16] = { + [CHANNEL_A] = { + 1, 0, 2, 4, 3, 7, 5, 6, + 9, 8, 12, 11, 10, 15, 13, 14 + }, + + [CHANNEL_B] = { + 0, 1, 5, 6, 3, 7, 4, 2, + 9, 8, 12, 15, 11, 14, 13, 10 + } +}; + +void dramc_set_broadcast(u32 bOnOff) +{ + write32(&mt8183_infracfg->dramc_wbr, bOnOff); +} + +u32 dramc_get_broadcast(void) +{ + return read32(&mt8183_infracfg->dramc_wbr); +} + +static u64 get_ch_rank_size(u8 chn, u8 rank) +{ + u32 shift_for_16bit = 1; + u32 col_bit, row_bit; + u32 emi_cona = read32(&emi_regs->cona); + + shift_for_16bit = (emi_cona & 0x2) ? 0 : 1; + + col_bit = ((emi_cona >> (chn * 16 + rank * 2 + 4)) & 0x03) + 9; + row_bit = ((((emi_cona >> (24 - chn * 20 + rank)) & 0x01) << 2) + + ((emi_cona >> (12 + chn*16 + rank * 2)) & 0x03)) + 13; + + /* data width (bytes) * 8 banks */ + return ((u64)(1 << (row_bit + col_bit))) * + ((u64)(4 >> shift_for_16bit) * 8); +} + +void dramc_get_rank_size(u64 *dram_rank_size) +{ + u64 ch0_rank0_size, ch0_rank1_size, ch1_rank0_size, ch1_rank1_size; + u64 ch_rank0_size = 0, ch_rank1_size = 0; + u32 emi_cona = read32(&emi_regs->cona); + u32 emi_conh = read32(&emi_regs->conh); + + dram_rank_size[0] = 0; + dram_rank_size[1] = 0; + + ch0_rank0_size = (emi_conh >> 16) & 0xf; + ch0_rank1_size = (emi_conh >> 20) & 0xf; + ch1_rank0_size = (emi_conh >> 24) & 0xf; + ch1_rank1_size = (emi_conh >> 28) & 0xf; + + /* CH0 EMI */ + if (ch0_rank0_size == 0) + ch_rank0_size = get_ch_rank_size(CHANNEL_A, RANK_0); + else + ch_rank0_size = (ch0_rank0_size * 256 << 20); + + /* dual rank enable */ + if ((emi_cona & (1 << 17)) != 0) { + if (ch0_rank1_size == 0) + ch_rank1_size = get_ch_rank_size(CHANNEL_A, RANK_1); + else + ch_rank1_size = (ch0_rank1_size * 256 << 20); + } + + dram_rank_size[0] = ch_rank0_size; + dram_rank_size[1] = ch_rank1_size; + + if (ch1_rank0_size == 0) + ch_rank0_size = get_ch_rank_size(CHANNEL_B, RANK_0); + else + ch_rank0_size = (ch1_rank0_size * 256 << 20); + + if ((emi_cona & (1 << 16)) != 0) { + if (ch1_rank1_size == 0) + ch_rank1_size = get_ch_rank_size(CHANNEL_B, RANK_1); + else + ch_rank1_size = (ch1_rank1_size * 256 << 20); + } + dram_rank_size[0] += ch_rank0_size; + dram_rank_size[1] += ch_rank1_size; +} size_t sdram_size(void) { - return (size_t)4 * GiB; + size_t dram_size = 0; + u64 rank_size[RANK_MAX]; + + dramc_get_rank_size(&rank_size[0]); + + for (int i = 0; i < RANK_MAX; i++) { + dram_size += rank_size[i]; + dramc_show("rank%d size:0x%llx\n", i, rank_size[i]); + } + + return dram_size; +} + +static void set_rank_info_to_conf(const struct sdram_params *params) +{ + u8 u4value = 0; + + /* CONA 17th bit 0: Disable dual rank mode + * 1: Enable dual rank mode */ + u4value = ((params->emi_cona_val & (0x1 << 17)) >> 17) ? 0 : 1; + clrsetbits_le32(&ch[0].ao.arbctl, 0x1 << 12, u4value << 12); +} + +static void set_MRR_pinmux_mapping(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + const u8 *map = phy_mapping[chn]; + write32(&ch[chn].ao.mrr_bit_mux1, + (map[0] << 0) | (map[1] << 8) | + (map[2] << 16) | (map[3] << 24)); + + write32(&ch[chn].ao.mrr_bit_mux2, + (map[4] << 0) | (map[5] << 8) | + (map[6] << 16) | (map[7] << 24)); + + write32(&ch[chn].ao.mrr_bit_mux3, + (map[8] << 0) | (map[9] << 8) | + (map[10] << 16) | (map[11] << 24)); + + write32(&ch[chn].ao.mrr_bit_mux4, + (map[12] << 0) | (map[13] << 8) | + (map[14] << 16) | (map[15] << 24)); + } +} + +static void global_option_init(const struct sdram_params *params) +{ + set_rank_info_to_conf(params); + set_MRR_pinmux_mapping(); +} + +static void emi_esl_setting1(void) +{ + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + write32(&emi_regs->cona, 0xa053a154); + write32(&emi_regs->conb, 0x17283544); + write32(&emi_regs->conc, 0x0a1a0b1a); + write32(&emi_regs->cond, 0x3657587a); + write32(&emi_regs->cone, 0x80400148); + write32(&emi_regs->conf, 0x00000000); + write32(&emi_regs->cong, 0x2b2b2a38); + write32(&emi_regs->conh, 0x00000000); + write32(&emi_regs->coni, 0x00008803); + write32(&emi_regs->conm, 0x000001ff); + write32(&emi_regs->conn, 0x00000000); + write32(&emi_regs->mdct, 0x11338c17); + write32(&emi_regs->mdct_2nd, 0x00001112); + write32(&emi_regs->iocl, 0xa8a8a8a8); + write32(&emi_regs->iocl_2nd, 0x25252525); + write32(&emi_regs->iocm, 0xa8a8a8a8); + write32(&emi_regs->iocm_2nd, 0x25252525); + write32(&emi_regs->testb, 0x00060037); + write32(&emi_regs->testc, 0x38460000); + write32(&emi_regs->testd, 0x00000000); + write32(&emi_regs->arba, 0x4020524f); + write32(&emi_regs->arbb, 0x4020504f); + write32(&emi_regs->arbc, 0xa0a050c6); + write32(&emi_regs->arbd, 0x000070cc); + write32(&emi_regs->arbe, 0x40406045); + write32(&emi_regs->arbf, 0xa0a070d5); + write32(&emi_regs->arbg, 0xa0a0504f); + write32(&emi_regs->arbh, 0xa0a0504f); + write32(&emi_regs->arbi, 0x00007108); + write32(&emi_regs->arbi_2nd, 0x00007108); + write32(&emi_regs->slct, 0x0001ff00); + + write32(&ch[0].emi.chn_cona, 0x0400a051); + write32(&ch[0].emi.chn_conb, 0x00ff2048); + write32(&ch[0].emi.chn_conc, 0x00000000); + write32(&ch[0].emi.chn_mdct, 0x88008817); + write32(&ch[0].emi.chn_testb, 0x00030027); + write32(&ch[0].emi.chn_testc, 0x38460002); + write32(&ch[0].emi.chn_testd, 0x00000000); + write32(&ch[0].emi.chn_md_pre_mask, 0x00000f00); + write32(&ch[0].emi.chn_md_pre_mask_shf, 0x00000b00); + write32(&ch[0].emi.chn_arbi, 0x20406188); + write32(&ch[0].emi.chn_arbi_2nd, 0x20406188); + write32(&ch[0].emi.chn_arbj, 0x3719595e); + write32(&ch[0].emi.chn_arbj_2nd, 0x3719595e); + write32(&ch[0].emi.chn_arbk, 0x64f3fc79); + write32(&ch[0].emi.chn_arbk_2nd, 0x64f3fc79); + write32(&ch[0].emi.chn_slct, 0x00080888); + write32(&ch[0].emi.chn_arb_ref, 0x82410222); + write32(&ch[0].emi.chn_emi_shf0, 0x8a228c17); + write32(&ch[0].emi.chn_rkarb0, 0x0006002f); + write32(&ch[0].emi.chn_rkarb1, 0x01010101); + write32(&ch[0].emi.chn_rkarb2, 0x10100820); + write32(&ch[0].emi.chn_eco3, 0x00000000); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + +static void emi_esl_setting2(void) +{ + dramc_set_broadcast(DRAMC_BROADCAST_ON); + + write32(&ch[0].emi.chn_conc, 0x01); + write32(&emi_regs->conm, 0x05ff); + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); +} + +static void emi_init(const struct sdram_params *params) +{ + emi_esl_setting1(); + + write32(&emi_regs->cona, params->emi_cona_val); + write32(&emi_regs->conf, params->emi_conf_val); + write32(&emi_regs->conh, params->emi_conh_val); + + for (size_t chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + write32(&ch[chn].emi.chn_cona, params->chn_emi_cona_val[chn]); + write32(&ch[chn].emi.chn_conc, 0); + } +} + +static void emi_init2(const struct sdram_params *params) +{ + emi_esl_setting2(); + + setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 1, 0x1 << 4); + setbits_le32(&emi_mpu->mpu_ctrl_d0 + 0x4 * 7, 0x1 << 4); + + write32(&emi_regs->bwct0, 0x0A000705); + write32(&emi_regs->bwct0_3rd, 0x0); + + /* EMI QoS 0.5 */ + write32(&emi_regs->bwct0_2nd, 0x00030023); + write32(&emi_regs->bwct0_4th, 0x00c00023); + write32(&emi_regs->bwct0_5th, 0x00240023); +} + +static void dramc_init_pre_settings(void) +{ + clrsetbits_le32(&ch[0].phy.ca_cmd[8], + (0x1 << 21) | (0x1 << 20) | (0x1 << 19) | (0x1 << 18) | + (0x1F << 8) | (0x1f << 0), + (0x1 << 19) | (0xa << 8) | (0xa << 0)); + + setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 12)); + clrbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 13)); + setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 31)); +} + +static void init_dram(const struct sdram_params *params) +{ + global_option_init(params); + emi_init(params); + + dramc_set_broadcast(DRAMC_BROADCAST_ON); + dramc_init_pre_settings(); + + emi_init2(params); +} + +void mt_set_emi(const struct sdram_params *params) +{ + init_dram(params); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h new file mode 100644 index 0000000..e699e80 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_common_mt8183.h @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRAMC_COMMON_MT8183_H_ +#define _DRAMC_COMMON_MT8183_H_ + +#define DRAM_DFS_SHUFFLE_MAX 3 + +enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_MAX +}; + +enum { + RANK_0 = 0, + RANK_1, + RANK_MAX +}; + +enum dram_odt_type { + ODT_OFF = 0, + ODT_ON +}; + +enum { + DQ_DATA_WIDTH = 16, + DQS_BIT_NUMBER = 8, + DQS_NUMBER = (DQ_DATA_WIDTH / DQS_BIT_NUMBER) +}; + +/* + * Internal CBT mode enum + * 1. Calibration flow uses vGet_Dram_CBT_Mode to + * differentiate between mixed vs non-mixed LP4 + * 2. Declared as dram_cbt_mode[RANK_MAX] internally to + * store each rank's CBT mode type + */ +enum { + CBT_NORMAL_MODE = 0, + CBT_BYTE_MODE1 +}; + +#endif /* _DRAMC_COMMON_MT8183_H_ */ diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h new file mode 100644 index 0000000..e24bd6c --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRAMC_PI_API_MT8183_H +#define _DRAMC_PI_API_MT8183_H + +#include <types.h> +#include <soc/emi.h> +#include <console/console.h> + +#define dramc_show(_x_...) printk(BIOS_INFO, _x_) +#if IS_ENABLED(CONFIG_DEBUG_DRAM) +#define dramc_dbg(_x_...) printk(BIOS_DEBUG, _x_) +#else +#define dramc_dbg(_x_...) +#endif + +#define ENABLE 1 +#define DISABLE 0 + +#define DATLAT_TAP_NUMBER 32 + +#define MAX_CMP_CPT_WAIT_LOOP 10000 +#define TIME_OUT_CNT 100 + +#define DRAMC_BROADCAST_ON 0x1f +#define DRAMC_BROADCAST_OFF 0x0 +#define MAX_BACKUP_REG_CNT 32 + +enum dram_te_op { + TE_OP_WRITE_READ_CHECK = 0, + TE_OP_READ_CHECK +}; + +enum { + DBI_OFF = 0, + DBI_ON +}; + +enum { + FSP_0 = 0, + FSP_1, + FSP_MAX +}; + +enum { + TX_DQ_DQS_MOVE_DQ_ONLY = 0, + TX_DQ_DQS_MOVE_DQM_ONLY, + TX_DQ_DQS_MOVE_DQ_DQM +}; + +enum { + MAX_CA_FINE_TUNE_DELAY = 63, + MAX_CS_FINE_TUNE_DELAY = 63, + MAX_CLK_FINE_TUNE_DELAY = 31, + CATRAINING_NUM = 6, + PASS_RANGE_NA = 0x7fff +}; + +enum { + GATING_OFF = 0, + GATING_ON = 1 +}; + +enum { + CKE_FIXOFF = 0, + CKE_FIXON, + CKE_DYNAMIC +}; + +enum { + GATING_PATTERN_NUM = 0x23, + GATING_GOLDEND_DQSCNT = 0x4646 +}; + +enum { + IMPCAL_STAGE_DRVP = 0x1, + IMPCAL_STAGE_DRVN, + IMPCAL_STAGE_TRACKING +}; + +enum { + DQS_GW_COARSE_STEP = 1, + DQS_GW_FINE_START = 0, + DQS_GW_FINE_END = 32, + DQS_GW_FINE_STEP = 4, + DQS_GW_FREQ_DIV = 4, + RX_DQS_CTL_LOOP = 8, + RX_DLY_DQSIENSTB_LOOP = 32 +}; + +enum { + SAVE_VALUE, + RESTORE_VALUE +}; + +enum { + DQ_DIV_SHIFT = 3, + DQ_DIV_MASK = BIT(DQ_DIV_SHIFT) - 1, + OEN_SHIFT = 16, + + DQS_DELAY_2T = 3, + DQS_DELAY_0P5T = 4, + DQS_DELAY = ((DQS_DELAY_2T << DQ_DIV_SHIFT) + DQS_DELAY_0P5T) << 5, + + DQS_OEN_DELAY_2T = 3, + DQS_OEN_DELAY_0P5T = 1, + + SELPH_DQS0 = (DQS_DELAY_2T << 0) | (DQS_DELAY_2T << 4) | + (DQS_DELAY_2T << 8) | (DQS_DELAY_2T << 12) | + (DQS_OEN_DELAY_2T << 16) | (DQS_OEN_DELAY_2T << 20) | + (DQS_OEN_DELAY_2T << 24) | (DQS_OEN_DELAY_2T << 28), + + SELPH_DQS1 = (DQS_DELAY_0P5T << 0) | (DQS_DELAY_0P5T << 4) | + (DQS_DELAY_0P5T << 8) | (DQS_DELAY_0P5T << 12) | + (DQS_OEN_DELAY_0P5T << 16) | (DQS_OEN_DELAY_0P5T << 20) | + (DQS_OEN_DELAY_0P5T << 24) | (DQS_OEN_DELAY_0P5T << 28) +}; + +void dramc_get_rank_size(u64 *dram_rank_size); +void dramc_set_broadcast(u32 onoff); +u32 dramc_get_broadcast(void); +#endif /* _DRAMC_PI_API_MT8183_H */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index edc27a8..c3c8e81 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -18,7 +18,27 @@ #include <stdint.h> #include <types.h> +#include <soc/dramc_common_mt8183.h> +struct sdram_params { + u32 impedance[2][4]; + u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]; + u8 cbt_cs[CHANNEL_MAX][RANK_MAX]; + u8 cbt_mr12[CHANNEL_MAX][RANK_MAX]; + s8 clk_delay; + s8 dqs_delay[CHANNEL_MAX]; + u32 emi_cona_val; + u32 emi_conh_val; + u32 emi_conf_val; + u32 chn_emi_cona_val[CHANNEL_MAX]; + u32 cbt_mode_extern; + u16 delay_cell_unit; +}; + +int complex_mem_test(u8 *start, unsigned int len); size_t sdram_size(void); +const struct sdram_params *get_sdram_config(void); +void mt_set_emi(const struct sdram_params *params); +void mt_mem_init(const struct sdram_params *params); -#endif +#endif /* SOC_MEDIATEK_MT8183_EMI_H */ diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c new file mode 100644 index 0000000..643ca6b --- /dev/null +++ b/src/soc/mediatek/mt8183/memory.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/emi.h> + +void mt_mem_init(const struct sdram_params *params) +{ + /* memory calibration */ + mt_set_emi(params); +} -- To view, visit https://review.coreboot.org/28835 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I945181aa1c901fe78ec1f4478a928c600c1b1dea Gerrit-Change-Number: 28835 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

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Change in coreboot[master]: mc_apl1: Set up SPI OPCODE menu before locking
by Werner Zeh (Code Review) 01 Oct '18

01 Oct '18

Werner Zeh has uploaded this change for review. ( https://review.coreboot.org/28834 Change subject: mc_apl1: Set up SPI OPCODE menu before locking ...................................................................... mc_apl1: Set up SPI OPCODE menu before locking In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/mainboard.c 1 file changed, 55 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/28834/1 diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index b81da5f..58a053e 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -36,6 +36,51 @@ #define BIOS_MAILBOX_INTERFACE 0x7084 #define RUN_BUSY_STS (1 << 31) +/* + * SPI Opcode Menu setup for SPIBAR lock down + * should support most common flash chips. + */ +#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ +#define SPI_OPTYPE_0 0x01 /* Write, no address */ + +#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ +#define SPI_OPTYPE_1 0x03 /* Write, address required */ + +#define SPI_OPMENU_2 0x03 /* READ: Read Data */ +#define SPI_OPTYPE_2 0x02 /* Read, address required */ + +#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ +#define SPI_OPTYPE_3 0x00 /* Read, no address */ + +#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ +#define SPI_OPTYPE_4 0x03 /* Write, address required */ + +#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ +#define SPI_OPTYPE_5 0x00 /* Read, no address */ + +#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ +#define SPI_OPTYPE_6 0x03 /* Write, address required */ + +#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ +#define SPI_OPTYPE_7 0x02 /* Read, address required */ + +#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ + (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) +#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ + (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) + +#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ + (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ + (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ + (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) + +#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ + +#define SPIBAR_OFFSET 0x3800 +#define SPI_REG_PREOP_OPTYPE 0xa4 +#define SPI_REG_OPMENU_L 0xa8 +#define SPI_REG_OPMENU_H 0xac + /** \brief This function can decide if a given MAC address is valid or not. * Currently, addresses filled with 0xff or 0x00 are not valid. * @param mac Buffer to the MAC address to check @@ -197,6 +242,7 @@ { uint16_t cmd = 0; struct device *dev = NULL; + void *spi_base = NULL; /* Do board specific things */ variant_mainboard_final(); @@ -208,6 +254,15 @@ cmd |= PCI_COMMAND_MASTER; pci_write_config16(dev, PCI_COMMAND, cmd); } + /* Setup SPI OPCODE menu before the controller is locked. */ + dev = PCH_DEV_SPI; + spi_base = (void *)pci_read_config32(dev, PCI_BASE_ADDRESS_0); + if (!spi_base) + return; + write32((spi_base + SPI_REG_PREOP_OPTYPE), + ((SPI_OPTYPE << 16) | SPI_OPPREFIX)); + write32((spi_base + SPI_REG_OPMENU_L), SPI_OPMENU_LOWER); + write32((spi_base + SPI_REG_OPMENU_H), SPI_OPMENU_UPPER); } /* The following function performs board specific things. */ -- To view, visit https://review.coreboot.org/28834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Gerrit-Change-Number: 28834 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: siemens/mc_apl1: Activate clock spreading for PTN3460
by Werner Zeh (Code Review) 01 Oct '18

01 Oct '18

Werner Zeh has submitted this change and it was merged. ( https://review.coreboot.org/28761 ) Change subject: siemens/mc_apl1: Activate clock spreading for PTN3460 ...................................................................... siemens/mc_apl1: Activate clock spreading for PTN3460 In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c index f1cbf0f..829af2a 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/ptn3460.c @@ -84,8 +84,8 @@ /* Use 18 bits per pixel. */ cfg.lvds_interface_ctrl1 |= 0x20; - /* No clock spreading, 300 mV LVDS swing. */ - cfg.lvds_interface_ctrl2 = 0x03; + /* 1 % clock spreading, 300 mV LVDS swing. */ + cfg.lvds_interface_ctrl2 = 0x13; /* No LVDS signal swap. */ cfg.lvds_interface_ctrl3 = 0x00; /* Delay T2 (VDD to LVDS active) by 16 ms. */ -- To view, visit https://review.coreboot.org/28761 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Gerrit-Change-Number: 28761 Gerrit-PatchSet: 4 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018