coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

1 participants
1285 discussions

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of pre-calibration part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28838 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add DDR driver of pre-calibration part ...................................................................... mediatek/mt8183: Add DDR driver of pre-calibration part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 212 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/28838/2 -- To view, visit https://review.coreboot.org/28838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Gerrit-Change-Number: 28838 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of software impedance part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28837 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add DDR driver of software impedance part ...................................................................... mediatek/mt8183: Add DDR driver of software impedance part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 131 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/28837/2 -- To view, visit https://review.coreboot.org/28837 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I42a33ffb66ffa2f938f85484ffc3a0d3788816b3 Gerrit-Change-Number: 28837 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of memory test part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28845 Change subject: mediatek/mt8183: Add DDR driver of memory test part ...................................................................... mediatek/mt8183: Add DDR driver of memory test part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Kconfig M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/memory.c 3 files changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/28845/1 diff --git a/src/soc/mediatek/mt8183/Kconfig b/src/soc/mediatek/mt8183/Kconfig index b58be7f..51c6df3 100644 --- a/src/soc/mediatek/mt8183/Kconfig +++ b/src/soc/mediatek/mt8183/Kconfig @@ -19,4 +19,14 @@ select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE +config DEBUG_DRAM + bool "Output verbose DRAM related debug messages" + default n + help + This option enables additional DRAM related debug messages. + +config MEMORY_TEST + bool + default y + endif diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index ec2a9c0..2c128f9 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += dramc_pi_basic_api.c romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c +romstage-$(CONFIG_MEMORY_TEST) += ../common/memory_test.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index 643ca6b..a0f698c 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -13,10 +13,39 @@ * GNU General Public License for more details. */ +#include <assert.h> +#include <console/console.h> +#include <soc/dramc_pi_api.h> #include <soc/emi.h> +#include <symbols.h> void mt_mem_init(const struct sdram_params *params) { + u64 rank_size[RANK_MAX]; + /* memory calibration */ mt_set_emi(params); + + if (IS_ENABLED(CONFIG_MEMORY_TEST)) { + size_t r; + u8 *addr = _dram; + + dramc_get_rank_size(&rank_size[0]); + + for (r = RANK_0; r < RANK_MAX; r++) { + int i; + + if (rank_size[r] == 0) + break; + + i = complex_mem_test(addr, 0x2000); + + printk(BIOS_DEBUG, "[MEM] complex R/W mem test %s : %d\n", + (i == 0) ? "pass" : "fail", i); + + ASSERT(i == 0); + + addr += rank_size[r]; + } + } } -- To view, visit https://review.coreboot.org/28845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I30d5fbd3db2acf36e3058ba4f34558b981fba78c Gerrit-Change-Number: 28845 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of runtime config part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28844 Change subject: mediatek/mt8183: Add DDR driver of runtime config part ...................................................................... mediatek/mt8183: Add DDR driver of runtime config part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 228 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28844/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 74eddd5..b172e16 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <delay.h> #include <soc/emi.h> +#include <soc/spm.h> #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> @@ -132,3 +133,212 @@ dramc_set_broadcast(broadcast_bak); } +static void transfer_pll_to_spm_control(void) +{ + u8 shu_lev = (read32(&ch[0].ao.shustatus) & 0x00000006) >> 1; + + /* set SPM project code and enable clock enable */ + clrsetbits_le32(&mtk_spm->poweron_config_set, + (0xffff << 16) | (0x1 << 0), + (0xb16 << 16) | (0x1 << 0)); + + /* set SPM pinmux */ + clrbits_le32(&mtk_spm->pcm_pwr_io_en, (0xff << 0) | (0xff << 16)); + setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel, 0xffffffff << 0); + setbits_le32(&mtk_spm->dramc_dpy_clk_sw_con_sel2, 0xffffffff << 0); + + setbits_le32(&mtk_spm->spm_power_on_val0, (0x1 << 8) | (0xf << 12)); + setbits_le32(&mtk_spm->spm_s1_mode_ch, 0x3 << 0); + + shu_lev = (shu_lev == 1) ? 2 : 1; + clrsetbits_le32(&mtk_spm->spm_power_on_val0, 0x3 << 28, shu_lev << 28); + clrsetbits_le32(&mtk_spm->dramc_dpy_clk_sw_con2, + 0x3 << 2, shu_lev << 2); + + udelay(1); + for (u8 chn = CHANNEL_A; chn < CHANNEL_MAX; chn++) { + clrbits_le32(&ch[chn].phy.pll1, 0x1 << 31); + clrbits_le32(&ch[chn].phy.pll2, 0x1 << 31); + } +} + +static void dramc_rx_input_delay_tracking(u8 chn) +{ + /* Enable RX_FIFO macro DIV4 clock CG */ + write32(&ch[chn].phy.misc_cg_ctrl1, 0xffffffff); + + /* DVS mode to RG mode */ + for (u8 r = 0; r < 2; r++) + for (u8 b = 0; b < 2; b++) + clrbits_le32(&ch[chn].phy.r[r].b[b].rxdvs[2], 3 << 30); + + clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 19), (0x1 << 9)); + clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 19), (0x1 << 9)); + + for (size_t b = 0; b < 2; b++) { + /* tracking rising and update rising/falling together */ + clrbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[2], (0x1 << 29)); + clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2], (0x1 << 29)); + + /* DQS, DQ, DQM (DQ, DQM are tied together now) + * -> controlled using DQM MAX_MIN */ + clrsetbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[7], + (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), + (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24)); + clrsetbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[1], + (0xffff << 16) | (0xffff << 0), + (0x2 << 16) | (0x2 << 0)); + + /* DQ/DQS Rx DLY adjustment for tracking mode */ + clrbits_le32(&ch[chn].phy.r[0].b[b].rxdvs[2], + (0x3 << 26) | (0x3 << 24) | (0x3 << 18) | (0x3 << 16)); + + /* DQS, DQ, DQM (DQ, DQM are tied together now) + * -> controlled using DQM MAX_MIN */ + clrsetbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[7], + (0x3f << 0) | (0x3f << 8) | (0x7f << 16) | (0x7f << 24), + (0x0 << 0) | (0x3f << 8) | (0x0 << 16) | (0x7f << 24)); + clrsetbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[1], + (0xffff << 16) | (0xffff << 0), + (0x2 << 16) | (0x2 << 0)); + + /* DQ/DQS Rx DLY adjustment for tracking mode */ + clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2], + (0x3 << 26) | (0x3 << 24)); + clrbits_le32(&ch[chn].phy.r[1].b[b].rxdvs[2], + (0x3 << 18) | (0x3 << 16)); + } + + clrbits_le32(&ch[chn].phy.ca_cmd[10], (0x7 << 28) | (0x7 << 24)); + + /* Rx DLY tracking setting (Static) */ + clrsetbits_le32(&ch[chn].phy.b0_rxdvs[0], + (0x1 << 29) | (0xf << 4) | (0x1 << 0), + (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); + clrsetbits_le32(&ch[chn].phy.b1_rxdvs[0], + (0x1 << 29) | (0xf << 4) | (0x1 << 0), + (0x1 << 29) | (0x0 << 4) | (0x1 << 0)); + + for (u8 b = 0; b < 2; b++) { + clrsetbits_le32(&ch[chn].phy.b[b].dq[9], + (0x7 << 28) | (0x7 << 24), + (0x1 << 28) | (0x0 << 24)); + setbits_le32(&ch[chn].phy.b[b].dq[5], (0x1 << 31)); + } + + setbits_le32(&ch[chn].phy.b0_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + setbits_le32(&ch[chn].phy.b1_rxdvs[0], (0x1 << 28) | (0x1 << 31)); + for (u8 rank = RANK_0; rank < RANK_MAX; rank++) + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.r[rank].b[b].rxdvs[2], + (0x3 << 30) | (0x1 << 28) | (0x1 << 23), + (0x2 << 30) | (0x1 << 28) | (0x1 << 23)); + +} + +static void dramc_hw_dqs_gating_tracking(u8 chn) +{ + setbits_le32(&ch[chn].ao.stbcal, (0x3 << 26) | (0x1 << 0)); + clrsetbits_le32(&ch[chn].ao.stbcal1, + (0xffff << 16) | (0x1 << 8) | (0x1 << 6), + (0x1 << 16) | (0x1 << 8) | (0x0 << 6)); + + clrsetbits_le32(&ch[chn].phy.misc_ctrl0, + (0x1 << 24) | (0x1f << 11) | (0xf << 0), + (0x1 << 24) | (0x0 << 11) | (0x0 << 0)); + + clrbits_le32(&ch[chn].phy.b[0].dq[6], (0x1 << 31)); + clrbits_le32(&ch[chn].phy.b[1].dq[6], (0x1 << 31)); + clrbits_le32(&ch[chn].phy.ca_cmd[6], (0x1 << 31)); +} + +static void dramc_hw_gating_init(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits_le32(&ch[chn].ao.stbcal, + (0x7 << 22) | (0x3 << 14) | (0x1 << 19) | (0x1 << 21)); + setbits_le32(&ch[chn].ao.stbcal, (0x1 << 20) | (0x3 << 28)); + setbits_le32(&ch[chn].phy.misc_ctrl1, (0x1 << 24)); + + dramc_hw_dqs_gating_tracking(chn); + } +} + +static void dramc_impedance_tracking_enable(void) +{ + u8 chn; + + setbits_le32(&ch[0].phy.misc_ctrl0, (0x1 << 10)); + for (chn = 0; chn < CHANNEL_MAX; chn++) { + setbits_le32(&ch[chn].ao.impcal, (0x1 << 31) | (0x1 << 29) | + (0x1 << 26) | (0x1 << 17) | (0x7 << 11)); + clrbits_le32(&ch[chn].ao.impcal, (0x1 << 30)); + setbits_le32(&ch[chn].phy.misc_ctrl0, (0x1 << 18)); + setbits_le32(&ch[chn].ao.impcal, (0x1 << 19)); + } + setbits_le32(&ch[0].ao.impcal, (0x1 << 14)); + setbits_le32(&ch[1].ao.refctrl0, (0x1 << 2)); + for (chn = 0; chn < CHANNEL_MAX; chn++) + setbits_le32(&ch[chn].ao.refctrl0, (0x1 << 3)); +} + +void dramc_runtime_config(void) +{ + u8 chn = 0, shu = 0, shu_cnt = DRAM_DFS_SHUFFLE_MAX; + + clrbits_le32(&ch[0].ao.refctrl0, (0x1 << 29)); + clrbits_le32(&ch[1].ao.refctrl0, (0x1 << 29)); + + transfer_pll_to_spm_control(); + setbits_le32(&mtk_spm->spm_power_on_val0, (0x3 << 25)); + + dramc_dbg("TX_TRACKING: OFF\n"); + for (chn = 0; chn < CHANNEL_MAX; chn++) + dramc_rx_input_delay_tracking(chn); + dramc_dbg("RX_TRACKING: ON\n"); + + dramc_hw_gating_init(); + dramc_hw_gating_onoff(CHANNEL_A, GATING_ON); + dramc_dbg("HW_GATING: ON\n"); + + for (chn = 0; chn < CHANNEL_MAX; chn++) + clrbits_le32(&ch[chn].ao.stbcal2, + (0x3 << 4) | (0x3 << 8) | (0x1 << 28)); + dramc_dbg("HW_GATING DBG: OFF\n"); + + /* ZQCS_ENABLE_LP4 */ + clrbits_le32(&ch[0].ao.spcmdctrl, (0x1 << 30)); + clrbits_le32(&ch[1].ao.spcmdctrl, (0x1 << 30)); + dramc_dbg("ZQCS_ENABLE_LP4: OFF\n"); + + dramc_enable_phy_dcm(0); + dramc_dbg("LOWPOWER_GOLDEN_SETTINGS(DCM): OFF\n"); + + for (chn = 0; chn < CHANNEL_MAX; chn++) + for (shu = 0; shu < shu_cnt; shu++) + clrbits_le32(&ch[chn].ao.shu[shu].dqsg_retry, + (0x1 << 1) | (0x3 << 13)); + dramc_dbg("DUMMY_READ_FOR_DQS_GATING_RETRY: OFF\n"); + + write32(&ch[0].phy.misc_spm_ctrl0, 0xfbffefff); + write32(&ch[1].phy.misc_spm_ctrl0, 0xfbffefff); + write32(&ch[0].phy.misc_spm_ctrl2, 0xffffffef); + write32(&ch[1].phy.misc_spm_ctrl2, 0x7fffffef); + dramc_dbg("SPM_CONTROL_AFTERK: ON\n"); + + dramc_impedance_tracking_enable(); + dramc_dbg("IMPEDANCE_TRACKING: ON\n"); + + for (chn = 0; chn < CHANNEL_MAX; chn++) { + clrbits_le32(&ch[chn].ao.spcmdctrl, (0x3 << 28)); + setbits_le32(&ch[chn].ao.hw_mrr_fun, (0x1 << 0) | (0x1 << 11)); + dramc_dbg("TEMP_SENSOR: ON\n"); + + clrbits_le32(&ch[0].ao.refctrl0, (0x1 << 18)); + dramc_dbg("PER_BANK_REFRESH: OFF\n"); + + setbits_le32(&ch[chn].phy.dvfs_emi_clk, (0x1 << 24)); + setbits_le32(&ch[chn].ao.dvfsdll, (0x1 << 7)); + } +} + diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 2295f39..f1ce236 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -241,7 +241,7 @@ } } -static void dramc_enable_phy_dcm(u8 en) +void dramc_enable_phy_dcm(u8 en) { u32 broadcast_bak = dramc_get_broadcast(); u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX; @@ -309,7 +309,7 @@ } } -static void dramc_hw_gating_onoff(u8 chn, u8 onoff) +void dramc_hw_gating_onoff(u8 chn, u8 onoff) { clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14, (onoff << 14) | (onoff << 15)); diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index eb75890..f991932 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -274,6 +274,17 @@ setbits_le32(&ch[0].phy.misc_ctrl1, (0x1 << 31)); } +static void dramc_ac_timing_optimize(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + clrsetbits_le32(&ch[chn].ao.shu[0].actim[3], + (0xff << 16), (0x64 << 16)); + clrbits_le32(&ch[chn].ao.shu[0].ac_time_05t, (0x1 << 2)); + clrsetbits_le32(&ch[chn].ao.shu[0].actim[4], + (0x3ff << 0), (0x77 << 0)); + } +} + static void dramc_init(void) { for (int i = 0; i < ARRAY_SIZE(init_settings); i++) @@ -297,6 +308,8 @@ { dramc_apply_pre_calibration_config(); dramc_calibrate_all_channels(params); + dramc_ac_timing_optimize(); + dramc_runtime_config(); } void mt_set_emi(const struct sdram_params *params) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index a67e16d..e1a0333 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -136,6 +136,7 @@ }; void dramc_get_rank_size(u64 *dram_rank_size); +void dramc_runtime_config(void); void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); void dramc_sw_impedance(const struct sdram_params *params); @@ -143,4 +144,6 @@ void dramc_calibrate_all_channels(const struct sdram_params *params); void dramc_save_restore_multi_reg(u8 type, u32 *store_mem, u32 **addr, u32 count); +void dramc_hw_gating_onoff(u8 chn, u8 onoff); +void dramc_enable_phy_dcm(u8 bEn); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/28844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563 Gerrit-Change-Number: 28844 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of rx datlat calibration part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28843 Change subject: mediatek/mt8183: Add DDR driver of rx datlat calibration part ...................................................................... mediatek/mt8183: Add DDR driver of rx datlat calibration part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/28843/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index f6ab9a0..2295f39 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -1701,6 +1701,81 @@ return 0; } + +static void dle_factor_handler(u8 chn, u8 curr_val) +{ + curr_val = MAX(curr_val, 2); + clrsetbits_le32(&ch[chn].ao.shu[0].conf[1], + (SHU_CONF1_DATLAT_MASK) | (SHU_CONF1_DATLAT_DSEL_MASK) | + (SHU_CONF1_DATLAT_DSEL_PHY_MASK), + (curr_val << SHU_CONF1_DATLAT_SHIFT) | + ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_SHIFT) | + ((curr_val - 2) << SHU_CONF1_DATLAT_DSEL_PHY_SHIFT)); + dram_phy_reset(chn); +} + +static u8 dramc_rx_datlat_cal(u8 chn, u8 rank) +{ + u32 err = 0xffffffff, datlat_begin = 7; + s32 datlat, first = -1, sum = 0, best_step = 0; + + best_step = read32(&ch[chn].ao.shu[0].conf[1]) & + (SHU_CONF1_DATLAT_MASK); + + dramc_show("[DATLAT] start. CH%d RK%d DATLAT Default: 0x%x\n", + chn, rank, best_step); + + u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, 0x400, 0); + + for (datlat = datlat_begin; datlat < DATLAT_TAP_NUMBER; datlat++) { + dle_factor_handler(chn, datlat); + + err = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + + if (err && (first != -1)) + break; + + if (sum > 4) + break; + + if (err == 0) { + if (first == -1) + first = datlat; + + sum++; + } + + dramc_show("TAP=%2d, err_value=0x%8x, sum=%d\n", + datlat, err, sum); + } + + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + + best_step = first + (sum >> 1); + dramc_dbg("first_step=%d, total pass=%d, best_step=%d\n", + first, sum, best_step); + + assert(sum != 0); + + dle_factor_handler(chn, best_step); + + clrsetbits_le32(&ch[chn].ao.padctrl, PADCTRL_DQIENQKEND_MASK, + (0x1 << PADCTRL_DQIENQKEND_SHIFT) | + (0x1 << PADCTRL_DQIENLATEBEGIN_SHIFT)); + + return (u8)best_step; +} + +static void dramc_dual_rank_rx_datlat_cal(u8 chn, u8 datlat0, u8 datlat1) +{ + u8 final_datlat = MAX(datlat0, datlat1); + dle_factor_handler(chn, final_datlat); + dramc_dbg("[%s] RK0: %d, RK1: %d, Final_Datlat %d\n", + __func__, datlat0, datlat1, final_datlat); +} + static void dramc_rx_dqs_gating_post_process(u8 chn) { u8 dqs, rank_rx_dvs, dqsinctl, rank; @@ -1801,6 +1876,7 @@ void dramc_calibrate_all_channels(const struct sdram_params *pams) { + u8 rx_datlat[RANK_MAX] = {0x0}; for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { dramc_show("start K ch:%d, rank:%d\n", chn, rk); @@ -1812,9 +1888,11 @@ dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); + rx_datlat[rk] = dramc_rx_datlat_cal(chn, rk); dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); } dramc_rx_dqs_gating_post_process(chn); + dramc_dual_rank_rx_datlat_cal(chn, rx_datlat[0], rx_datlat[1]); } } -- To view, visit https://review.coreboot.org/28843 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia20de54633bf1077bd469df75ccb4390308e0b97 Gerrit-Change-Number: 28843 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of tx rx window perbit cal part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28842 Change subject: mediatek/mt8183: Add DDR driver of tx rx window perbit cal part ...................................................................... mediatek/mt8183: Add DDR driver of tx rx window perbit cal part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I4434897864993e254e1362416316470083351493 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h M src/soc/mediatek/mt8183/include/soc/memlayout.ld 3 files changed, 844 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/28842/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 159d72a..f6ab9a0 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -20,6 +20,81 @@ #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> +enum { + RX_VREF_BEGIN = 0, + RX_VREF_END = 12, + RX_VREF_STEP = 1, + TX_VREF_BEGIN = 8, + TX_VREF_END = 18, + TX_VREF_STEP = 1, +}; + +enum { + FIRST_DQ_DELAY = 0, + FIRST_DQS_DELAY = -27, + MAX_DQDLY_TAPS = 16, + MAX_RX_DQDLY_TAPS = 63, + MAX_TX_DQDLY_TAPS = 200, + MAX_TX_DQSDLY_TAPS = 63, + MAX_RX_DQSDLY_TAPS = 26 +}; + +enum { + RX_WIN_RD_DQC = 0, + RX_WIN_TEST_ENG, + TX_WIN_DQ_ONLY, + TX_WIN_DQ_DQM, +}; + +enum { + RX_DQ = 0, + RX_DQM, + RX_DQS, +}; + +struct dqdqs_perbit_dly { + s16 first_dqdly; + s16 last_dqdly; + s16 first_dqsdly; + s16 last_dqsdly; + s16 best_first_dqdly; + s16 best_last_dqdly; + s16 best_first_dqsdly; + s16 best_last_dqsdly; + s16 best_dqdly; + s16 best_dqsdly; +}; + +struct vref_perbit_dly { + u8 vref; + u16 max_win; + u16 min_win; + struct dqdqs_perbit_dly perbit_dly[DQ_DATA_WIDTH]; +}; + +struct tx_dly_tune { + u8 fine_tune; + u8 coarse_tune_large; + u8 coarse_tune_small; + u8 coarse_tune_large_oen; + u8 coarse_tune_small_oen; +}; + +struct per_byte_dly { + u16 max_center; + u16 min_center; + u16 final_dly; +}; + +struct per_bit_dly { + s16 first_pass; + s16 last_pass; + s16 win_center; + u16 win_size; + u16 best_dqdly; +}; +extern const u8 phy_mapping[CHANNEL_MAX][16]; + static void auto_refresh_switch(u8 chn, u8 option) { clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, @@ -863,6 +938,769 @@ dram_phy_reset(chn); } +static void dramc_rd_dqc_init(u8 chn, u8 rank) +{ + u8 *lpddr_phy_mapping; + u16 temp_value = 0; + u8 mr15_golden_value = 0; + u8 mr20_golden_value = 0; + + for (u8 b = 0; b < 2; b++) + clrbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], + 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT); + + clrsetbits_le32(&ch[chn].ao.mrs, + MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + setbits_le32(&ch[chn].ao.mpc_option, + 0x1 << MPC_OPTION_MPCRKEN_SHIFT); + + lpddr_phy_mapping = (u8 *)phy_mapping[chn]; + for (u8 i = 0; i < 16; i++) + temp_value |= ((0x5555 >> i) & 0x1) << lpddr_phy_mapping[i]; + + mr15_golden_value = (u8) temp_value & 0xff; + mr20_golden_value = (u8) (temp_value >> 8) & 0xff; + clrsetbits_le32(&ch[chn].ao.mr_golden, + MR_GOLDEN_MR15_GOLDEN_MASK | MR_GOLDEN_MR20_GOLDEN_MASK, + mr15_golden_value << 8 | mr20_golden_value); +} + +static u32 dramc_rd_dqc_run(u8 chn) +{ + u16 timeout_cnt = 100; + u8 response; + u32 result; + + setbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); + setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); + do { + response = read32(&ch[chn].nao.spcmdresp) & + (0x1 << SPCMDRESP_RDDQC_RESPONSE_SHIFT); + timeout_cnt--; + udelay(1); + } while ((response == 0) && (timeout_cnt > 0)); + + if (timeout_cnt == 0) + dramc_dbg("[RxWinRDDQC] Resp fail (time out)\n"); + + result = read32(&ch[chn].nao.rdqc_cmp); + clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_RDDQCEN_SHIFT); + clrbits_le32(&ch[chn].ao.spcmdctrl, 1 << SPCMDCTRL_RDDQCDIS_SHIFT); + + return result; +} + +static void dramc_rd_dqc_end(u8 chn) +{ + clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, 0 << MRS_MRSRK_SHIFT); +} + +static void dramc_rx_vref_enable(u8 chn) +{ + setbits_le32(&ch[chn].phy.b[0].dq[5], + 0x1 << B0_DQ5_RG_RX_ARDQ_VREF_EN_B0_SHIFT); + setbits_le32(&ch[chn].phy.b[1].dq[5], + 0x1 << B1_DQ5_RG_RX_ARDQ_VREF_EN_B1_SHIFT); +} + +static void dramc_set_rx_vref(u8 chn, u8 value) +{ + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[5], + SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_MASK, + value << SHU1_BX_DQ5_RG_RX_ARDQ_VREF_SEL_B0_SHIFT); +} + +static void dramc_set_tx_vref(u8 chn, u8 rank, u8 value) +{ + dramc_mode_reg_write_by_rank(chn, rank, 14, value | 0 << 6); +} + +static void dramc_set_vref(u8 chn, u8 rank, u8 cal_type, u8 vref) +{ + if (cal_type == RX_WIN_TEST_ENG) + dramc_set_rx_vref(chn, vref); + else + dramc_set_tx_vref(chn, rank, vref); +} + +static void dramc_transfer_dly_tune(u8 chn, u32 dly, + struct tx_dly_tune *dly_tune) +{ + u16 tmp_val; + + dly_tune->fine_tune = dly & (TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP - 1); + + tmp_val = (dly / TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP) << 1; + dly_tune->coarse_tune_small = tmp_val - ((tmp_val >> 3) << 3); + dly_tune->coarse_tune_large = tmp_val >> 3; + + tmp_val -= 4; + dly_tune->coarse_tune_small_oen = tmp_val - ((tmp_val >> 3) << 3); + dly_tune->coarse_tune_large_oen = tmp_val >> 3; +} + +static void set_rx_dly_factor(u8 chn, u8 rank, u8 type, u32 val) +{ + u8 i; + u32 tmp, mask; + + switch (type) { + case RX_DQ: + tmp = (val << 24 | val << 16 | val << 8 | val); + for (i = 2; i < 6; i++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[i], tmp); + write32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[i], tmp); + } + break; + + case RX_DQM: + tmp = (val << 8 | val); + mask = SHU1_B0_DQ6_RK_RX_ARDQM0_F_DLY_B0_MASK | + SHU1_B0_DQ6_RK_RX_ARDQM0_R_DLY_B0_MASK; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], + mask, tmp); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], + mask, tmp); + break; + + case RX_DQS: + tmp = (val << 24 | val << 16); + mask = SHU1_B0_DQ6_RK_RX_ARDQS0_F_DLY_B0_MASK | + SHU1_B0_DQ6_RK_RX_ARDQS0_R_DLY_B0_MASK; + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[6], + mask, tmp); + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[6], + mask, tmp); + } +} + +static void set_tx_dly_factor(u8 chn, u8 rank, u8 type, u32 curr_val) +{ + struct tx_dly_tune dly_tune = {0}; + u32 coarse_tune_large = 0, coarse_tune_large_oen = 0; + u32 coarse_tune_small = 0, coarse_tune_small_oen = 0; + + dramc_transfer_dly_tune(chn, curr_val, &dly_tune); + + for (u8 i = 0; i < 4; i++) { + coarse_tune_large += dly_tune.coarse_tune_large << (i * 4); + coarse_tune_large_oen += + dly_tune.coarse_tune_large_oen << (i * 4); + coarse_tune_small += dly_tune.coarse_tune_small << (i * 4); + coarse_tune_small_oen += + dly_tune.coarse_tune_small_oen << (i * 4); + } + if (type == TX_WIN_DQ_DQM) + dramc_dbg("%3d |%d %d %2d | [0]", curr_val, + dly_tune.coarse_tune_large, + dly_tune.coarse_tune_small, dly_tune.fine_tune); + + if (type != TX_WIN_DQ_DQM && type != TX_WIN_DQ_ONLY) + return; + + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + (coarse_tune_large_oen << 16) | coarse_tune_large); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + (coarse_tune_small_oen << 16) | coarse_tune_small); + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQ_MASK, dly_tune.fine_tune << 8); + + if (type == TX_WIN_DQ_DQM) { + /* large coarse_tune setting */ + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + (coarse_tune_large_oen << 16) | coarse_tune_large); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + (coarse_tune_small_oen << 16) | coarse_tune_small); + /* fine_tune delay setting */ + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQM_MASK, dly_tune.fine_tune << 16); + + } +} + +static u32 dramc_get_smallest_dqs_dly(u8 chn, u8 rank, + const struct sdram_params *params) +{ + u32 min_dly = 0xffff; + + for (size_t i = 0; i < DQS_NUMBER; i++) + min_dly = MIN(min_dly, params->wr_level[chn][rank][i]); + + return DQS_DELAY + min_dly; +} + + +static void dramc_get_dly_range(u8 chn, u8 rank, u8 cal_type, u16 *pre_cal, + s16 *begin, s16 *end, const struct sdram_params *params) +{ + u16 pre_dq_dly; + switch (cal_type) { + case RX_WIN_RD_DQC: + case RX_WIN_TEST_ENG: + *begin = FIRST_DQS_DELAY; + *end = MAX_RX_DQDLY_TAPS; + break; + + case TX_WIN_DQ_DQM: + *begin = dramc_get_smallest_dqs_dly(chn, rank, params); + *end = *begin + 256; + break; + + case TX_WIN_DQ_ONLY: + pre_dq_dly = MIN(pre_cal[0], pre_cal[1]); + pre_dq_dly = (pre_dq_dly > 24) ? (pre_dq_dly - 24) : 0; + *begin = pre_dq_dly; + *end = *begin + 64; + break; + } +} + +static void dramc_check_dqdqs_win(struct dqdqs_perbit_dly *p, + u16 dly_step, u16 last_step, u32 fail_bit, u8 flag) +{ + s16 pass_win, best_pass_win; + s16 *first_dly_pass, *last_dly_pass; + s16 *best_first_pass, *best_last_pass; + + if (flag == 0) { + first_dly_pass = &(p->first_dqsdly); + last_dly_pass = &(p->last_dqsdly); + best_first_pass = &(p->best_first_dqsdly); + best_last_pass = &(p->best_last_dqsdly); + } else { + first_dly_pass = &(p->first_dqdly); + last_dly_pass = &(p->last_dqdly); + best_first_pass = &(p->best_first_dqdly); + best_last_pass = &(p->best_last_dqdly); + } + + if (fail_bit == 0) { + if (*first_dly_pass == -1) { + /* first pass delay tap */ + *first_dly_pass = dly_step; + } + if ((*last_dly_pass == -2) && (dly_step == last_step)) { + /* pass to the last tap */ + *last_dly_pass = dly_step; + pass_win = *last_dly_pass - *first_dly_pass; + best_pass_win = *best_last_pass - *best_first_pass; + if (pass_win > best_pass_win) { + *best_last_pass = *last_dly_pass; + *best_first_pass = *first_dly_pass; + } + /* clear to find the next pass range if it has */ + *first_dly_pass = -1; + *last_dly_pass = -2; + } + } else { + if ((*first_dly_pass != -1) + && (*last_dly_pass == -2)) { + *last_dly_pass = dly_step - 1; + pass_win = *last_dly_pass - *first_dly_pass; + best_pass_win = *best_last_pass - *best_first_pass; + if (pass_win > best_pass_win) { + *best_last_pass = *last_dly_pass; + *best_first_pass = *first_dly_pass; + } + /* clear to find the next pass range if it has */ + *first_dly_pass = -1; + *last_dly_pass = -2; + } + } +} + +static void dramc_set_vref_dly(struct vref_perbit_dly *vref_dly, + u8 vref, u32 win_size_sum, struct dqdqs_perbit_dly delay[]) +{ + struct dqdqs_perbit_dly *perbit_dly = vref_dly->perbit_dly; + + vref_dly->max_win = win_size_sum; + vref_dly->vref = vref; + for (u8 bit = 0; bit < DQ_DATA_WIDTH; bit++) { + perbit_dly[bit].best_dqdly = delay[bit].best_dqdly; + perbit_dly[bit].best_first_dqdly = delay[bit].best_first_dqdly; + perbit_dly[bit].best_last_dqdly = delay[bit].best_last_dqdly; + perbit_dly[bit].best_first_dqsdly = + delay[bit].best_first_dqsdly; + perbit_dly[bit].best_last_dqsdly = delay[bit].best_last_dqsdly; + } +} + +static int dramk_calc_best_vref(u8 cal_type, u8 vref, + struct vref_perbit_dly *vref_dly, + struct dqdqs_perbit_dly delay[]) +{ + u8 bit; + u32 win_size; + u32 win_size_sum = 0; + static u32 min_win_size_vref; + + if (cal_type == RX_WIN_TEST_ENG) { + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_size_sum += (delay[bit].best_last_dqdly - + delay[bit].best_first_dqdly + 1); + win_size_sum += (delay[bit].best_last_dqsdly - + delay[bit].best_first_dqsdly + 1); + } + + if (win_size_sum > vref_dly->max_win) + dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + + if (win_size_sum < (vref_dly->max_win * 95 / 100)) + return 1; + } else if (cal_type == TX_DQ_DQS_MOVE_DQ_ONLY) { + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + win_size = (delay[bit].best_last_dqdly - + delay[bit].best_first_dqdly + 1); + vref_dly->min_win = MIN(vref_dly->min_win, win_size); + win_size_sum += win_size; + } + + if ((win_size_sum > vref_dly->max_win) + && (vref_dly->min_win >= min_win_size_vref)) { + min_win_size_vref = vref_dly->min_win; + dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + } + } else + dramc_set_vref_dly(vref_dly, vref, win_size_sum, delay); + + return 0; +} + +static void dramc_calc_tx_perbyte_dly( + struct dqdqs_perbit_dly *p, s16 *win, + struct per_byte_dly *byte_delay_prop) +{ + s16 win_center; + win_center = (p->best_first_dqdly + p->best_last_dqdly) >> 1; + *win = win_center; + + if (win_center < byte_delay_prop->min_center) + byte_delay_prop->min_center = win_center; + if (win_center > byte_delay_prop->max_center) + byte_delay_prop->max_center = win_center; +} + +static void dramc_set_rx_dly(u8 chn, u8 rank, s32 dly) +{ + if (dly <= 0) { + /* Hold time calibration */ + set_rx_dly_factor(chn, rank, RX_DQS, -dly); + dram_phy_reset(chn); + } else { + /* Setup time calibration */ + set_rx_dly_factor(chn, rank, RX_DQS, 0); + set_rx_dly_factor(chn, rank, RX_DQM, dly); + dram_phy_reset(chn); + set_rx_dly_factor(chn, rank, RX_DQ, dly); + } + +} + +static void set_tx_best_dly_factor(u8 chn, u8 rank_start, + struct per_byte_dly *tx_perbyte_dly, u16 dq_precal_result[]) +{ + u8 i, rank; + u32 coarse_tune_large = 0; + u32 coarse_tune_large_oen = 0; + u32 coarse_tune_small = 0; + u32 coarse_tune_small_oen = 0; + u16 dq_oen[DQS_NUMBER] = {0}, dqm_oen[DQS_NUMBER] = {0}; + struct tx_dly_tune dqdly_tune[DQS_NUMBER] = {0}; + struct tx_dly_tune dqmdly_tune[DQS_NUMBER] = {0}; + + for (i = 0; i < DQS_NUMBER; i++) { + dramc_transfer_dly_tune(chn, tx_perbyte_dly[i].final_dly, + &dqdly_tune[i]); + dramc_transfer_dly_tune(chn, dq_precal_result[i], + &dqmdly_tune[i]); + + coarse_tune_large += dqdly_tune[i].coarse_tune_large << (i * 4); + coarse_tune_large_oen += + dqdly_tune[i].coarse_tune_large_oen << (i * 4); + coarse_tune_small += dqdly_tune[i].coarse_tune_small << (i * 4); + coarse_tune_small_oen += + dqdly_tune[i].coarse_tune_small_oen << (i * 4); + + dq_oen[i] = (dqdly_tune[i].coarse_tune_large_oen << 3) + + (dqdly_tune[i].coarse_tune_small_oen << 5) + + dqdly_tune[i].fine_tune; + dqm_oen[i] = (dqmdly_tune[i].coarse_tune_large_oen << 3) + + (dqmdly_tune[i].coarse_tune_small_oen << 5) + + dqmdly_tune[i].fine_tune; + } + + for (rank = rank_start; rank < RANK_MAX; rank++) { + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[0], + (coarse_tune_large_oen << 16) | coarse_tune_large); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[2], + (coarse_tune_small_oen << 16) | coarse_tune_small); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[1], + (coarse_tune_large_oen << 16) | coarse_tune_large); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dq[3], + (coarse_tune_small_oen << 16) | coarse_tune_small); + } + + for (rank = rank_start; rank < RANK_MAX; rank++) + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[b].dq[7], + FINE_TUNE_DQ_MASK | FINE_TUNE_DQM_MASK, + (dqdly_tune[b].fine_tune << + FINE_TUNE_DQ_SHIFT) | + (dqmdly_tune[b].fine_tune << + FINE_TUNE_DQM_SHIFT)); +} + +static void set_rx_best_dly_factor(u8 chn, u8 rank, + struct dqdqs_perbit_dly *dqdqs_perbit_dly, + u32 *max_dqsdly_byte, u32 *ave_dqm_dly) +{ + u32 i, value = 0; + u8 index, byte; + + for (i = 0; i < DQS_NUMBER; i++) { + value = (max_dqsdly_byte[i] << 24) | + (max_dqsdly_byte[i] << 16) | + (ave_dqm_dly[i] << 8) | (ave_dqm_dly[i] << 0); + + /* Delay dqs/dqm */ + write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[6], value); + } + dram_phy_reset(chn); + + value = 0; + for (i = 0; i < DQ_DATA_WIDTH; i += 2) { + byte = i / DQS_BIT_NUMBER; + index = 2 + ((i % 8) * 2) / 4; + value = dqdqs_perbit_dly[i + 1].best_dqdly << 24 | + dqdqs_perbit_dly[i + 1].best_dqdly << 16 | + dqdqs_perbit_dly[i].best_dqdly << 8 | + dqdqs_perbit_dly[i].best_dqdly; + write32(&ch[chn].phy.shu[0].rk[rank].b[byte].dq[index], value); + } +} + +static u8 dramc_calc_best_dly(u8 bit, + struct dqdqs_perbit_dly *p, u32 *p_max_byte) +{ + u8 fail = 0, hold, setup; + + hold = p->best_last_dqsdly - p->best_first_dqsdly + 1; + setup = p->best_last_dqdly - p->best_first_dqdly + 1; + + if (hold > setup) { + p->best_dqdly = 0; + p->best_dqsdly = (setup != 0) ? (hold - setup) / 2 : + (hold - setup) / 2 + p->best_first_dqsdly; + + if (p->best_dqsdly > *p_max_byte) + *p_max_byte = p->best_dqsdly; + + } else if (hold < setup) { + p->best_dqsdly = 0; + p->best_dqdly = (hold != 0) ? (setup - hold) / 2 : + (setup - hold) / 2 + p->best_first_dqdly; + + } else { /* hold time == setup time */ + p->best_dqsdly = 0; + p->best_dqdly = 0; + + if (hold == 0) { + dramc_dbg("ERROR, error bit %d, " + "setup_time = hold_time = 0\n", bit); + fail = 1; + } + } + + dramc_dbg("bit#%d : dq =%d dqs=%d win=%d (%d, %d)\n", + bit, setup, hold, setup + hold, p->best_dqdly, p->best_dqsdly); + + return fail; +} + +static void dramc_set_dqdqs_dly(u8 chn, u8 rank, u8 cal_type, s32 dly) +{ + if ((cal_type == RX_WIN_RD_DQC) || (cal_type == RX_WIN_TEST_ENG)) + dramc_set_rx_dly(chn, rank, dly); + else + set_tx_dly_factor(chn, rank, cal_type, dly); +} + +static void dramc_set_tx_best_dly(u8 chn, u8 rank, + struct dqdqs_perbit_dly *tx_dly, u16 *tx_dq_precal_result, + const struct sdram_params *params) +{ + s16 dq_win_center[DQ_DATA_WIDTH]; + u16 pi_diff; + u32 byte_dly_cell[DQS_NUMBER] = {0, 0}; + struct per_byte_dly tx_perbyte_dly[DQS_NUMBER]; + u16 dly_cell_unit = params->delay_cell_unit; + int i, index, bit; + u16 dq_delay_cell[DQ_DATA_WIDTH]; + + for (i = 0; i < DQS_NUMBER; i++) { + tx_perbyte_dly[i].min_center = 0xffff; + tx_perbyte_dly[i].max_center = 0; + } + + for (i = 0; i < DQ_DATA_WIDTH; i++) { + index = i / DQS_BIT_NUMBER; + dramc_calc_tx_perbyte_dly(&tx_dly[i], + &dq_win_center[i], &tx_perbyte_dly[index]); + } + + for (i = 0; i < DQS_NUMBER; i++) { + tx_perbyte_dly[i].final_dly = tx_perbyte_dly[i].min_center; + tx_dq_precal_result[i] = (tx_perbyte_dly[i].max_center + + tx_perbyte_dly[i].min_center) >> 1; + + for (bit = 0; bit < DQS_BIT_NUMBER; bit++) { + pi_diff = dq_win_center[i * 8 + bit] + - tx_perbyte_dly[i].min_center; + dq_delay_cell[i * 8 + bit] = + ((pi_diff * 1000000) / (16 * 64)) + / dly_cell_unit; + byte_dly_cell[i] |= + (dq_delay_cell[i * 8 + bit] << (bit * 4)); + } + + write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], + byte_dly_cell[i]); + } + + set_tx_best_dly_factor(chn, rank, tx_perbyte_dly, tx_dq_precal_result); +} + +static int dramc_set_rx_best_dly(u8 chn, u8 rank, + struct dqdqs_perbit_dly *rx_dly) +{ + s16 dly; + s8 fail = 0; + u8 i, index, max_limit; + static u32 max_dqsdly_byte[DQS_NUMBER]; + static u32 ave_dqmdly_byte[DQS_NUMBER]; + + for (i = 0; i < DQS_NUMBER; i++) { + max_dqsdly_byte[i] = 0; + ave_dqmdly_byte[i] = 0; + } + + for (i = 0; i < DQ_DATA_WIDTH; i++) { + index = i / DQS_BIT_NUMBER; + fail |= dramc_calc_best_dly(i, &rx_dly[i], + &max_dqsdly_byte[index]); + } + + for (i = 0; i < DQ_DATA_WIDTH; i++) { + index = i / DQS_BIT_NUMBER; + /* set DQS to max for 8-bit */ + if (rx_dly[i].best_dqsdly < max_dqsdly_byte[index]) { + /* Delay DQ to compensate extra DQS delay */ + dly = max_dqsdly_byte[index] - rx_dly[i].best_dqsdly; + rx_dly[i].best_dqdly += dly; + max_limit = MAX_DQDLY_TAPS - 1; + if (rx_dly[i].best_dqdly > max_limit) + rx_dly[i].best_dqdly = max_limit; + } + + ave_dqmdly_byte[index] += rx_dly[i].best_dqdly; + if ((i + 1) % DQS_BIT_NUMBER == 0) + ave_dqmdly_byte[index] /= DQS_BIT_NUMBER; + } + + if (fail == 1) { + dramc_dbg("FAIL on perbit_window_cal()\n"); + return -1; + } + + set_rx_best_dly_factor(chn, rank, rx_dly, max_dqsdly_byte, + ave_dqmdly_byte); + return 0; +} + +static void dramc_get_vref_prop(u8 rank, u8 cal_type, + u8 *vref_scan_en, u8 *vref_begin, u8 *vref_end) +{ + if ((cal_type == RX_WIN_TEST_ENG) && (rank == RANK_0)) { + *vref_scan_en = 1; + *vref_begin = RX_VREF_BEGIN; + *vref_end = RX_VREF_END; + } else if (cal_type == TX_WIN_DQ_ONLY) { + *vref_scan_en = 1; + *vref_begin = TX_VREF_BEGIN; + *vref_end = TX_VREF_END; + } else + *vref_scan_en = 0; +} + +static void dramc_engine2_setpat(u8 chn, u8 testaudpat) +{ + const u32 log2loopcount = 0; + const u32 len1 = 0; + + clrbits_le32(&ch[chn].ao.test2_4, + 0x1 << TEST2_4_TESTXTALKPAT_SHIFT | + 0x1 << TEST2_4_TESTAUDMODE_SHIFT | + 0x1 << TEST2_4_TESTAUDBITINV_SHIFT); + + if (testaudpat == 0) { + setbits_le32(&ch[chn].ao.perfctl0, 1 << PERFCTL0_RWOFOEN_SHIFT); + + clrsetbits_le32(&ch[chn].ao.test2_4, + 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT | + 0x1 << TEST2_4_TESTSSOPAT_SHIFT | + 0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT | + 0x1 << TEST2_4_TESTXTALKPAT_SHIFT, + len1 << TEST2_4_TEST_REQ_LEN1_SHIFT); + } else if (testaudpat == 1) { + clrsetbits_le32(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, + (0x11 << 8) | (0xd << 0) | (0x1 << 14)); + } + clrsetbits_le32(&ch[chn].ao.test2_3, + 0x1 << TEST2_3_TESTAUDPAT_SHIFT | TEST2_3_TESTCNT_MASK, + (testaudpat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT | + log2loopcount << 0); +} + +static u32 dram_k_perbit(u8 chn, u8 cal_type) +{ + u32 err_value = 0x0; + + if (cal_type == RX_WIN_RD_DQC) { + err_value = dramc_rd_dqc_run(chn); + } else { + dramc_engine2_setpat(chn, 1); + err_value = dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + dramc_engine2_setpat(chn, 0); + err_value |= dramc_engine2_run(chn, TE_OP_WRITE_READ_CHECK); + } + return err_value; +} + +static u8 dramc_window_perbit_cal(u8 chn, u8 rank, + u8 type, const struct sdram_params *params) +{ + u8 vref = 0, vref_begin = 0, vref_end = 1, vref_scan_enable = 0; + s16 dly, dly_begin = 0, dly_end = 0; + u8 i, bit, dly_step = 1; + u32 dummy_rd_backup = 0; + static u16 dq_precal_result[DQS_NUMBER]; + u32 err_value, fail_bit; + static struct vref_perbit_dly vref_dly; + struct dqdqs_perbit_dly dq_perbit_dly[DQ_DATA_WIDTH]; + + dramc_get_vref_prop(rank, type, + &vref_scan_enable, &vref_begin, &vref_end); + if (vref_scan_enable && (type == RX_WIN_RD_DQC)) + dramc_rx_vref_enable(chn); + + dramc_dbg("%s [Rank %d] [Channel %d] cal_type:%d,vref_enable:%d\n", + __func__, rank, chn, type, vref_scan_enable); + + if ((type == TX_WIN_DQ_ONLY) || (type == TX_WIN_DQ_DQM)) { + for (i = 0; i < 2; i++) { + write32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[0], 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[1], + 0xf); + } + setbits_le32(&ch[chn].phy.misc_ctrl1, + 0x1 << MISC_CTRL1_R_DMAR_FINE_TUNE_DQ_SW_SHIFT); + setbits_le32(&ch[chn].ao.dqsoscr, + 0x1 << DQSOSCR_AR_COARSE_TUNE_DQ_SW_SHIFT); + } + + if (type == RX_WIN_RD_DQC) { + dramc_rd_dqc_init(chn, rank); + } else { + dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, 0x400, 0); + } + + vref_dly.max_win = 0; + vref_dly.min_win = 0xffff; + for (vref = vref_begin; vref < vref_end; vref += dly_step) { + vref_dly.vref = vref; + for (i = 0; i < DQ_DATA_WIDTH; i++) { + dq_perbit_dly[i].first_dqdly = -1; + dq_perbit_dly[i].last_dqdly = -2; + dq_perbit_dly[i].first_dqsdly = -1; + dq_perbit_dly[i].last_dqsdly = -2; + dq_perbit_dly[i].best_first_dqdly = -1; + dq_perbit_dly[i].best_last_dqdly = -2; + dq_perbit_dly[i].best_first_dqsdly = -1; + dq_perbit_dly[i].best_last_dqsdly = -2; + } + + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_dly.vref); + + if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) { + set_rx_dly_factor(chn, rank, RX_DQM, FIRST_DQ_DELAY); + set_rx_dly_factor(chn, rank, RX_DQ, FIRST_DQ_DELAY); + } + + dramc_get_dly_range(chn, rank, type, dq_precal_result, + &dly_begin, &dly_end, params); + for (dly = dly_begin; dly < dly_end; dly += dly_step) { + dramc_set_dqdqs_dly(chn, rank, type, dly); + err_value = dram_k_perbit(chn, type); + if (!vref_scan_enable) + dramc_dbg("%d ", dly); + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) { + fail_bit = err_value & ((u32) 1 << bit); + if (dly < 0) + dramc_check_dqdqs_win( + &(dq_perbit_dly[bit]), + -dly, -FIRST_DQS_DELAY, + fail_bit, 0); + else + dramc_check_dqdqs_win( + &(dq_perbit_dly[bit]), + dly, dly_end, fail_bit, 1); + if (!vref_scan_enable) { + if (fail_bit == 0) + dramc_dbg("o"); + else + dramc_dbg("x"); + } + } + + if (!vref_scan_enable) + dramc_dbg(" [MSB]\n"); + } + + for (bit = 0; bit < DQ_DATA_WIDTH; bit++) + dramc_dbg("dq[%d] win(%d ~ %d)\n", bit, + dq_perbit_dly[bit].best_first_dqdly, + dq_perbit_dly[bit].best_last_dqdly); + + if (dramk_calc_best_vref(type, vref, &vref_dly, dq_perbit_dly)) + break; + } + + if (type == RX_WIN_RD_DQC) { + dramc_rd_dqc_end(chn); + } else { + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + } + + if (vref_scan_enable) + dramc_set_vref(chn, rank, type, vref_dly.vref); + + if ((type == RX_WIN_RD_DQC) || (type == RX_WIN_TEST_ENG)) + dramc_set_rx_best_dly(chn, rank, vref_dly.perbit_dly); + else + dramc_set_tx_best_dly(chn, rank, vref_dly.perbit_dly, + dq_precal_result, params); + return 0; +} + static void dramc_rx_dqs_gating_post_process(u8 chn) { u8 dqs, rank_rx_dvs, dqsinctl, rank; @@ -971,6 +1809,10 @@ dramc_write_leveling(chn, rk, pams->wr_level); auto_refresh_switch(chn, 1); dramc_rx_dqs_gating_cal(chn, rk); + dramc_window_perbit_cal(chn, rk, RX_WIN_RD_DQC, pams); + dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_DQM, pams); + dramc_window_perbit_cal(chn, rk, TX_WIN_DQ_ONLY, pams); + dramc_window_perbit_cal(chn, rk, RX_WIN_TEST_ENG, pams); } dramc_rx_dqs_gating_post_process(chn); diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index 761fff6..a67e16d 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -38,6 +38,7 @@ #define DRAMC_BROADCAST_ON 0x1f #define DRAMC_BROADCAST_OFF 0x0 #define MAX_BACKUP_REG_CNT 32 +#define TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP 64 #define IMP_LP4X_TERM_VREF_SEL 0x1b #define IMP_DRVP_LP4X_UNTERM_VREF_SEL 0x1a diff --git a/src/soc/mediatek/mt8183/include/soc/memlayout.ld b/src/soc/mediatek/mt8183/include/soc/memlayout.ld index f148eed..2a6d42d 100644 --- a/src/soc/mediatek/mt8183/include/soc/memlayout.ld +++ b/src/soc/mediatek/mt8183/include/soc/memlayout.ld @@ -39,7 +39,7 @@ SRAM_END(0x00120000) SRAM_L2C_START(0x00200000) - OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 92K) + OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 110K) BOOTBLOCK(0x00227000, 89K) VERSTAGE(0x0023E000, 114K) SRAM_L2C_END(0x00280000) -- To view, visit https://review.coreboot.org/28842 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4434897864993e254e1362416316470083351493 Gerrit-Change-Number: 28842 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of rx dqs gating calibration part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28841 Change subject: mediatek/mt8183: Add DDR driver of rx dqs gating calibration part ...................................................................... mediatek/mt8183: Add DDR driver of rx dqs gating calibration part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 666 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/28841/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c index 4c95814..74eddd5 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_basic_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_basic_api.c @@ -19,6 +19,16 @@ #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> +void dramc_save_restore_multi_reg(u8 type, u32 *store_mem, + u32 **addr, u32 count) +{ + for (int i = 0; i < count; i++) + if (type == SAVE_VALUE) + store_mem[i] = read32(addr[i]); + else + write32(addr[i], store_mem[i]); +} + static void sw_imp_cal_vref_sel(u8 term_option, u8 impcal_stage) { u8 vref_sel = 0; diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 7b42287..159d72a 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -310,6 +310,657 @@ } } +static void rx_dqs_isi_pulse_cg_switch(u8 chn, u8 flag) +{ + dramc_dbg("CH%d RX DQS ISI pulse CG: %s\n", chn, + (flag == ENABLE) ? "enable" : "disable"); + + clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 1 << 5, flag << 5); + clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 1 << 5, flag << 5); +} + +static void dramc_set_rank_engine2(u8 chn, u8 rank) +{ + setbits_le32(&ch[chn].ao.dramctrl, 0x1 << 1); + clrbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRKSEL_MASK); + clrsetbits_le32(&ch[chn].ao.test2_4, TEST2_4_TESTAGENTRK_MASK, + rank << TEST2_4_TESTAGENTRK_SHIFT); +} + +static void dramc_engine2_init(u8 chn, u8 rank, u32 size, u8 testaudpat) +{ + const u32 pat0 = 0x55; + const u32 pat1 = 0xaa; + const u32 addr = 0; + const u32 log2loopcount = 0; + + dramc_set_rank_engine2(chn, rank); + + clrbits_le32(&ch[chn].ao.dummy_rd, + (0x1 << DUMMY_RD_DQSG_DMYRD_EN_SHIFT) | + (0x1 << DUMMY_RD_DQSG_DMYWR_EN_SHIFT) | + (0x1 << DUMMY_RD_DUMMY_RD_EN_SHIFT) | + (0x1 << DUMMY_RD_SREF_DMYRD_EN_SHIFT) | + (0x1 << DUMMY_RD_DMY_RD_DBG_SHIFT) | + (0x1 << DUMMY_RD_DMY_WR_DBG_SHIFT)); + clrbits_le32(&ch[chn].nao.testchip_dma1, + 0x1 << TESTCHIP_DMA1_DMA_LP4MATAB_OPT_SHIFT); + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT) | + (0x1 << TEST2_3_TESTAUDPAT_SHIFT) | + TEST2_3_TESTCNT_MASK, + log2loopcount << TEST2_3_TESTCNT_SHIFT | + ((testaudpat ? 1 : 0) << TEST2_3_TESTAUDPAT_SHIFT)); + clrsetbits_le32(&ch[chn].ao.test2_0, + TEST2_0_PAT0_MASK | TEST2_0_PAT1_MASK, + (pat0 << TEST2_0_PAT0_SHIFT) | + (pat1 << TEST2_0_PAT1_SHIFT)); + write32(&ch[chn].ao.test2_1, (addr << 4) & 0x00ffffff); + write32(&ch[chn].ao.test2_2, (size << 4) & 0x00ffffff); + + clrsetbits_le32(&ch[chn].ao.test2_4, + (0x1 << TEST2_4_TESTAUDMODE_SHIFT) | + (0x1 << TEST2_4_TESTAUDBITINV_SHIFT) | + (0x1 << TEST2_4_TESTXTALKPAT_SHIFT), + (((testaudpat == 0) ? 1 : 0) << TEST2_4_TESTXTALKPAT_SHIFT) | + (testaudpat << TEST2_4_TESTAUDMODE_SHIFT) | + (testaudpat << TEST2_4_TESTAUDBITINV_SHIFT)); + + if (testaudpat == 0) { + clrbits_le32(&ch[chn].ao.test2_4, + 0x1 << TEST2_4_TEST_REQ_LEN1_SHIFT | + (0x1 << TEST2_4_TESTSSOPAT_SHIFT) | + (0x1 << TEST2_4_TESTSSOXTALKPAT_SHIFT)); + setbits_le32(&ch[chn].ao.perfctl0, + 0x1 << PERFCTL0_RWOFOEN_SHIFT); + } else if (testaudpat == 1) { + clrsetbits_le32(&ch[chn].ao.test2_4, + TEST2_4_TESTAUDINIT_MASK | TEST2_4_TESTAUDINC_MASK, + (0x11 << TEST2_4_TESTAUDINIT_SHIFT) | + (0xd << TEST2_4_TESTAUDINC_SHIFT)); + } +} + +static void dramc_engine2_check_complete(u8 chn) +{ + u32 u4loop_count = 0; + while ((read32(&ch[chn].nao.testrpt) & (0x1 << 0)) == 0) { + udelay(1); + u4loop_count++; + + if (u4loop_count > MAX_CMP_CPT_WAIT_LOOP) { + dramc_dbg("MEASURE_A timeout\n"); + break; + } + } +} + +static u32 dramc_engine2_run(u8 chn, enum dram_te_op wr) +{ + u32 u4result = 0xffffffff; + + if (wr == TE_OP_READ_CHECK) { + clrbits_le32(&ch[chn].ao.test2_4, + 0x1 << TEST2_4_TESTAUDMODE_SHIFT); + } else if (wr == TE_OP_WRITE_READ_CHECK) { + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT), + 0x1 << TEST2_3_TEST2W_SHIFT); + + dramc_engine2_check_complete(chn); + clrbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | + 0x1 << TEST2_3_TEST1_SHIFT); + udelay(1); + } + + /* do Read test */ + clrsetbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | (0x1 << TEST2_3_TEST1_SHIFT), + 0x1 << TEST2_3_TEST2R_SHIFT); + + dramc_engine2_check_complete(chn); + + udelay(1); + u4result = read32(&ch[chn].nao.cmp_err); + clrbits_le32(&ch[chn].ao.test2_3, + (0x1 << TEST2_3_TEST2W_SHIFT) | + (0x1 << TEST2_3_TEST2R_SHIFT) | + (0x1 << TEST2_3_TEST1_SHIFT)); + + return u4result; +} + +static void dramc_engine2_end(u8 chn) +{ + clrbits_le32(&ch[chn].ao.test2_4, 0x1 << 17); +} + +static void find_gating_window(u32 result_r, u32 result_f, u32 *debug_cnt, + u8 dly_coarse_large, u8 dly_coarse_0p5t, u8 *pass_begin, + u8 *pass_count, u8 *dly_fine_xt, u32 *coarse_tune, u8 *dqs_high) +{ + u16 debug_cnt_perbyte; + u8 pass_count_1[DQS_NUMBER], min_coarse_tune2t_1[DQS_NUMBER], + min_coarse_tune0p5t_1[DQS_NUMBER], min_fine_tune_1[DQS_NUMBER]; + + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + u8 dqs_result_r = (u8) ((result_r >> (8 * dqs)) & 0xff); + u8 dqs_result_f = (u8) ((result_f >> (8 * dqs)) & 0xff); + debug_cnt_perbyte = (u16) debug_cnt[dqs]; + + if ((dqs_result_r == 0) && (dqs_result_f == 0) && + (debug_cnt_perbyte == GATING_GOLDEND_DQSCNT)) { + if (pass_begin[dqs] == 0) { + pass_begin[dqs] = 1; + pass_count_1[dqs] = 0; + min_coarse_tune2t_1[dqs] = dly_coarse_large; + min_coarse_tune0p5t_1[dqs] = dly_coarse_0p5t; + min_fine_tune_1[dqs] = *dly_fine_xt; + dramc_dbg("[Byte %d]First pass (%d, %d, %d)\n", + dqs, dly_coarse_large, + dly_coarse_0p5t, *dly_fine_xt); + } + + if (pass_begin[dqs] == 1) + pass_count_1[dqs]++; + + if ((pass_begin[dqs] == 1) && + (pass_count_1[dqs] * DQS_GW_FINE_STEP > 32)) + dqs_high[dqs] = 0; + + if ((pass_count_1[0] * DQS_GW_FINE_STEP > 32) && + (pass_count_1[1] * DQS_GW_FINE_STEP > 32)) { + dramc_dbg("All bytes gating window > 1 " + "coarse_tune, Early break\n"); + *dly_fine_xt = 32; + *coarse_tune = 42; + } + } + } +} + +static void find_dly_tune(u8 chn, u8 dly_coarse_large, u8 dly_coarse_0p5t, + u8 dly_fine_xt, u8 *dqs_high, u8 *dly_coarse_large_cnt, + u8 *dly_coarse_0p5t_cnt, u8 *dly_fine_tune_cnt, u8 *dqs_trans) +{ + for (u8 dqs = 0; dqs < DQS_NUMBER; dqs++) { + u32 dqs_cnt = read32(&ch[chn].phy_nao.misc_phy_stben_b[dqs]); + dqs_cnt = (dqs_cnt >> 16) & 3; + + if (dqs_cnt == 3) + dqs_high[dqs]++; + + if (dqs_high[dqs] * DQS_GW_FINE_STEP <= 16) + continue; + + switch (dqs_cnt) { + case 3: + dly_coarse_large_cnt[dqs] = dly_coarse_large; + dly_coarse_0p5t_cnt[dqs] = dly_coarse_0p5t; + dly_fine_tune_cnt[dqs] = dly_fine_xt; + dqs_trans[dqs] = 1; + break; + case 2: + case 1: + dqs_trans[dqs]++; + break; + case 0: + dqs_high[dqs] = 0; + break; + } + } +} + +static void dram_phy_reset(u8 chn) +{ + setbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); + setbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); + clrbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + clrbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + + udelay(1); + setbits_le32(&ch[chn].phy.b[1].dq[9], (1 << 4) | (1 << 0)); + setbits_le32(&ch[chn].phy.b[0].dq[9], (1 << 4) | (1 << 0)); + clrbits_le32(&ch[chn].phy.misc_ctrl1, 1 << MISC_CTRL1_R_DMPHYRST_SHIFT); + clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_RDATRST_SHIFT); +} + +static void dramc_set_gating_mode(u8 chn, u8 mode) +{ + u8 vref = 0, burst = 0; + + if (mode) { + vref = 2; + burst = 1; + } + + clrsetbits_le32(&ch[chn].ao.stbcal1, 0x1 << 5, burst << 5); + setbits_le32(&ch[chn].ao.stbcal, 0x1 << 30); + + for (u8 b = 0; b < 2; b++) { + clrsetbits_le32(&ch[chn].phy.b[b].dq[6], 0x3 << 14, vref << 14); + setbits_le32(&ch[chn].phy.b[b].dq[9], 0x1 << 5); + clrbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + setbits_le32(&ch[chn].phy.b[b].dq[9], (0x1 << 4) | (0x1 << 0)); + } +} + +static void dramc_rx_dqs_gating_cal(u8 chn, u8 rank) +{ + u8 pass_begin[DQS_NUMBER], pass_count[DQS_NUMBER]; + u8 min_coarse_tune2t[DQS_NUMBER], min_coarse_tune0p5t[DQS_NUMBER], + min_fine_tune[DQS_NUMBER]; + u8 best_fine_tune[DQS_NUMBER], best_coarse_tune0p5t[DQS_NUMBER], + best_coarse_tune2t[DQS_NUMBER]; + u8 best_fine_tune_p1[DQS_NUMBER], best_coarse_tune0p5t_p1[DQS_NUMBER], + best_coarse_tune2t_p1[DQS_NUMBER]; + + u8 best_coarse_large_rodt[DQS_NUMBER], + best_coarse_0p5t_rodt[DQS_NUMBER]; + u8 best_coarse_large_rodt_p1[DQS_NUMBER], + best_coarse_0p5t_rodt_p1[DQS_NUMBER]; + u32 coarse_start = 18, coarse_end = coarse_start + 24; + u32 debug_cnt[DQS_NUMBER]; + + u8 dqs_high[DQS_NUMBER], dqs_transition[DQS_NUMBER]; + u8 dly_coarse_large_cnt[DQS_NUMBER], dly_coarse_0p5t_cnt[DQS_NUMBER], + dly_fine_tune_cnt[DQS_NUMBER]; + u8 dqs; + u8 mr1_value[FSP_MAX] = { 0x56, 0x56 }; + + u32 value_store[MAX_BACKUP_REG_CNT]; + u32 *regs_backup[] = { + &ch[chn].ao.stbcal, + &ch[chn].ao.stbcal1, + &ch[chn].ao.ddrconf0, + &ch[chn].ao.spcmd, + &ch[chn].ao.refctrl0, + &ch[chn].phy.b[0].dq[6], + &ch[chn].phy.b[1].dq[6], + }; + dramc_save_restore_multi_reg(SAVE_VALUE, value_store, + regs_backup, ARRAY_SIZE(regs_backup)); + + rx_dqs_isi_pulse_cg_switch(chn, DISABLE); + dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] | 0x80); + clrbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_PBREFEN_SHIFT); + + dramc_hw_gating_onoff(chn, GATING_OFF); + + setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBENCMPEN_SHIFT); + setbits_le32(&ch[chn].ao.stbcal1, 1 << STBCAL1_STBCNT_LATCH_EN_SHIFT); + clrbits_le32(&ch[chn].ao.ddrconf0, 1 << DDRCONF0_DM4TO1MODE_SHIFT); + setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTEN_SHIFT); + + udelay(4); + setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + udelay(1); + clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_DQSGCNTRST_SHIFT); + clrsetbits_le32(&ch[chn].phy.misc_ctrl1, + 1 << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT, + rank << MISC_CTRL1_R_DMSTBENCMP_RK_OPT_SHIFT); + + u32 dummy_rd_backup = read32(&ch[chn].ao.dummy_rd); + dramc_engine2_init(chn, rank, 0x23, 1); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + pass_begin[dqs] = 0; + pass_count[dqs] = 0; + dqs_high[dqs] = 0; + dqs_transition[dqs] = 0; + dly_coarse_large_cnt[dqs] = 0; + dly_coarse_0p5t_cnt[dqs] = 0; + dly_fine_tune_cnt[dqs] = 0; + } + + dramc_show("[Gating]\n"); + for (u32 coarse_tune = coarse_start; coarse_tune < coarse_end; + coarse_tune += DQS_GW_COARSE_STEP) { + u32 dly_coarse_large_rodt = 0; + u32 dly_coarse_0p5t_rodt = 0; + u32 dly_coarse_large_rodt_p1 = 4; + u32 dly_coarse_0p5t_rodt_p1 = 4; + + u8 dly_coarse_large = coarse_tune / RX_DQS_CTL_LOOP; + u8 dly_coarse_0p5t = coarse_tune % RX_DQS_CTL_LOOP; + u32 dly_coarse_large_p1 = + (coarse_tune + DQS_GW_FREQ_DIV) / RX_DQS_CTL_LOOP; + u32 dly_coarse_0p5t_p1 = + (coarse_tune + DQS_GW_FREQ_DIV) % RX_DQS_CTL_LOOP; + u32 value = (dly_coarse_large << 3) + dly_coarse_0p5t; + + if (value >= 11) { + value -= 11; + dly_coarse_large_rodt = value >> 3; + dly_coarse_0p5t_rodt = + value - (dly_coarse_large_rodt << 3); + + value = (dly_coarse_large << 3) + dly_coarse_0p5t - 11; + dly_coarse_large_rodt_p1 = value >> 3; + dly_coarse_0p5t_rodt_p1 = + value - (dly_coarse_large_rodt_p1 << 3); + } + + write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + ((u32) dly_coarse_large << + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | + ((u32) dly_coarse_large << + SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | + (dly_coarse_large_p1 << + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | + (dly_coarse_large_p1 << + SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + ((u32) dly_coarse_0p5t << + SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | + ((u32) dly_coarse_0p5t << + SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | + (dly_coarse_0p5t_p1 << + SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | + (dly_coarse_0p5t_p1 << + SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); + write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + (dly_coarse_large_rodt << + SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | + (dly_coarse_large_rodt << + SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | + (dly_coarse_large_rodt_p1 << + SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | + (dly_coarse_large_rodt_p1 << + SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); + write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + (dly_coarse_0p5t_rodt << + SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | + (dly_coarse_0p5t_rodt << + SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | + (dly_coarse_0p5t_rodt_p1 << + SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | + (dly_coarse_0p5t_rodt_p1 << + SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); + + for (u8 dly_fine_xt = DQS_GW_FINE_START; + dly_fine_xt < DQS_GW_FINE_END; + dly_fine_xt += DQS_GW_FINE_STEP) { + + dramc_set_gating_mode(chn, 0); + + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + dly_fine_xt | (dly_fine_xt << 8)); + + dram_phy_reset(chn); + + setbits_le32(&ch[chn].ao.spcmd, + 1 << SPCMD_DQSGCNTRST_SHIFT); + udelay(1); + clrbits_le32(&ch[chn].ao.spcmd, + 1 << SPCMD_DQSGCNTRST_SHIFT); + + dramc_engine2_run(chn, TE_OP_READ_CHECK); + + u32 result_r = read32(&ch[chn].phy.misc_stberr_rk0_r) & + MISC_STBERR_RK_R_STBERR_RK_R_MASK; + u32 result_f = read32(&ch[chn].phy.misc_stberr_rk0_f) & + MISC_STBERR_RK_F_STBERR_RK_F_MASK; + debug_cnt[0] = read32(&ch[chn].nao.dqsgnwcnt[0]); + debug_cnt[1] = (debug_cnt[0] >> 16) & 0xffff; + debug_cnt[0] &= 0xffff; + + dramc_set_gating_mode(chn, 1); + dramc_engine2_run(chn, TE_OP_READ_CHECK); + + find_dly_tune(chn, dly_coarse_large, dly_coarse_0p5t, + dly_fine_xt, dqs_high, dly_coarse_large_cnt, + dly_coarse_0p5t_cnt, + dly_fine_tune_cnt, dqs_transition); + + dramc_show("%d %d %d |", + dly_coarse_large, dly_coarse_0p5t, + dly_fine_xt); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_show("%X ", debug_cnt[dqs]); + + dramc_show(" |"); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + dramc_show("(%X %X)", + (result_f >> (DQS_BIT_NUMBER * dqs)) & 0xff, + (result_r >> (DQS_BIT_NUMBER * dqs)) & 0xff); + } + + dramc_show("\n"); + find_gating_window(result_r, result_f, &debug_cnt[0], + dly_coarse_large, dly_coarse_0p5t, + &pass_begin[0], &pass_count[0], + &dly_fine_xt, &coarse_tune, &dqs_high[0]); + } + } + + dramc_engine2_end(chn); + write32(&ch[chn].ao.dummy_rd, dummy_rd_backup); + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + pass_count[dqs] = dqs_transition[dqs]; + min_fine_tune[dqs] = dly_fine_tune_cnt[dqs]; + min_coarse_tune0p5t[dqs] = dly_coarse_0p5t_cnt[dqs]; + min_coarse_tune2t[dqs] = dly_coarse_large_cnt[dqs]; + + u8 tmp_offset = pass_count[dqs] * DQS_GW_FINE_STEP / 2; + u8 tmp_value = min_fine_tune[dqs] + tmp_offset; + best_fine_tune[dqs] = tmp_value % RX_DLY_DQSIENSTB_LOOP; + best_fine_tune_p1[dqs] = best_fine_tune[dqs]; + + tmp_offset = tmp_value / RX_DLY_DQSIENSTB_LOOP; + tmp_value = min_coarse_tune0p5t[dqs] + tmp_offset; + best_coarse_tune0p5t[dqs] = tmp_value % RX_DQS_CTL_LOOP; + + tmp_offset = tmp_value / RX_DQS_CTL_LOOP; + best_coarse_tune2t[dqs] = + min_coarse_tune2t[dqs] + tmp_offset; + + tmp_value = best_coarse_tune0p5t[dqs] + DQS_GW_FREQ_DIV; + best_coarse_tune0p5t_p1[dqs] = tmp_value % RX_DQS_CTL_LOOP; + + tmp_offset = tmp_value / RX_DQS_CTL_LOOP; + best_coarse_tune2t_p1[dqs] = + best_coarse_tune2t[dqs] + tmp_offset; + } + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_show("best DQS%d dly(2T, 0.5T, fine tune)" + " = (%d, %d, %d)\n", + dqs, best_coarse_tune2t[dqs], + best_coarse_tune0p5t[dqs], best_fine_tune[dqs]); + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) + dramc_show("best DQS%d best coarse dly" + "(2T, 0.5T, fine tune) = (%d, %d, %d)\n", + dqs, best_coarse_tune2t_p1[dqs], + best_coarse_tune0p5t_p1[dqs], + best_fine_tune[dqs]); + + dramc_save_restore_multi_reg(RESTORE_VALUE, value_store, + regs_backup, ARRAY_SIZE(regs_backup)); + + dramc_mode_reg_write_by_rank(chn, rank, 0x1, mr1_value[1] & 0x7f); + rx_dqs_isi_pulse_cg_switch(chn, ENABLE); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + ((u32) best_coarse_tune2t[0] << + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_SHIFT) | + ((u32) best_coarse_tune2t[1] << + SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_SHIFT) | + ((u32) best_coarse_tune2t_p1[0] << + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT) | + ((u32) best_coarse_tune2t_p1[1] << + SHURK_SELPH_DQSG0_TX_DLY_DQS1_GATED_P1_SHIFT)); + write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg1, + ((u32) best_coarse_tune0p5t[0] << + SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_SHIFT) | + ((u32) best_coarse_tune0p5t[1] << + SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_SHIFT) | + ((u32) best_coarse_tune0p5t_p1[0] << + SHURK_SELPH_DQSG1_REG_DLY_DQS0_GATED_P1_SHIFT) | + ((u32) best_coarse_tune0p5t_p1[1] << + SHURK_SELPH_DQSG1_REG_DLY_DQS1_GATED_P1_SHIFT)); + + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + u8 tmp_value = (best_coarse_tune2t[dqs] << 3) + + best_coarse_tune0p5t[dqs]; + + if (tmp_value >= 11) { + tmp_value -= 11; + best_coarse_large_rodt[dqs] = tmp_value >> 3; + best_coarse_0p5t_rodt[dqs] = + tmp_value - (best_coarse_large_rodt[dqs] << 3); + + tmp_value = (best_coarse_tune2t_p1[dqs] << 3) + + best_coarse_tune0p5t_p1[dqs] - 11; + best_coarse_large_rodt_p1[dqs] = tmp_value >> 3; + best_coarse_0p5t_rodt_p1[dqs] = + tmp_value - (best_coarse_large_rodt_p1[dqs] << 3); + + dramc_dbg("best RODT dly(2T, 0.5T) = (%d, %d)\n", + best_coarse_large_rodt[dqs], + best_coarse_0p5t_rodt[dqs]); + } else { + + best_coarse_large_rodt[dqs] = 0; + best_coarse_0p5t_rodt[dqs] = 0; + + best_coarse_large_rodt_p1[dqs] = 4; + best_coarse_0p5t_rodt_p1[dqs] = 4; + + dramc_dbg("RxdqsGatingCal Error: best_coarse_tune2t:%d" + " is already 0. RODT cannot be -1 coarse tune\n", + dqs); + } + } + + write32(&ch[chn].ao.shu[0].rk[rank].selph_odten0, + ((u32) best_coarse_large_rodt[0] << + SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_SHIFT) | + ((u32) best_coarse_large_rodt[1] << + SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_SHIFT) | + ((u32) best_coarse_large_rodt_p1[0] << + SHURK_SELPH_ODTEN0_TXDLY_B0_RODTEN_P1_SHIFT) | + ((u32) best_coarse_large_rodt_p1[1] << + SHURK_SELPH_ODTEN0_TXDLY_B1_RODTEN_P1_SHIFT)); + write32(&ch[chn].ao.shu[0].rk[rank].selph_odten1, + ((u32) best_coarse_0p5t_rodt[0] << + SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_SHIFT) | + ((u32) best_coarse_0p5t_rodt[1] << + SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_SHIFT) | + ((u32) best_coarse_0p5t_rodt_p1[0] << + SHURK_SELPH_ODTEN1_DLY_B0_RODTEN_P1_SHIFT) | + ((u32) best_coarse_0p5t_rodt_p1[1] << + SHURK_SELPH_ODTEN1_DLY_B1_RODTEN_P1_SHIFT)); + + write32(&ch[chn].ao.shu[0].rk[rank].dqsien, + best_fine_tune[0] | (best_fine_tune[1] << 8)); + + dram_phy_reset(chn); +} + +static void dramc_rx_dqs_gating_post_process(u8 chn) +{ + u8 dqs, rank_rx_dvs, dqsinctl, rank; + u32 read_dqsinctl, rankinctl_root, xrtr2r, reg_tx_dly_dqsgated_min = 3; + u8 txdly_cal_min = 0xff, txdly_cal_max = 0, tx_dly_dqs_gated = 0; + u32 best_coarse_tune2t[RANK_MAX][DQS_NUMBER]; + u32 best_coarse_tune2t_p1[RANK_MAX][DQS_NUMBER]; + + rank_rx_dvs = reg_tx_dly_dqsgated_min - 1; + + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], + SHU1_BX_DQ7_R_DMRANKRXDVS_MASK, + rank_rx_dvs << SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT); + + for (rank = 0; rank < RANK_MAX; rank++) { + u32 dqsg0 = read32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + best_coarse_tune2t[rank][dqs] = + (dqsg0 >> (dqs * 8)) & + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_MASK; + best_coarse_tune2t_p1[rank][dqs] = + ((dqsg0 >> (dqs * 8)) & + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_MASK) >> + SHURK_SELPH_DQSG0_TX_DLY_DQS0_GATED_P1_SHIFT; + dramc_dbg("rank%d best DQS%d dly(2T, (P1)2T) = (%d, %d)\n", + rank, dqs, best_coarse_tune2t[rank][dqs], + best_coarse_tune2t_p1[rank][dqs]); + + tx_dly_dqs_gated = best_coarse_tune2t[rank][dqs]; + txdly_cal_min = MIN(txdly_cal_min, tx_dly_dqs_gated); + + tx_dly_dqs_gated = best_coarse_tune2t_p1[rank][dqs]; + txdly_cal_max = MAX(txdly_cal_max, tx_dly_dqs_gated); + } + } + + dqsinctl = reg_tx_dly_dqsgated_min - txdly_cal_min; + dramc_dbg("dqsinctl:%d, tx_dly_dqsgated_min %d, txdly_cal_min %d\n", + dqsinctl, reg_tx_dly_dqsgated_min, txdly_cal_min); + + if (dqsinctl != 0) { + txdly_cal_min += dqsinctl; + txdly_cal_max += dqsinctl; + + for (rank = 0; rank < RANK_MAX; rank++) { + dramc_dbg("Rank: %d\n", rank); + for (dqs = 0; dqs < DQS_NUMBER; dqs++) { + best_coarse_tune2t[rank][dqs] += dqsinctl; + best_coarse_tune2t_p1[rank][dqs] += dqsinctl; + + dramc_dbg("best DQS%d dly(2T) = (%d)\n", + dqs, best_coarse_tune2t[rank][dqs]); + dramc_dbg("best DQS%d P1 dly(2T) = (%d)\n", + dqs, best_coarse_tune2t_p1[rank][dqs]); + } + + write32(&ch[chn].ao.shu[0].rk[rank].selph_dqsg0, + (best_coarse_tune2t[rank][0] << 0) | + (best_coarse_tune2t[rank][1] << 8) | + (best_coarse_tune2t_p1[rank][0] << 4) | + (best_coarse_tune2t_p1[rank][1] << 12)); + } + } + + read_dqsinctl = (read32(&ch[chn].ao.shu[0].rk[0].dqsctl) & + SHURK_DQSCTL_DQSINCTL_MASK) - dqsinctl; + if (read_dqsinctl >= 3) { + rankinctl_root = read_dqsinctl - 3; + } else { + rankinctl_root = 0; + dramc_dbg("DQSINCTL < 3, Risk for supporting 1066/RL8\n"); + } + + clrsetbits_le32(&ch[chn].ao.shu[0].rk[0].dqsctl, + SHURK_DQSCTL_DQSINCTL_MASK, + read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); + clrsetbits_le32(&ch[chn].ao.shu[0].rk[1].dqsctl, + SHURK_DQSCTL_DQSINCTL_MASK, + read_dqsinctl << SHURK_DQSCTL_DQSINCTL_SHIFT); + clrsetbits_le32(&ch[chn].ao.shu[0].rankctl, + SHU_RANKCTL_RANKINCTL_PHY_MASK | + SHU_RANKCTL_RANKINCTL_MASK | SHU_RANKCTL_RANKINCTL_ROOT1_MASK, + (read_dqsinctl << SHU_RANKCTL_RANKINCTL_PHY_SHIFT) | + (rankinctl_root << SHU_RANKCTL_RANKINCTL_SHIFT) | + (rankinctl_root << SHU_RANKCTL_RANKINCTL_ROOT1_SHIFT)); + + xrtr2r = MIN(8 + txdly_cal_max + 1, 12); + clrsetbits_le32(&ch[chn].ao.shu[0].actim_xrt, + SHU_ACTIM_XRT_XRTR2R_MASK, + xrtr2r << SHU_ACTIM_XRT_XRTR2R_SHIFT); + + dramc_dbg("TX_dly_DQS gated check: min %d max %d, ChangeDQSINCTL=%d\n" + "DQSINCTL=%d, RANKINCTL=%d, XRTR2R=%d\n", + txdly_cal_min, txdly_cal_max, dqsinctl, + read_dqsinctl, rankinctl_root, xrtr2r); +} + void dramc_calibrate_all_channels(const struct sdram_params *pams) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { @@ -319,6 +970,9 @@ cmd_bus_training(chn, rk, pams); dramc_write_leveling(chn, rk, pams->wr_level); auto_refresh_switch(chn, 1); + dramc_rx_dqs_gating_cal(chn, rk); } + + dramc_rx_dqs_gating_post_process(chn); } } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index f5b6251..761fff6 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -140,4 +140,6 @@ void dramc_sw_impedance(const struct sdram_params *params); void dramc_apply_pre_calibration_config(void); void dramc_calibrate_all_channels(const struct sdram_params *params); +void dramc_save_restore_multi_reg(u8 type, u32 *store_mem, + u32 **addr, u32 count); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/28841 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I504d6d5c9ea01b11a9f2a05b5ee4b5f1af87e23f Gerrit-Change-Number: 28841 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of cmd bus training part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28839 Change subject: mediatek/mt8183: Add DDR driver of cmd bus training part ...................................................................... mediatek/mt8183: Add DDR driver of cmd bus training part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 94 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28839/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index c5ec9c7..0542baa 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -20,6 +20,88 @@ #include <soc/dramc_register.h> #include <soc/dramc_pi_api.h> +static void auto_refresh_switch(u8 chn, u8 option) +{ + clrsetbits_le32(&ch[chn].ao.refctrl0, 1 << REFCTRL0_REFDIS_SHIFT, + (option ? 0 : 1) << REFCTRL0_REFDIS_SHIFT); + + if (option == DISABLE) { + /* because HW will actually disable autorefresh + * after refresh_queue empty, we need to wait quene empty */ + udelay(((read32(&ch[chn].nao.misc_statusa) & + MISC_STATUSA_REFRESH_QUEUE_CNT_MASK) >> + MISC_STATUSA_REFRESH_QUEUE_CNT_SHIFT)*4); + } +} + +static void dramc_cke_fix_onoff(int option, u8 chn) +{ + u8 on = 0, off = 0; + + /* if CKE is dynamic, set both CKE fix On and Off as 0 */ + if (option != CKE_DYNAMIC) { + on = option; + off = (1 - option); + } + + clrsetbits_le32(&ch[chn].ao.ckectrl, + (0x1 << 6) | (0x1 << 7), (on << 6) | (off << 7)); +} + +static void dramc_mode_reg_write(u8 chn, u8 mr_idx, u8 value) +{ + u32 rank = 0; + u32 ckectrl_bak = read32(&ch[chn].ao.ckectrl); + + dramc_cke_fix_onoff(CKE_FIXON, chn); + clrsetbits_le32(&ch[chn].ao.mrs, + MRS_MRSMA_MASK, mr_idx << MRS_MRSMA_SHIFT); + clrsetbits_le32(&ch[chn].ao.mrs, + MRS_MRSOP_MASK, value << MRS_MRSOP_SHIFT); + setbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + + while ((read32(&ch[chn].nao.spcmdresp) & 1) == 0) { + dramc_dbg("wait MRW command fired\n"); + udelay(1); + } + + clrbits_le32(&ch[chn].ao.spcmd, 1 << SPCMD_MRWEN_SHIFT); + setbits_le32(&ch[chn].ao.ckectrl, ckectrl_bak); + + rank = (read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK) >> MRS_MRSRK_SHIFT; + dramc_dbg("Write Rank%d MR%d =0x%x\n", rank, mr_idx, value); +} + +static void dramc_mode_reg_write_by_rank(u8 chn, u8 rank, + u8 mr_idx, u8 value) +{ + u32 mrs_back = read32(&ch[chn].ao.mrs) & MRS_MRSRK_MASK; + + clrsetbits_le32(&ch[chn].ao.mrs, + MRS_MRSRK_MASK, rank << MRS_MRSRK_SHIFT); + dramc_mode_reg_write(chn, mr_idx, value); + clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); +} + +static void cmd_bus_training(u8 chn, u8 rank, + const struct sdram_params *params) +{ + u32 cbt_cs, mr12_value; + + cbt_cs = params->cbt_cs[chn][rank]; + mr12_value = params->cbt_mr12[chn][rank]; + + dramc_dbg("start chn:%d, rank:%d, cbt_cs:0x%x, mr12_value:0x%x\n", + chn, rank, cbt_cs, mr12_value); + + /* cbt_adjust_cs */ + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CS_MASK, cbt_cs << 0); + + /* cbt_set_vref */ + dramc_mode_reg_write_by_rank(chn, rank, 12, mr12_value); +} + static void dramc_read_dbi_onoff(u8 onoff) { for (u8 chn = 0; chn < CHANNEL_MAX; chn++) @@ -203,3 +285,13 @@ } } +void dramc_calibrate_all_channels(const struct sdram_params *pams) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) { + for (u8 rk = RANK_0; rk < RANK_MAX; rk++) { + dramc_show("start K ch:%d, rank:%d\n", chn, rk); + auto_refresh_switch(chn, 0); + cmd_bus_training(chn, rk, pams); + } + } +} diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index ba913a2..eb75890 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -296,6 +296,7 @@ static void do_calib(const struct sdram_params *params) { dramc_apply_pre_calibration_config(); + dramc_calibrate_all_channels(params); } void mt_set_emi(const struct sdram_params *params) diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index ed9eb81..f5b6251 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -139,4 +139,5 @@ u32 dramc_get_broadcast(void); void dramc_sw_impedance(const struct sdram_params *params); void dramc_apply_pre_calibration_config(void); +void dramc_calibrate_all_channels(const struct sdram_params *params); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/28839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Gerrit-Change-Number: 28839 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of write leveling part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28840 Change subject: mediatek/mt8183: Add DDR driver of write leveling part ...................................................................... mediatek/mt8183: Add DDR driver of write leveling part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c 1 file changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/28840/1 diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c index 0542baa..7b42287 100644 --- a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -83,6 +83,31 @@ clrsetbits_le32(&ch[chn].ao.mrs, MRS_MRSRK_MASK, mrs_back); } +static void dramc_write_leveling(u8 chn, u8 rank, + const u8 wr_level[CHANNEL_MAX][RANK_MAX][DQS_NUMBER]) +{ + s32 clock_delay_max = 0; + + dramc_show("chn:%d, rank:%d params write level:0x%x, 0x%x\n", + chn, rank, wr_level[chn][rank][0], wr_level[chn][rank][1]); + + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[9], + SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_MASK, + clock_delay_max << SHU1_CA_CMD9_RG_RK_ARFINE_TUNE_CLK_SHIFT); + + for (u8 i = 0; i < DQS_NUMBER; i++) { + s32 wrlevel_dq_delay = wr_level[chn][rank][i] + 0x10; + assert(wrlevel_dq_delay < 0x40); + + clrsetbits_le32(&ch[chn].phy.shu[0].rk[rank].b[i].dq[7], + FINE_TUNE_PBYTE_MASK | FINE_TUNE_DQM_MASK | + FINE_TUNE_DQ_MASK, + (wr_level[chn][rank][i] << FINE_TUNE_PBYTE_SHIFT) | + (wrlevel_dq_delay << FINE_TUNE_DQM_SHIFT) | + (wrlevel_dq_delay << FINE_TUNE_DQ_SHIFT)); + } +} + static void cmd_bus_training(u8 chn, u8 rank, const struct sdram_params *params) { @@ -292,6 +317,8 @@ dramc_show("start K ch:%d, rank:%d\n", chn, rk); auto_refresh_switch(chn, 0); cmd_bus_training(chn, rk, pams); + dramc_write_leveling(chn, rk, pams->wr_level); + auto_refresh_switch(chn, 1); } } } -- To view, visit https://review.coreboot.org/28840 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibde5f613c61c36f5c9b405326fd18a3fd16cca56 Gerrit-Change-Number: 28840 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Change in coreboot[master]: mediatek/mt8183: Add DDR driver of pre-calibration part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/28838 Change subject: mediatek/mt8183: Add DDR driver of pre-calibration part ...................................................................... mediatek/mt8183: Add DDR driver of pre-calibration part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/Makefile.inc A src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 213 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/28838/1 diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index e9b5f42..ec2a9c0 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -22,6 +22,7 @@ romstage-y += ../common/cbmem.c emi.c romstage-y += dramc_pi_basic_api.c +romstage-y += dramc_pi_calibration_api.c romstage-y += memory.c romstage-y += ../common/gpio.c gpio.c romstage-y += ../common/mmu_operations.c mmu_operations.c diff --git a/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c new file mode 100644 index 0000000..c5ec9c7 --- /dev/null +++ b/src/soc/mediatek/mt8183/dramc_pi_calibration_api.c @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <delay.h> +#include <arch/io.h> +#include <soc/emi.h> +#include <soc/dramc_register.h> +#include <soc/dramc_pi_api.h> + +static void dramc_read_dbi_onoff(u8 onoff) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 b = 0; b < 2; b++) + clrsetbits_le32(&ch[chn].phy.shu[0].b[b].dq[7], + 0x1 << SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT, + onoff << SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT); +} + +static void dramc_write_dbi_onoff(u8 onoff) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + clrsetbits_le32(&ch[chn].ao.shu[0].wodt, + 0x1 << SHU1_WODT_DBIWR_SHIFT, + onoff << SHU1_WODT_DBIWR_SHIFT); +} + +static void enable_dramc_phy_dcm_2_channel(u8 chn, u8 en) +{ + u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX; + + if (!en) { + clrsetbits_le32(&ch[chn].phy.misc_cg_ctrl0, + (0x1 << 20) | (0x1 << 19) | 0x3FF << 8, + (0x0 << 20) | (0x1 << 19) | 0x3FF << 8); + + for (shu = 0; shu < shu_cnt; shu++) { + setbits_le32(&ch[chn].phy.shu[shu].b[0].dq[8], + 0x1FFF << 19); + setbits_le32(&ch[chn].phy.shu[shu].b[1].dq[8], + 0x1FFF << 19); + clrbits_le32(&ch[chn].phy.shu[shu].ca_cmd[8], + 0x1FFF << 19); + } + clrbits_le32(&ch[chn].phy.misc_cg_ctrl5, + (0x7 << 16) | (0x7 << 20)); + } +} + +static void dramc_enable_phy_dcm(u8 en) +{ + u32 broadcast_bak = dramc_get_broadcast(); + u8 shu, shu_cnt = DRAM_DFS_SHUFFLE_MAX; + u8 chn = 0; + + dramc_set_broadcast(DRAMC_BROADCAST_OFF); + + for (chn = 0; chn < CHANNEL_MAX ; chn++) { + clrbits_le32(&ch[chn].phy.b[0].dll_fine_tune[1], 0x1 << 20); + clrbits_le32(&ch[chn].phy.b[1].dll_fine_tune[1], 0x1 << 20); + clrbits_le32(&ch[chn].phy.ca_dll_fine_tune[1], 0x1 << 20); + + for (shu = 0; shu < shu_cnt; shu++) { + setbits_le32(&ch[chn].phy.shu[shu].b[0].dll[0], + 0x1 << 0); + setbits_le32(&ch[chn].phy.shu[shu].b[1].dll[0], + 0x1 << 0); + setbits_le32(&ch[chn].phy.shu[shu].ca_dll[0], + 0x1 << 0); + } + + clrsetbits_le32(&ch[chn].ao.dramc_pd_ctrl, + (0x1 << 0) | (0x1 << 1) | (0x1 << 2) | + (0x1 << 5) | (0x1 << 26) | (0x1 << 30) | (0x1 << 31), + ((en ? 0x1 : 0) << 0) | ((en ? 0x1 : 0) << 1) | + ((en ? 0x1 : 0) << 2) | ((en ? 0 : 0x1) << 5) | + ((en ? 0 : 0x1) << 26) | ((en ? 0x1 : 0) << 30) | + ((en ? 0x1 : 0) << 31)); + + /* DCM on :CHANNEL_EMI free run ; DCM off :mem_dcm */ + assert(en == 0 || en == 1); + write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033E | (0x40 << en)); + write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033F | (0x40 << en)); + write32(&ch[chn].phy.misc_cg_ctrl2, 0x8060033E | (0x40 << en)); + + clrsetbits_le32(&ch[chn].phy.misc_ctrl3, 0x3 << 26, + (en ? 0 : 0x3) << 26); + for (shu = 0; shu < shu_cnt; shu++) { + clrsetbits_le32(&ch[chn].phy.shu[shu].b[0].dq[7], + 0x7 << 17, (en ? 0x7 : 0) << 17); + clrsetbits_le32(&ch[chn].phy.shu[shu].b[1].dq[7], + 0x7 << 17, (en ? 0x7 : 0) << 17); + clrsetbits_le32(&ch[chn].phy.shu[shu].ca_cmd[7], + 0x7 << 17, (en ? 0x7 : 0) << 17); + } + } + enable_dramc_phy_dcm_2_channel(chn, en); + dramc_set_broadcast(broadcast_bak); +} + +static void reset_delay_chain_before_calibration(void) +{ + for (u8 chn = 0; chn < CHANNEL_MAX; chn++) + for (u8 rank = 0; rank < RANK_MAX; rank++) { + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].ca_cmd[0], + 0xffffff << 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[0], + 0xfffffff << 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[0], + 0xfffffff << 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[0].dq[1], + 0xf << 0); + clrbits_le32(&ch[chn].phy.shu[0].rk[rank].b[1].dq[1], + 0xf << 0); + } +} + +static void dramc_hw_gating_onoff(u8 chn, u8 onoff) +{ + clrsetbits_le32(&ch[chn].ao.shuctrl2, 0x3 << 14, + (onoff << 14) | (onoff << 15)); + clrsetbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28, onoff << 28); + clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 24, onoff << 24); + clrsetbits_le32(&ch[chn].ao.stbcal, 0x1 << 22, onoff << 22); +} + +static void dramc_rx_input_delay_tracking_init_by_freq(u8 chn) +{ + u8 delay = 3; + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[5], 0x7 << 20, delay << 20); + clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[5], 0x7 << 20, delay << 20); + clrsetbits_le32(&ch[chn].phy.shu[0].b[0].dq[7], + (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13)); + clrsetbits_le32(&ch[chn].phy.shu[0].b[1].dq[7], + (0x1 << 12) | (0x1 << 13), (0x0 << 12) | (0x0 << 13)); +} + +void dramc_apply_pre_calibration_config(void) +{ + u8 shu = 0; + + dramc_enable_phy_dcm(0); + reset_delay_chain_before_calibration(); + + setbits_le32(&ch[0].ao.shu[0].conf[3], 0x1ff << 16); + setbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 24); + clrsetbits_le32(&ch[0].ao.shu[0].scintv, 0x1f << 1, 0x1b << 1); + + for (shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits_le32(&ch[0].ao.shu[shu].conf[3], 0x1ff << 0); + + clrbits_le32(&ch[0].ao.dramctrl, 0x1 << 18); + clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 31); + clrbits_le32(&ch[0].ao.spcmdctrl, 0x1 << 30); + clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 26); + clrbits_le32(&ch[0].ao.dqsoscr, 0x1 << 25); + + dramc_write_dbi_onoff(DBI_OFF); + dramc_read_dbi_onoff(DBI_OFF); + + for (int chn = 0; chn < CHANNEL_MAX; chn++) { + setbits_le32(&ch[chn].ao.spcmdctrl, 0x1 << 29); + setbits_le32(&ch[chn].ao.dqsoscr, 0x1 << 24); + for (shu = 0; shu < DRAM_DFS_SHUFFLE_MAX; shu++) + setbits_le32(&ch[chn].ao.shu[shu].scintv, 0x1 << 30); + + clrbits_le32(&ch[chn].ao.dummy_rd, (0x1 << 7) | (0x7 << 20)); + dramc_hw_gating_onoff(chn, GATING_OFF); + clrbits_le32(&ch[chn].ao.stbcal2, 0x1 << 28); + + setbits_le32(&ch[chn].phy.misc_ctrl1, + (0x1 << 7) | (0x1 << 11)); + clrbits_le32(&ch[chn].ao.refctrl0, 0x1 << 18); + clrbits_le32(&ch[chn].ao.mrs, 0x3 << 24); + setbits_le32(&ch[chn].ao.mpc_option, 0x1 << 17); + clrsetbits_le32(&ch[chn].phy.b[0].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits_le32(&ch[chn].phy.b[1].dq[6], 0x3 << 0, 0x1 << 0); + clrsetbits_le32(&ch[chn].phy.ca_cmd[6], 0x3 << 0, 0x1 << 0); + setbits_le32(&ch[chn].ao.dummy_rd, 0x1 << 25); + setbits_le32(&ch[chn].ao.drsctrl, 0x1 << 0); + clrbits_le32(&ch[chn].ao.shu[1].drving[1], 0x1 << 31); + + dramc_rx_input_delay_tracking_init_by_freq(chn); + } + + for (size_t r = 0; r < 2; r++) { + for (size_t b = 0; b < 2; b++) + clrbits_le32(&ch[0].phy.r[r].b[b].rxdvs[2], + (0x1 << 28) | (0x1 << 23) | (0x3 << 30)); + clrbits_le32(&ch[0].phy.r0_ca_rxdvs[2], 0x3 << 30); + } +} + diff --git a/src/soc/mediatek/mt8183/emi.c b/src/soc/mediatek/mt8183/emi.c index 37997aa..ba913a2 100644 --- a/src/soc/mediatek/mt8183/emi.c +++ b/src/soc/mediatek/mt8183/emi.c @@ -293,7 +293,13 @@ emi_init2(params); } +static void do_calib(const struct sdram_params *params) +{ + dramc_apply_pre_calibration_config(); +} + void mt_set_emi(const struct sdram_params *params) { init_dram(params); + do_calib(params); } diff --git a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h index af96316..ed9eb81 100644 --- a/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h @@ -138,4 +138,5 @@ void dramc_set_broadcast(u32 onoff); u32 dramc_get_broadcast(void); void dramc_sw_impedance(const struct sdram_params *params); +void dramc_apply_pre_calibration_config(void); #endif /* _DRAMC_PI_API_MT8183_H */ -- To view, visit https://review.coreboot.org/28838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If462126df31468ef55ec52e2061b9f98d3015f61 Gerrit-Change-Number: 28838 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2018