coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Enable S4 sleep state support
by Subrata Banik (Code Review) 01 Oct '18

01 Oct '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/28846 ) Change subject: soc/intel/cannonlake: Enable S4 sleep state support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Gerrit-Change-Number: 28846 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 07:51:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Enable S4 sleep state support
by Subrata Banik (Code Review) 01 Oct '18

01 Oct '18

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/28846 ) Change subject: soc/intel/cannonlake: Enable S4 sleep state support ...................................................................... Patch Set 1: i think should good but adding Chrome team to confirm. -- To view, visit https://review.coreboot.org/28846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Gerrit-Change-Number: 28846 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Rajat Jain <rajatja(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 07:51:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Enable S4 sleep state support
by Kin Wai Ng (Code Review) 01 Oct '18

01 Oct '18

Kin Wai Ng has posted comments on this change. ( https://review.coreboot.org/28846 ) Change subject: soc/intel/cannonlake: Enable S4 sleep state support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Gerrit-Change-Number: 28846 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Kin Wai Ng <kin.wai.ng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 07:47:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mc_apl1: Set up SPI OPCODE menu before locking
by Mario Scheithauer (Code Review) 01 Oct '18

01 Oct '18

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/28834 ) Change subject: mc_apl1: Set up SPI OPCODE menu before locking ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/28834/1/src/mainboard/siemens/mc_apl1/mainb… File src/mainboard/siemens/mc_apl1/mainboard.c: https://review.coreboot.org/#/c/28834/1/src/mainboard/siemens/mc_apl1/mainb… PS1, Line 46: Byte Program should that be 'Page Program'? -- To view, visit https://review.coreboot.org/28834 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Gerrit-Change-Number: 28834 Gerrit-PatchSet: 1 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 07:43:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28847 Change subject: src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse ...................................................................... src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/include/soc/msr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28847/1 diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 6617d7f..c63c921 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -26,7 +26,7 @@ #define ENERGY_POLICY_NORMAL 6 #define ENERGY_POLICY_POWERSAVE 15 #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 -#define IA32_PLATFORM_DCA_CAP 0x1f9 +#define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_VR_MISC_CONFIG2 0x636 #endif -- To view, visit https://review.coreboot.org/28847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Gerrit-Change-Number: 28847 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/cannonlake: Enable S4 sleep state support
by PraveenX Hodagatta Pranesh (Code Review) 01 Oct '18

01 Oct '18

PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28846 Change subject: soc/intel/cannonlake: Enable S4 sleep state support ...................................................................... soc/intel/cannonlake: Enable S4 sleep state support Add ACPI entry in sleepstates.asl to support S4(hibernate). TEST:boot to Windows on CFL RVP11 & RVP8, verified hibernate functionality. Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com> --- M src/soc/intel/cannonlake/acpi/sleepstates.asl 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/28846/1 diff --git a/src/soc/intel/cannonlake/acpi/sleepstates.asl b/src/soc/intel/cannonlake/acpi/sleepstates.asl index d19f080..2d84a66 100644 --- a/src/soc/intel/cannonlake/acpi/sleepstates.asl +++ b/src/soc/intel/cannonlake/acpi/sleepstates.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2017 Intel Corp. + * Copyright (C) 2018 Intel Corp. * * * This program is free software; you can redistribute it and/or modify @@ -17,4 +17,5 @@ Name (\_S0, Package () { 0x0, 0x0, 0x0, 0x0 }) Name (\_S3, Package () { 0x5, 0x5, 0x0, 0x0 }) +Name (\_S4, Package () { 0x6, 0x6, 0x0, 0x0 }) Name (\_S5, Package () { 0x7, 0x7, 0x0, 0x0 }) -- To view, visit https://review.coreboot.org/28846 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I751c774e6ec7fd89ac3af5a619033bd38a759281 Gerrit-Change-Number: 28846 Gerrit-PatchSet: 1 Gerrit-Owner: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com>

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Change in coreboot[master]: drivers/generic: Add support for providing DSD properties
by HARSHAPRIYA N (Code Review) 01 Oct '18

01 Oct '18

HARSHAPRIYA N has posted comments on this change. ( https://review.coreboot.org/28796 ) Change subject: drivers/generic: Add support for providing DSD properties ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/28796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ca6614f1ef322397618676bbf6da898bef18990 Gerrit-Change-Number: 28796 Gerrit-PatchSet: 6 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 06:12:53 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD
by HARSHAPRIYA N (Code Review) 01 Oct '18

01 Oct '18

HARSHAPRIYA N has posted comments on this change. ( https://review.coreboot.org/28797 ) Change subject: mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSD ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/28797 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Gerrit-Change-Number: 28797 Gerrit-PatchSet: 6 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Benson Leung <bleung(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: HARSHAPRIYA N <harshapriya.n(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Sathyanarayana Nujella <sathyanarayana.nujella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 06:12:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mediatek/mt8183: Add DDR driver of runtime config part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28844 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add DDR driver of runtime config part ...................................................................... mediatek/mt8183: Add DDR driver of runtime config part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563 Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_basic_api.c M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 4 files changed, 228 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/28844/2 -- To view, visit https://review.coreboot.org/28844 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id1e8862ff6feb9628d37fe5300780ff56865a563 Gerrit-Change-Number: 28844 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mediatek/mt8183: Add DDR driver of cmd bus training part
by Tristan Hsieh (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28839 to look at the new patch set (#2). Change subject: mediatek/mt8183: Add DDR driver of cmd bus training part ...................................................................... mediatek/mt8183: Add DDR driver of cmd bus training part BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui, and inits DRAM successfully with related patches. Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/dramc_pi_calibration_api.c M src/soc/mediatek/mt8183/emi.c M src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h 3 files changed, 95 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/28839/2 -- To view, visit https://review.coreboot.org/28839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icb281f1b23c637971497eb28ed428235adf42f2d Gerrit-Change-Number: 28839 Gerrit-PatchSet: 2 Gerrit-Owner: Tristan Hsieh <tristan.shieh(a)mediatek.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018