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Change in coreboot[master]: src: Move IA32_MISC_ENABLE to x86/msr.h
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28855 Change subject: src: Move IA32_MISC_ENABLE to x86/msr.h ...................................................................... src: Move IA32_MISC_ENABLE to x86/msr.h Change-Id: I5d39a1834610ef054c14ce1a7637f44e715d0654 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_106cx/model_106cx_init.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/model_6ex/model_6ex_init.c M src/cpu/intel/model_6fx/model_6fx_init.c M src/cpu/intel/speedstep/speedstep.c M src/cpu/intel/turbo/turbo.c M src/cpu/via/nano/nano_init.c M src/include/cpu/intel/speedstep.h M src/include/cpu/intel/turbo.h M src/include/cpu/x86/msr.h M src/northbridge/intel/nehalem/early_init.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/cpu.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/tsc_freq.c 27 files changed, 36 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28855/1 diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 29a868d..eb4d6a9 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -25,7 +25,6 @@ #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 169744a..194fc12 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -26,7 +26,6 @@ #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 7533a6b..b4e8c88 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -40,7 +40,6 @@ #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 0d9169b..ce5dac4 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -190,7 +190,7 @@ const u32 sub_cstates = cpuid_edx(5); - msr = rdmsr(IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 3); /* TM1 enable */ if (tm2) msr.lo |= (1 << 13); /* TM2 enable */ @@ -220,11 +220,11 @@ if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32))) msr.hi &= ~(1 << (38 - 32)); - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); if (eist) { msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */ - wrmsr(IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index dd7bbc8..6bf21fd 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -56,7 +56,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index de1282b..445d313 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -25,7 +25,6 @@ #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 4a40ac3..cbfa6ae 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -25,7 +25,6 @@ #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) #define IA32_PLATFORM_DCA_CAP 0x1f8 -#define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 96830c4..8d68b9e 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -58,7 +58,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 static void configure_misc(void) { msr_t msr; diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index a1433f6..9dd1223 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -59,7 +59,6 @@ wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); } -#define IA32_MISC_ENABLE 0x1a0 #define IA32_PECI_CTL 0x5a0 static void configure_misc(void) diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c index 441f2a3..43d5b5a 100644 --- a/src/cpu/intel/speedstep/speedstep.c +++ b/src/cpu/intel/speedstep/speedstep.c @@ -72,7 +72,7 @@ msr = rdmsr(MSR_FSB_CLOCK_VCC); if ((msr.hi & (1 << (63 - 32))) && /* supported and */ - !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { + !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) { /* not disabled */ params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); params->turbo.is_turbo = 1; diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c index 5583c46..c31f4c0 100644 --- a/src/cpu/intel/turbo/turbo.c +++ b/src/cpu/intel/turbo/turbo.c @@ -68,7 +68,7 @@ cpuid_regs = cpuid(CPUID_LEAF_PM); turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE); - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO); if (!turbo_cap && turbo_en) { @@ -97,9 +97,9 @@ /* Only possible if turbo is available but hidden */ if (get_turbo_state() == TURBO_DISABLED) { /* Clear Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi &= ~H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_ENABLED); @@ -115,9 +115,9 @@ msr_t msr; /* Set Turbo Disable bit in Misc Enables */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi |= H_MISC_DISABLE_TURBO; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Update cached turbo state */ set_global_turbo_state(TURBO_UNAVAILABLE); diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index c8b054c..985a3c7 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -28,7 +28,6 @@ #define MODEL_NANO_3000_B0 0x8 #define MODEL_NANO_3000_B2 0xa -#define MSR_IA32_MISC_ENABLE 0x000001a0 #define NANO_MYSTERIOUS_MSR 0x120e static void nano_finish_fid_vid_transition(void) @@ -94,9 +93,9 @@ { msr_t msr; /* Enable Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable 6 bit or 7-bit VRM support * This MSR is not documented by VIA docs, other than setting these @@ -114,24 +113,24 @@ nano_set_max_fid_vid(); /* Enable TM3 */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 3) | (1 << 13) ); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); u8 stepping = ( cpuid_eax(0x1) ) &0xf; if (stepping >= MODEL_NANO_3000_B0) { /* Hello Nano 3000. The Terminator needs a CPU upgrade */ /* Enable C1e, C2e, C3e, and C4e states */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */ msr.hi |= (1 << 0); /* C4e */ - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } /* Lock on Powersaver */ - msr = rdmsr(MSR_IA32_MISC_ENABLE); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 20); - wrmsr(MSR_IA32_MISC_ENABLE, msr); + wrmsr(IA32_MISC_ENABLE, msr); } static void nano_init(struct device *dev) diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index d8b73f2..2413b44 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -36,7 +36,7 @@ /* Speedstep related MSRs */ #define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 +#define IA32_MISC_ENABLE 0x1A0 #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 58f4831..0880ebb 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -20,7 +20,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index b37eb83..02c698d 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -25,6 +25,9 @@ #define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b +#define IA32_MISC_ENABLE 0x1a0 +/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ +#define BURST_MODE_DISABLE (1 << 6) #define MSR_IA32_PAT 0x277 #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 0a9b408..1ebb2a5 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -110,11 +110,11 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.hi &= ~0x00000040; m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } m = rdmsr(MSR_FSB_CLOCK_VCC); @@ -124,9 +124,9 @@ m.lo = (m.lo & ~0xff) | reg8; wrmsr(IA32_PERF_CTL, m); - m = rdmsr(MSR_IA32_MISC_ENABLES); + m = rdmsr(IA32_MISC_ENABLE); m.lo |= 0x10000; - wrmsr(MSR_IA32_MISC_ENABLES, m); + wrmsr(IA32_MISC_ENABLE, m); } void nehalem_early_initialization(int chipset_type) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index caa3bbf..928679f 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -54,7 +54,7 @@ REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE, (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable support for MONITOR and MWAIT instructions */ - REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), + REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0), #endif /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0), diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index fa0c40a..dd60345 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -23,7 +23,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 0aee1d7..f9c3014 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 207a27d..ec0cbe3 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -24,7 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index de82e23..72dbca5 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -67,14 +67,14 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Enable Burst Mode */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.hi = 0; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* * Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 5e32e15..437aef0 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -29,7 +29,6 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 13276a6..0ceef9a 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -45,9 +45,6 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 -/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ -#define BURST_MODE_DISABLE (1 << 6) #define MSR_TEMPERATURE_TARGET 0x1a2 #define MSR_PREFETCH_CTL 0x1a4 #define PREFETCH_L1_DISABLE (1 << 0) diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index b7b5550..676fab7 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -44,9 +44,9 @@ /* Enable speed step. */ if (get_turbo_state() == TURBO_ENABLED) { - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); } } diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index cc87871..d63cc04 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -31,7 +31,6 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index e6143ae..6a2ce1a 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 -#define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 #define MSR_PKG_POWER_LIMIT 0x610 diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 0aee1d7..f9c3014 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -60,9 +60,9 @@ msr_t msr; /* Enable speed step. */ - msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= (1 << 16); - wrmsr(MSR_IA32_MISC_ENABLES, msr); + wrmsr(IA32_MISC_ENABLE, msr); /* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of * the PERF_CTL. */ -- To view, visit https://review.coreboot.org/28855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d39a1834610ef054c14ce1a7637f44e715d0654 Gerrit-Change-Number: 28855 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src: Move IA32_THERM_INTERRUPT to x86/msr.h
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28854 Change subject: src: Move IA32_THERM_INTERRUPT to x86/msr.h ...................................................................... src: Move IA32_THERM_INTERRUPT to x86/msr.h Change-Id: I9d0a36d07d114f48894977c0b80ff0ff9f776ed4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/x86/msr.h M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/cannonlake/include/soc/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/skylake/include/soc/msr.h 10 files changed, 1 insertion(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/28854/1 diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 87f0525..29a868d 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -27,7 +27,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 135a3f8..169744a 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -28,7 +28,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index d1924cf..7533a6b 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -42,7 +42,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f26ac0f..de1282b 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -29,7 +29,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 606a65c..4a40ac3 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -27,7 +27,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 31449ed..b37eb83 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -24,6 +24,7 @@ #define PLATFORM_INFO_SET_TDP (1 << 29) #define IA32_PERF_STATUS 0x198 #define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b #define MSR_IA32_PAT 0x277 #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index f26ec66..5e32e15 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -34,7 +34,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/cannonlake/include/soc/msr.h b/src/soc/intel/cannonlake/include/soc/msr.h index 6617d7f..86e13ab 100644 --- a/src/soc/intel/cannonlake/include/soc/msr.h +++ b/src/soc/intel/cannonlake/include/soc/msr.h @@ -20,7 +20,6 @@ #include <intelblocks/msr.h> #define MSR_PIC_MSG_CONTROL 0x2e -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index 8a07865..cc87871 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -36,7 +36,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 780f94f..bfe3671 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -24,7 +24,6 @@ #define EMULATE_PM_TMR_EN (1 << 16) #define EMULATE_DELAY_OFFSET_VALUE 20 #define EMULATE_DELAY_VALUE 0x13 -#define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 #define ENERGY_POLICY_NORMAL 6 -- To view, visit https://review.coreboot.org/28854 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9d0a36d07d114f48894977c0b80ff0ff9f776ed4 Gerrit-Change-Number: 28854 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Move IA32_PERF_{STATUS, CTL} to x86/msr.h
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28853 Change subject: src: Move IA32_PERF_{STATUS,CTL} to x86/msr.h ...................................................................... src: Move IA32_PERF_{STATUS,CTL} to x86/msr.h Change-Id: I7f884379bcaec8340031c914107a7277d620f448 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/via/nano/nano_init.c M src/include/cpu/intel/speedstep.h M src/include/cpu/x86/msr.h M src/soc/intel/baytrail/include/soc/msr.h M src/soc/intel/baytrail/tsc_freq.c M src/soc/intel/braswell/include/soc/msr.h M src/soc/intel/braswell/tsc_freq.c M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_baytrail/include/soc/msr.h M src/soc/intel/fsp_baytrail/tsc_freq.c M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 19 files changed, 11 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/28853/1 diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index 7db870d..87f0525 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -27,7 +27,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 953fdca..135a3f8 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -28,7 +28,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 51a0deb..d1924cf 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -42,7 +42,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index 521e806..f26ac0f 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -29,7 +29,6 @@ #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_FERR_CAPABILITY 0x1f1 #define FERR_ENABLE (1 << 0) -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 9ab7466..606a65c 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -27,7 +27,6 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define IA32_MISC_ENABLE 0x1a0 #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c index 62c6316..c8b054c 100644 --- a/src/cpu/via/nano/nano_init.c +++ b/src/cpu/via/nano/nano_init.c @@ -28,8 +28,6 @@ #define MODEL_NANO_3000_B0 0x8 #define MODEL_NANO_3000_B2 0xa -#define MSR_IA32_PERF_STATUS 0x00000198 -#define MSR_IA32_PERF_CTL 0x00000199 #define MSR_IA32_MISC_ENABLE 0x000001a0 #define NANO_MYSTERIOUS_MSR 0x120e @@ -41,7 +39,7 @@ int cnt = 0; do { udelay(16); - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); cnt++; if (cnt > 128) { printk(BIOS_WARNING, @@ -61,7 +59,7 @@ { msr_t msr; /* Get voltage and frequency info */ - msr = rdmsr(MSR_IA32_PERF_STATUS); + msr = rdmsr(IA32_PERF_STATUS); u8 min_fid = (msr.hi >> 24); u8 max_fid = (msr.hi >> 8) & 0xff; u8 min_vid = (msr.hi >> 16) & 0xff; @@ -78,7 +76,7 @@ /* Set highest frequency and VID */ msr.lo = msr.hi; msr.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, msr); + wrmsr(IA32_PERF_CTL, msr); /* Wait for the transition to complete, otherwise, the CPU * might reset itself repeatedly */ nano_finish_fid_vid_transition(); diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 05a61bb..d8b73f2 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -35,8 +35,6 @@ /* Speedstep related MSRs */ -#define IA32_PERF_STATUS 0x198 -#define IA32_PERF_CTL 0x199 #define MSR_THERM2_CTL 0x19D #define IA32_MISC_ENABLES 0x1A0 #define MSR_EBC_FREQUENCY_ID 0x2c diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index f9d8f50..31449ed 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -22,6 +22,8 @@ #define CPUID_SMX (1 << 6) #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) +#define IA32_PERF_STATUS 0x198 +#define IA32_PERF_CTL 0x199 #define MSR_IA32_PAT 0x277 #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h index c207432b..fa0c40a 100644 --- a/src/soc/intel/baytrail/include/soc/msr.h +++ b/src/soc/intel/baytrail/include/soc/msr.h @@ -23,7 +23,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 66fde22..0aee1d7 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h index 1ed6d3a..207a27d 100644 --- a/src/soc/intel/braswell/include/soc/msr.h +++ b/src/soc/intel/braswell/include/soc/msr.h @@ -24,7 +24,6 @@ #define MSR_POWER_MISC 0x120 #define ENABLE_ULFM_AUTOCM_MASK (1 << 2) #define ENABLE_INDP_AUTOCM_MASK (1 << 3) -#define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c index b05a007..de82e23 100644 --- a/src/soc/intel/braswell/tsc_freq.c +++ b/src/soc/intel/braswell/tsc_freq.c @@ -91,7 +91,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* ENV_SMM */ diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 13cc6f2..f26ec66 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -34,7 +34,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 112a049..ebbdabd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -95,7 +95,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -115,7 +115,7 @@ perf_ctl.lo = (msr.lo & 0xff) << 8; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } @@ -135,7 +135,7 @@ perf_ctl.lo = msr.lo & 0xff00; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "CPU: frequency set to %d MHz\n", ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); } diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index 15aac62..13276a6 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -45,7 +45,6 @@ #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) #define FLEX_RATIO_EN (1 << 16) -#define MSR_IA32_PERF_CTL 0x199 #define IA32_MISC_ENABLE 0x1a0 /* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */ #define BURST_MODE_DISABLE (1 << 6) diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index c816ea4..8a07865 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -36,7 +36,6 @@ #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 -#define IA32_PERF_CTL 0x199 #define IA32_THERM_INTERRUPT 0x19b #define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0 #define ENERGY_POLICY_PERFORMANCE 0 diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h index c64810e..e6143ae 100644 --- a/src/soc/intel/fsp_baytrail/include/soc/msr.h +++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_POWER_MISC 0x120 -#define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 #define MSR_POWER_CTL 0x1fc #define MSR_PKG_POWER_SKU_UNIT 0x606 diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c index 66fde22..0aee1d7 100644 --- a/src/soc/intel/fsp_baytrail/tsc_freq.c +++ b/src/soc/intel/fsp_baytrail/tsc_freq.c @@ -74,7 +74,7 @@ perf_ctl.lo |= (msr.lo & 0x7f0000) >> 16; perf_ctl.hi = 0; - wrmsr(MSR_IA32_PERF_CTL, perf_ctl); + wrmsr(IA32_PERF_CTL, perf_ctl); } #endif /* __SMM__ */ diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index d81ed85..f240722 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce -#define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad #define IA32_MC0_CTL 0x400 #define IA32_MC0_STATUS 0x401 -- To view, visit https://review.coreboot.org/28853 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7f884379bcaec8340031c914107a7277d620f448 Gerrit-Change-Number: 28853 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Move IA32_{FEATURE_CONTROL, MCG_CAP} to x86/msr.h
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28852 Change subject: src: Move IA32_{FEATURE_CONTROL,MCG_CAP} to x86/msr.h ...................................................................... src: Move IA32_{FEATURE_CONTROL,MCG_CAP} to x86/msr.h Change-Id: I36a84896187558e16f6a960839c890a89ff2ac09 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common_init.c M src/cpu/intel/fsp_model_206ax/model_206ax.h M src/cpu/intel/fsp_model_406dx/model_406dx.h M src/cpu/intel/haswell/haswell.h M src/cpu/intel/haswell/haswell_init.c M src/cpu/intel/model_2065x/model_2065x.h M src/cpu/intel/model_206ax/model_206ax.h M src/cpu/intel/smm/gen1/smmrelocate.c M src/include/cpu/x86/msr.h M src/soc/intel/baytrail/romstage/cache_as_ram.inc M src/soc/intel/broadwell/include/soc/msr.h M src/soc/intel/common/block/include/intelblocks/msr.h M src/soc/intel/common/block/sgx/sgx.c M src/soc/intel/common/block/vmx/vmx.c M src/soc/intel/denverton_ns/include/soc/msr.h M src/soc/intel/fsp_broadwell_de/include/soc/msr.h 16 files changed, 15 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28852/1 diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 8dd8559..98b7f58 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -20,7 +20,6 @@ #include <cpu/x86/msr.h> #include "common.h" -#define IA32_FEATURE_CONTROL 0x3a #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h index e65b370..7db870d 100644 --- a/src/cpu/intel/fsp_model_206ax/model_206ax.h +++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h @@ -20,9 +20,6 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h index 87daeac..953fdca 100644 --- a/src/cpu/intel/fsp_model_406dx/model_406dx.h +++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h @@ -21,9 +21,6 @@ /* Rangeley bus clock is fixed at 100MHz */ #define RANGELEY_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h index 8498c1a..51a0deb 100644 --- a/src/cpu/intel/haswell/haswell.h +++ b/src/cpu/intel/haswell/haswell.h @@ -35,9 +35,6 @@ #define HASWELL_BCLK 100 #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 24de43e..5ea8535 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -661,11 +661,10 @@ static void configure_mca(void) { msr_t msr; - const unsigned int mcg_cap_msr = 0x179; int i; int num_banks; - msr = rdmsr(mcg_cap_msr); + msr = rdmsr(IA32_MCG_CAP); num_banks = msr.lo & 0xff; msr.lo = msr.hi = 0; /* TODO(adurbin): This should only be done on a cold boot. Also, some diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h index f87ba77..521e806 100644 --- a/src/cpu/intel/model_2065x/model_2065x.h +++ b/src/cpu/intel/model_2065x/model_2065x.h @@ -20,9 +20,6 @@ /* Nehalem bus clock is fixed at 133MHz */ #define NEHALEM_BCLK 133 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h index 98203b6..9ab7466 100644 --- a/src/cpu/intel/model_206ax/model_206ax.h +++ b/src/cpu/intel/model_206ax/model_206ax.h @@ -20,9 +20,6 @@ /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */ #define SANDYBRIDGE_BCLK 100 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_FEATURE_CONFIG 0x13c #define MSR_FLEX_RATIO 0x194 #define FLEX_RATIO_LOCK (1 << 20) @@ -39,7 +36,6 @@ #define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 #define MSR_LT_LOCK_MEMORY 0x2e7 #define IA32_MC0_STATUS 0x401 -#define IA32_MCG_CAP 0x179 #define MSR_PIC_MSG_CONTROL 0x2e #define MSR_PLATFORM_INFO 0xce diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c index a5a9de3..7391ac5 100644 --- a/src/cpu/intel/smm/gen1/smmrelocate.c +++ b/src/cpu/intel/smm/gen1/smmrelocate.c @@ -37,10 +37,6 @@ #define G_SMRAME (1 << 3) #define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK_BIT (1 << 0) -#define SMRR_ENABLE (1 << 3) - struct ied_header { char signature[10]; u32 size; diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index dcd23ee..f9d8f50 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -14,11 +14,20 @@ /* Page attribute type MSR */ #define IA32_PLATFORM_ID 0x17 +#define IA32_FEATURE_CONTROL 0x3a +#define FEATURE_CONTROL_LOCK_BIT (1 << 0) +#define FEATURE_ENABLE_VMX (1 << 2) +#define SMRR_ENABLE (1 << 3) +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define SGX_GLOBAL_ENABLE (1 << 18) +#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_IA32_PAT 0x277 #define IA32_BIOS_UPDT_TRIG 0x79 #define IA32_BIOS_SIGN_ID 0x8b #define MSR_IA32_MPERF 0xe7 #define MSR_IA32_APERF 0xe8 +#define IA32_MCG_CAP 0x179 #define MSR_IA32_PM_ENABLE 0x770 #define MSR_IA32_HWP_CAPABILITIES 0x771 #define MSR_IA32_HWP_REQUEST 0x774 diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index dcb6296..fea8686 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -35,7 +36,6 @@ #define NoEvictMod_MSR 0x2e0 #define BBL_CR_CTL3_MSR 0x11e -#define MCG_CAP_MSR 0x179 /* Save the BIST result. */ movl %eax, %ebp @@ -64,7 +64,7 @@ post_code(0x22) /* Zero the variable MTRRs. */ - movl $MCG_CAP_MSR, %ecx + movl $IA32_MCG_CAP, %ecx rdmsr movzx %al, %ebx /* First variable MTRR. */ diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h index 41ce17c..13cc6f2 100644 --- a/src/soc/intel/broadwell/include/soc/msr.h +++ b/src/soc/intel/broadwell/include/soc/msr.h @@ -18,9 +18,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h index e1fc431..15aac62 100644 --- a/src/soc/intel/common/block/include/intelblocks/msr.h +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -17,13 +17,6 @@ #define SOC_INTEL_COMMON_MSR_H #define MSR_CORE_THREAD_COUNT 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define FEATURE_CONTROL_LOCK (1) -#define FEATURE_ENABLE_VMX (1 << 2) -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) -#define SGX_GLOBAL_ENABLE (1 << 18) -#define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PLATFORM_INFO 0xce #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 /* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ @@ -46,7 +39,6 @@ #define MSR_FEATURE_CONFIG 0x13c #define FEATURE_CONFIG_RESERVED_MASK 0x3ULL #define FEATURE_CONFIG_LOCK (1 << 0) -#define IA32_MCG_CAP 0x179 #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57 #define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index daedcfc..6050dec 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -137,7 +137,7 @@ msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */ wrmsr(IA32_FEATURE_CONTROL, msr); } diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c index 591ffbc..2cffdab 100644 --- a/src/soc/intel/common/block/vmx/vmx.c +++ b/src/soc/intel/common/block/vmx/vmx.c @@ -58,7 +58,7 @@ msr = rdmsr(IA32_FEATURE_CONTROL); /* Only enable it when it is not locked */ - if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) { + if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) { /* Enable VMX */ msr.lo |= FEATURE_ENABLE_VMX; wrmsr(IA32_FEATURE_CONTROL, msr); @@ -68,5 +68,5 @@ msr = rdmsr(IA32_FEATURE_CONTROL); printk(BIOS_DEBUG, "VMX status: %s, %s\n", (msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled", - (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked"); + (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked"); } diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h index a49e225..c816ea4 100644 --- a/src/soc/intel/denverton_ns/include/soc/msr.h +++ b/src/soc/intel/denverton_ns/include/soc/msr.h @@ -20,9 +20,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define CORE_THREAD_COUNT_MSR 0x35 -#define IA32_FEATURE_CONTROL 0x3a -#define CPUID_VMX (1 << 5) -#define CPUID_SMX (1 << 6) #define MSR_PLATFORM_INFO 0xce #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h index af1db04..d81ed85 100644 --- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h +++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h @@ -20,7 +20,6 @@ #define MSR_CORE_THREAD_COUNT 0x35 #define MSR_PLATFORM_INFO 0xce -#define IA32_MCG_CAP 0x179 #define IA32_PERF_CTL 0x199 #define MSR_TURBO_RATIO_LIMIT 0x1ad #define IA32_MC0_CTL 0x400 -- To view, visit https://review.coreboot.org/28852 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I36a84896187558e16f6a960839c890a89ff2ac09 Gerrit-Change-Number: 28852 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse
by Elyes HAOUAS (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), Lijian Zhao, Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28847 to look at the new patch set (#3). Change subject: src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse ...................................................................... src/soc/intel/cannonlake: Fix IA32_PLATFORM_DCA_CAP addresse Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/cannonlake/include/soc/msr.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/28847/3 -- To view, visit https://review.coreboot.org/28847 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id4f99e82bb97a260d654b49a2ba94fde207d318b Gerrit-Change-Number: 28847 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: commonlib/region: Add region protect API
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: Add region protect API ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… PS2, Line 67: * Write protect the region indicated by region device. > copy paste error ? Done https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/1/src/commonlib/include/commonlib/reg… PS1, Line 67: Write protect the region indicated by region device. > use enum cb_err with CB_SUCCESS and CB_ERR. Was keeping it in-line with rest of the APIs in this file. https://review.coreboot.org/#/c/28724/2/src/commonlib/region.c File src/commonlib/region.c: https://review.coreboot.org/#/c/28724/2/src/commonlib/region.c@154 PS2, Line 154: /* Write protect the region indicated by region device */ > please mention in a comment that it'll make the flash write protected Done -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Oct 2018 11:34:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/region: Add region protect API
by build bot (Jenkins) (Code Review) 01 Oct '18

01 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: Add region protect API ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28724/3/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/3/src/commonlib/include/commonlib/reg… PS3, Line 97: int (*protect)(const struct region *); function definition argument 'const struct region *' should also have an identifier name -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Oct 2018 11:34:54 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/region: Add region protect API
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28724 to look at the new patch set (#3). Change subject: commonlib/region: Add region protect API ...................................................................... commonlib/region: Add region protect API Add "protect" operation to the region_device_ops. This can be used for write protecting the region that is represented by the device. Also add an API redev_protect() which will expose the protect operation to the library user. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c 2 files changed, 24 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28724/3 -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: drivers/spi: Implement write protect operation
by Patrick Rudolph (Code Review) 01 Oct '18

01 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28725 ) Change subject: drivers/spi: Implement write protect operation ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/28725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I87cef73852ea671ec80741af78844d32c0ed5d3c Gerrit-Change-Number: 28725 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 09:55:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: commonlib/region: Add region protect API
by Patrick Rudolph (Code Review) 01 Oct '18

01 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: Add region protect API ...................................................................... Patch Set 2: Code-Review+1 (2 comments) https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… PS2, Line 67: * Returns < 0 on error otherwise returns 0 on success, < 0 0n error. copy paste error ? https://review.coreboot.org/#/c/28724/2/src/commonlib/region.c File src/commonlib/region.c: https://review.coreboot.org/#/c/28724/2/src/commonlib/region.c@154 PS2, Line 154: int rdev_protect(const struct region_device *rd) please mention in a comment that it'll make the flash write protected -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Oct 2018 09:55:41 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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