coreboot-gerrit October 2018

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Change in coreboot[master]: util/autoport: Use romstage.c instead of early_southbridge.c
by Patrick Rudolph (Code Review) 01 Oct '18

01 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28851 ) Change subject: util/autoport: Use romstage.c instead of early_southbridge.c ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/28851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If9f9375f9a659e7e685de5f884163813261fa656 Gerrit-Change-Number: 28851 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 09:52:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: util/autoport: Use romstage.c instead of early_southbridge.c
by Angel Pons (Code Review) 01 Oct '18

01 Oct '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28851 Change subject: util/autoport: Use romstage.c instead of early_southbridge.c ...................................................................... util/autoport: Use romstage.c instead of early_southbridge.c Until now, autoport used to create a dummy "romstage.c", then write romstage code to "early_southbridge.c". While it works, it makes more sense to write to "romstage.c" instead, as virtually all mainboards do. Change-Id: If9f9375f9a659e7e685de5f884163813261fa656 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/autoport/bd82x6x.go M util/autoport/main.go 2 files changed, 1 insertion(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/28851/1 diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index 31f7ced..887a520 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -299,9 +299,8 @@ File: "southbridge/intel/bd82x6x/acpi/pch.asl", }) - sb := Create(ctx, "early_southbridge.c") + sb := Create(ctx, "romstage.c") defer sb.Close() - AddROMStageFile("early_southbridge.c", "") Add_gpl(sb) sb.WriteString(`#include <stdint.h> #include <string.h> diff --git a/util/autoport/main.go b/util/autoport/main.go index 3071559..ed56a55 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -827,10 +827,6 @@ fmt.Fprintf(bi, "FIXME: put %s\n", missing) } - rs := Create(ctx, "romstage.c") - defer rs.Close() - rs.WriteString("/* dummy file */\n") - if ROMSizeKB == 0 { KconfigBool["BOARD_ROMSIZE_KB_2048"] = true KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this" -- To view, visit https://review.coreboot.org/28851 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If9f9375f9a659e7e685de5f884163813261fa656 Gerrit-Change-Number: 28851 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: commonlib/region: Add region protect API
by build bot (Jenkins) (Code Review) 01 Oct '18

01 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28724 ) Change subject: commonlib/region: Add region protect API ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… File src/commonlib/include/commonlib/region.h: https://review.coreboot.org/#/c/28724/2/src/commonlib/include/commonlib/reg… PS2, Line 96: int (*protect)(const struct region *); function definition argument 'const struct region *' should also have an identifier name -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Mon, 01 Oct 2018 09:30:46 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: commonlib/region: Add region protect API
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28724 to look at the new patch set (#2). Change subject: commonlib/region: Add region protect API ...................................................................... commonlib/region: Add region protect API Add "protect" operation to the region_device_ops. This can be used for write protecting the region that is represented by the device. Also add an API redev_protect() which will expose the protect operation to the library user. Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/commonlib/include/commonlib/region.h M src/commonlib/region.c 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/28724/2 -- To view, visit https://review.coreboot.org/28724 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a Gerrit-Change-Number: 28724 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: drivers/spi: Implement write protect operation
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28725 to look at the new patch set (#2). Change subject: drivers/spi: Implement write protect operation ...................................................................... drivers/spi: Implement write protect operation Implement a write protect operation which can be used as part of a region_device_ops. This operation will protect the region using the SPI FPR. Change-Id: I87cef73852ea671ec80741af78844d32c0ed5d3c Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/drivers/spi/boot_device_rw_nommap.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/28725/2 -- To view, visit https://review.coreboot.org/28725 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I87cef73852ea671ec80741af78844d32c0ed5d3c Gerrit-Change-Number: 28725 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/intel/cannonlake_rvp: Remove empty romstage.c
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28850 Change subject: mb/intel/cannonlake_rvp: Remove empty romstage.c ...................................................................... mb/intel/cannonlake_rvp: Remove empty romstage.c Remove empty file, romstage.c Change-Id: I5382e0c260dfc26377ecbe86e9d797ea5e0cad0e Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- D src/mainboard/intel/cannonlake_rvp/romstage.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/28850/1 diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c deleted file mode 100644 index cb775e0..0000000 --- a/src/mainboard/intel/cannonlake_rvp/romstage.c +++ /dev/null @@ -1 +0,0 @@ -/* This file is required by src/arch/x86/Makefile.inc */ -- To view, visit https://review.coreboot.org/28850 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5382e0c260dfc26377ecbe86e9d797ea5e0cad0e Gerrit-Change-Number: 28850 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: arch/x86: Make mb/romstage.c optional
by Rizwan Qureshi (Code Review) 01 Oct '18

01 Oct '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/28849 Change subject: arch/x86: Make mb/romstage.c optional ...................................................................... arch/x86: Make mb/romstage.c optional currently src/mainboard/*/romstage.c is mandatory for compiling, this makes having the file present even though there is nothing to initialize in the romstage on the mainboard side. for e.g., mainboard/intel/cannonlake_rvp/romstage.c Eliminate the need to have empty romstage.c files using the wildcard function. BUG=None BRANCH=None TEST= build cannonlake_rvp after removing the romstage.c file. Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/arch/x86/Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/28849/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 3e272dd..7f85b6a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -224,7 +224,7 @@ romstage-y += postcar_loader.c romstage-$(CONFIG_COLLECT_TIMESTAMPS_TSC) += timestamp.c -romstage-srcs += $(src)/mainboard/$(MAINBOARDDIR)/romstage.c +romstage-srcs += $(wildcard $(src)/mainboard/$(MAINBOARDDIR)/romstage.c) romstage-libs ?= $(eval $(call early_x86_assembly_entry_rule,romstage)) -- To view, visit https://review.coreboot.org/28849 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id6335a473d413d1aa89389d3a3d174ed4a1bda90 Gerrit-Change-Number: 28849 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Move the FSP related callbacks to separate files
by build bot (Jenkins) (Code Review) 01 Oct '18

01 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28661 ) Change subject: soc/intel/cannonlake: Move the FSP related callbacks to separate files ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/28661/5/src/soc/intel/cannonlake/fsp_params… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/#/c/28661/5/src/soc/intel/cannonlake/fsp_params… PS5, Line 82: for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28661/5/src/soc/intel/cannonlake/fsp_params… PS5, Line 86: for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/28661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Gerrit-Change-Number: 28661 Gerrit-PatchSet: 5 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 08:28:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Move the FSP related callbacks to separate files
by build bot (Jenkins) (Code Review) 01 Oct '18

01 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28661 ) Change subject: soc/intel/cannonlake: Move the FSP related callbacks to separate files ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/#/c/28661/4/src/soc/intel/cannonlake/fsp_params… File src/soc/intel/cannonlake/fsp_params.c: https://review.coreboot.org/#/c/28661/4/src/soc/intel/cannonlake/fsp_params… PS4, Line 82: for (i = 0; i < ARRAY_SIZE(params->Usb2OverCurrentPin); i++) { braces {} are not necessary for single statement blocks https://review.coreboot.org/#/c/28661/4/src/soc/intel/cannonlake/fsp_params… PS4, Line 86: for (i = 0; i < ARRAY_SIZE(params->Usb3OverCurrentPin); i++) { braces {} are not necessary for single statement blocks -- To view, visit https://review.coreboot.org/28661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e Gerrit-Change-Number: 28661 Gerrit-PatchSet: 4 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 01 Oct 2018 08:10:04 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/broadwell/me.c: Correct HMRFPO misspelling
by Angel Pons (Code Review) 01 Oct '18

01 Oct '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28848 Change subject: src/soc/intel/broadwell/me.c: Correct HMRFPO misspelling ...................................................................... src/soc/intel/broadwell/me.c: Correct HMRFPO misspelling `HMRFPO` was spelled as `HMRPFO` twice. Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/me.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/28848/1 diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index ae0f48f..f8b3be9 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -589,7 +589,7 @@ return -1; } - printk(BIOS_INFO, "ME: HMRPFO LOCK message successful (%d)\n", ack); + printk(BIOS_INFO, "ME: HMRFPO LOCK message successful (%d)\n", ack); return 0; } @@ -607,7 +607,7 @@ return -1; } - printk(BIOS_INFO, "ME: HMRPFO LOCK NOACK message successful\n"); + printk(BIOS_INFO, "ME: HMRFPO LOCK NOACK message successful\n"); return 0; } -- To view, visit https://review.coreboot.org/28848 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibd04004ac5edcdeee49a6a69fcdd5c73603e92e2 Gerrit-Change-Number: 28848 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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coreboot-gerrit October 2018