coreboot-gerrit October 2018

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Change in coreboot[master]: mb/google/kahlee: Add delan variant
by Raul Rangel (Code Review) 10 Oct '18

10 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/28972 ) Change subject: mb/google/kahlee: Add delan variant ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Gerrit-Change-Number: 28972 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 15:51:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD
by Martin Roth (Code Review) 09 Oct '18

09 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28974 ) Change subject: mb/google/poppy/variants/nami: Add samsung_dimm_K4AAG165WB-MCRC SPD ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/28974 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb Gerrit-Change-Number: 28974 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 14:33:57 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/cavium: dynamic UART initialization for cavium cn8100
by Patrick Rudolph (Code Review) 09 Oct '18

09 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28975 ) Change subject: soc/cavium: dynamic UART initialization for cavium cn8100 ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/28975/3//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/28975/3//COMMIT_MSG@9 PS3, Line 9: Now only those UARTs that are enabled in devicetree.cbare initialized. missing space https://review.coreboot.org/#/c/28975/3//COMMIT_MSG@11 PS3, Line 11: Tested on Opencellular Elgon missing . https://review.coreboot.org/#/c/28975/3/src/soc/cavium/cn81xx/soc.c File src/soc/cavium/cn81xx/soc.c: https://review.coreboot.org/#/c/28975/3/src/soc/cavium/cn81xx/soc.c@398 PS3, Line 398: /*using device enable state from devicetree.cb*/ missing space 2x -- To view, visit https://review.coreboot.org/28975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Gerrit-Change-Number: 28975 Gerrit-PatchSet: 3 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 14:14:27 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: WIP: riscv: drop .data/.bss from bootblock
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28977 ) Change subject: WIP: riscv: drop .data/.bss from bootblock ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28977/2/src/arch/riscv/misaligned.c File src/arch/riscv/misaligned.c: https://review.coreboot.org/#/c/28977/2/src/arch/riscv/misaligned.c@139 PS2, Line 139: static const struct memory_instruction_info *match_instruction(const uintptr_t insn) line over 80 characters -- To view, visit https://review.coreboot.org/28977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Gerrit-Change-Number: 28977 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Xiang Wang <wxjstz(a)126.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 13:30:42 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: dynamic UART initialization for cavium cn8100
by Jens Drenhaus (Code Review) 09 Oct '18

09 Oct '18

Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28975 to look at the new patch set (#3). Change subject: soc/cavium: dynamic UART initialization for cavium cn8100 ...................................................................... soc/cavium: dynamic UART initialization for cavium cn8100 Now only those UARTs that are enabled in devicetree.cbare initialized. Tested on Opencellular Elgon Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/opencellular/elgon/mainboard.c M src/soc/cavium/cn81xx/soc.c 3 files changed, 28 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28975/3 -- To view, visit https://review.coreboot.org/28975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Gerrit-Change-Number: 28975 Gerrit-PatchSet: 3 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: WIP: riscv: drop .data/.bss from bootblock
by Jonathan Neuschäfer (Code Review) 09 Oct '18

09 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/28977 ) Change subject: WIP: riscv: drop .data/.bss from bootblock ...................................................................... Patch Set 1: I kind of like this idea, but console_inited, for example, is in common code, so other architectures don't seem to do this -- To view, visit https://review.coreboot.org/28977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Gerrit-Change-Number: 28977 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 13:18:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/cavium: dynamic UART initialization for cavium cn8100
by Jens Drenhaus (Code Review) 09 Oct '18

09 Oct '18

Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/28975 to look at the new patch set (#2). Change subject: soc/cavium: dynamic UART initialization for cavium cn8100 ...................................................................... soc/cavium: dynamic UART initialization for cavium cn8100 Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Signed-off-by: Jens Drenhaus <jens.drenhaus(a)9elements.com> --- M src/mainboard/cavium/cn8100_sff_evb/mainboard.c M src/mainboard/opencellular/elgon/mainboard.c M src/soc/cavium/cn81xx/soc.c 3 files changed, 28 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28975/2 -- To view, visit https://review.coreboot.org/28975 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62 Gerrit-Change-Number: 28975 Gerrit-PatchSet: 2 Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Jens Drenhaus <jens.drenhaus(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: WIP: riscv: drop .data/.bss from bootblock
by Philipp Hug (Code Review) 09 Oct '18

09 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/28977 ) Change subject: WIP: riscv: drop .data/.bss from bootblock ...................................................................... Patch Set 1: What do you think about this idea? Do you know how to make the linker complain about remaining data? I left a few in to test: 2 .sbss.timecmp 00000008 0000000008002398 0000000008002398 00002409 2**3 ALLOC 3 .sbss.console_inited 00000004 00000000080023a0 00000000080023a0 00002409 2**2 ALLOC 4 .sbss.cbmem_console_p 00000008 00000000080023a8 00000000080023a8 00002409 2**3 ALLOC -- To view, visit https://review.coreboot.org/28977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Gerrit-Change-Number: 28977 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 13:06:14 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: WIP: riscv: drop .data/.bss from bootblock
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28977 ) Change subject: WIP: riscv: drop .data/.bss from bootblock ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28977/1/src/arch/riscv/misaligned.c File src/arch/riscv/misaligned.c: https://review.coreboot.org/#/c/28977/1/src/arch/riscv/misaligned.c@139 PS1, Line 139: static const struct memory_instruction_info *match_instruction(const uintptr_t insn) line over 80 characters -- To view, visit https://review.coreboot.org/28977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Gerrit-Change-Number: 28977 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 09 Oct 2018 13:03:11 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: WIP: riscv: drop .data/.bss from bootblock
by Philipp Hug (Code Review) 09 Oct '18

09 Oct '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/28977 Change subject: WIP: riscv: drop .data/.bss from bootblock ...................................................................... WIP: riscv: drop .data/.bss from bootblock bootblock on RISC-V doesn't need a data and bss segment. This makes it easier to execute the bootblock directly from boot media. TODO: How can me make the linker complain if data segment is still present? Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/include/arch/memlayout.h M src/arch/riscv/misaligned.c M src/soc/sifive/fu540/media.c 3 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/28977/1 diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 7baab76..99e96e0 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -18,6 +18,14 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H +#if ENV_BOOTBLOCK +/* + * No .data or .bss sections in the bootblock + */ +#define ARCH_STAGE_HAS_DATA_SECTION 0 +#define ARCH_STAGE_HAS_BSS_SECTION 0 +#endif + #define STACK(addr, size) REGION(stack, addr, size, 4096) #if defined(__PRE_RAM__) diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ba96102..a91c4dd 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -57,7 +57,7 @@ unsigned int sign_extend : 1; /* mark need to be sign extended */ }; -static struct memory_instruction_info insn_info[] = { +static const struct memory_instruction_info insn_info[] = { #if __riscv_xlen == 128 { 0x00002000, 0x0000e003, 2, 7, 8, 0, 1, 16, 1}, // C.LQ #else @@ -136,7 +136,7 @@ #endif // defined(__riscv_flen) }; -static struct memory_instruction_info *match_instruction(uintptr_t insn) +static const struct memory_instruction_info *match_instruction(const uintptr_t insn) { int i; for (i = 0; i < ARRAY_SIZE(insn_info); i++) @@ -187,7 +187,7 @@ } /* matching instruction */ - struct memory_instruction_info *match = match_instruction(insn); + const struct memory_instruction_info *match = match_instruction(insn); if (!match) { redirect_trap(); diff --git a/src/soc/sifive/fu540/media.c b/src/soc/sifive/fu540/media.c index 7b9ccb0..754f956 100644 --- a/src/soc/sifive/fu540/media.c +++ b/src/soc/sifive/fu540/media.c @@ -16,7 +16,7 @@ #include <boot_device.h> /* At 0x20000000: A 256MiB long memory-mapped view of the flash at QSPI0 */ -static struct mem_region_device mdev = +static const struct mem_region_device mdev = MEM_REGION_DEV_RO_INIT((void *)0x20000000, CONFIG_ROM_SIZE); const struct region_device *boot_device_ro(void) -- To view, visit https://review.coreboot.org/28977 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I61f9610ed11379e42b6696beffef6e4ca2e72dbd Gerrit-Change-Number: 28977 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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coreboot-gerrit October 2018