coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Add back PM TIMER EMULATION
by Boon Tiong Teo (Code Review) 09 Oct '18

09 Oct '18

Boon Tiong Teo has posted comments on this change. ( https://review.coreboot.org/28937 ) Change subject: soc/intel/cannonlake: Add back PM TIMER EMULATION ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/cpu.c File src/soc/intel/cannonlake/cpu.c: https://review.coreboot.org/#/c/28937/2/src/soc/intel/cannonlake/cpu.c@170 PS2, Line 170: * The emulated ACPI timer allows disabling of the ACPI timer "disabling"? Isn't miss leading? -- To view, visit https://review.coreboot.org/28937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd Gerrit-Change-Number: 28937 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Boon Tiong Teo <boon.tiong.teo(a)intel.com> Gerrit-CC: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-CC: Lean Sheng Tan <lean.sheng.tan(a)intel.com> Gerrit-CC: Subrata Banik <subi.banik(a)gmail.com> Gerrit-Comment-Date: Tue, 09 Oct 2018 03:09:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: Add delan variant
by Martin Roth (Code Review) 09 Oct '18

09 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/28972 Change subject: mb/google/kahlee: Add delan variant ...................................................................... mb/google/kahlee: Add delan variant BUG=b:117173908 TEST=Build delan Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/Kconfig M src/mainboard/google/kahlee/Kconfig.name A src/mainboard/google/kahlee/variants/delan/Makefile.inc A src/mainboard/google/kahlee/variants/delan/devicetree.cb A src/mainboard/google/kahlee/variants/delan/include/variant/acpi/gpe.asl A src/mainboard/google/kahlee/variants/delan/include/variant/acpi/mainboard.asl A src/mainboard/google/kahlee/variants/delan/include/variant/acpi/routing.asl A src/mainboard/google/kahlee/variants/delan/include/variant/acpi/sleep.asl A src/mainboard/google/kahlee/variants/delan/include/variant/acpi/thermal.asl A src/mainboard/google/kahlee/variants/delan/include/variant/ec.h A src/mainboard/google/kahlee/variants/delan/include/variant/gpio.h A src/mainboard/google/kahlee/variants/delan/include/variant/thermal.h 12 files changed, 341 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/28972/1 diff --git a/src/mainboard/google/kahlee/Kconfig b/src/mainboard/google/kahlee/Kconfig index ce6227c..a8592b2 100644 --- a/src/mainboard/google/kahlee/Kconfig +++ b/src/mainboard/google/kahlee/Kconfig @@ -60,6 +60,7 @@ string default "aleena" if BOARD_GOOGLE_ALEENA default "careena" if BOARD_GOOGLE_CAREENA + default "delan" if BOARD_GOOGLE_DELAN default "grunt" if BOARD_GOOGLE_GRUNT default "liara" if BOARD_GOOGLE_LIARA @@ -113,6 +114,7 @@ depends on CHROMEOS default "ALEENA TEST 7281" if BOARD_GOOGLE_ALEENA default "CAREENA TEST 8777" if BOARD_GOOGLE_CAREENA + default "DELAN TEST 0359" if BOARD_GOOGLE_DELAN default "GRUNT TEST 8296" if BOARD_GOOGLE_GRUNT default "LIARA TEST 0464" if BOARD_GOOGLE_LIARA diff --git a/src/mainboard/google/kahlee/Kconfig.name b/src/mainboard/google/kahlee/Kconfig.name index c9401be..941390f 100644 --- a/src/mainboard/google/kahlee/Kconfig.name +++ b/src/mainboard/google/kahlee/Kconfig.name @@ -6,6 +6,9 @@ config BOARD_GOOGLE_CAREENA bool "-> Careena" select BOARD_GOOGLE_BASEBOARD_KAHLEE +config BOARD_GOOGLE_DELAN + bool "-> Delan" + select BOARD_GOOGLE_BASEBOARD_KAHLEE config BOARD_GOOGLE_GRUNT bool "-> Grunt" select BOARD_GOOGLE_BASEBOARD_KAHLEE diff --git a/src/mainboard/google/kahlee/variants/delan/Makefile.inc b/src/mainboard/google/kahlee/variants/delan/Makefile.inc new file mode 100644 index 0000000..0579e18 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/Makefile.inc @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2017 Google, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +subdirs-y += ../baseboard/spd + +romstage-y += ../baseboard/romstage.c + +ramstage-y += ../baseboard/mainboard.c diff --git a/src/mainboard/google/kahlee/variants/delan/devicetree.cb b/src/mainboard/google/kahlee/variants/delan/devicetree.cb new file mode 100644 index 0000000..0dfe204 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/devicetree.cb @@ -0,0 +1,174 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip soc/amd/stoneyridge + register "spd_addr_lookup" = " + { + { {0xA0, 0x00} }, // socket 0 - Channel 0, slot 0 + }" + register "dram_clear_on_reset" = "DRAM_CONTENTS_KEEP" + register "uma_mode" = "UMAMODE_SPECIFIED_SIZE" + register "uma_size" = "32 * MiB" + + # Enable I2C0 for audio, USB3 hub at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 85, + .fall_time_ns = 3, + }" + + # Enable I2C1 for H1 at 400kHz + register "i2c[1]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C2 for trackpad, pen at 400kHz + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 3, + .fall_time_ns = 2, + }" + + # Enable I2C3 for touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 16, + .fall_time_ns = 8, + }" + + device cpu_cluster 0 on + device lapic 10 on end + end + device domain 0 on + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # + device pci 2.2 on end # + device pci 2.3 on end # + device pci 2.4 on + chip drivers/generic/bayhub + register "power_saving" = "1" + device pci 00.0 on end + end + end # + device pci 2.5 on end # + device pci 8.0 on end # PSP + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 off end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SMbus + end # SMbus + device pci 14.3 on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #domain + device mmio 0xfedc2000 on + chip drivers/generic/adau7002 + device generic 0.0 on end + end + chip drivers/i2c/da7219 + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_14)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + register "mclk_name" = ""oscout1"" + device i2c 1a on end + end + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_119)" + register "sdmode_delay" = "5" + device generic 0.1 on end + end + end + device mmio 0xfedc3000 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "desc" = ""Cr50 TPM"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPIO_9)" + device i2c 50 on end + end + end + device mmio 0xfedc4000 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "wake" = "7" + register "probed" = "1" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""PNP0C50"" + register "generic.desc" = ""Synaptics Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_5)" + register "generic.wake" = "7" + register "generic.probed" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 2c on end + end + end + device mmio 0xfedc5000 on + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 39 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "probed" = "1" + register "irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPIO_11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_85)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/gpe.asl b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/gpe.asl new file mode 100644 index 0000000..05cd0b9 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/gpe.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/gpe.asl> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/mainboard.asl b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000..d026e9a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/mainboard.asl> +#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/routing.asl b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/routing.asl new file mode 100644 index 0000000..c1896c3 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/routing.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/routing.asl> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/sleep.asl b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/sleep.asl new file mode 100644 index 0000000..a401b3a --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/sleep.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/sleep.asl> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/thermal.asl b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/thermal.asl new file mode 100644 index 0000000..a7e511c --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/acpi/thermal.asl @@ -0,0 +1,14 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/acpi/thermal.asl> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/ec.h b/src/mainboard/google/kahlee/variants/delan/include/variant/ec.h new file mode 100644 index 0000000..e90724e --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/ec.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/ec.h> + +/* Enable EC backed Keyboard Backlight in ACPI */ +#define EC_ENABLE_KEYBOARD_BACKLIGHT diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/gpio.h b/src/mainboard/google/kahlee/variants/delan/include/variant/gpio.h new file mode 100644 index 0000000..5a6b540 --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/gpio.h @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/gpio.h> diff --git a/src/mainboard/google/kahlee/variants/delan/include/variant/thermal.h b/src/mainboard/google/kahlee/variants/delan/include/variant/thermal.h new file mode 100644 index 0000000..1bb78ef --- /dev/null +++ b/src/mainboard/google/kahlee/variants/delan/include/variant/thermal.h @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* + * Stoney Ridge Thermal Requirements 12 (6W) + * TDP (W) 6 + * T die,max (°C) 95 + * T ctl,max 85 + * T die,lmt (default) 90 + * T ctl,lmt (default) 80 + */ + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 2 /* EC TIN2 */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 94 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 85 + +#endif -- To view, visit https://review.coreboot.org/28972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953 Gerrit-Change-Number: 28972 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: src/superio/smsc/smscsuperio/superio.c: Add SCH5504
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28971 ) Change subject: src/superio/smsc/smscsuperio/superio.c: Add SCH5504 ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/28971/1/src/superio/smsc/smscsuperio/superi… File src/superio/smsc/smscsuperio/superio.c: https://review.coreboot.org/#/c/28971/1/src/superio/smsc/smscsuperio/superi… PS1, Line 135: {SCH5504, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, space required after that close brace '}' -- To view, visit https://review.coreboot.org/28971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6c433fa04c01ba6315bcdca699030dfce18a169a Gerrit-Change-Number: 28971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 19:46:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/superio/smsc/smscsuperio/superio.c: Add SCH5504
by Angel Pons (Code Review) 09 Oct '18

09 Oct '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28971 Change subject: src/superio/smsc/smscsuperio/superio.c: Add SCH5504 ...................................................................... src/superio/smsc/smscsuperio/superio.c: Add SCH5504 Based on previous reverse-engineering done on "util/superiotool". TEST=NOT TESTED (yet) Change-Id: I6c433fa04c01ba6315bcdca699030dfce18a169a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/superio/smsc/smscsuperio/superio.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/28971/1 diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index 6380f88..0beb910 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -53,6 +53,7 @@ #define LPC47B397 0x6f #define A8000 0x77 /* ASUS A8000, a rebranded DME1737(?) */ #define DME1737 0x78 +#define SCH5504 0x79 #define SCH3112 0x7c #define SCH3114 0x7d #define SCH5307 0x81 /* Rebranded LPC47B397(?) */ @@ -131,6 +132,7 @@ {LPC47U33X,{0, 3, 4, -1, -1, 7, -1, -1, -1, 9, 0, 5, 10, 0, 11}}, {A8000, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {DME1737, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, + {SCH5504, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3112, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH3114, {0, 3, 4, 5, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}}, {SCH5307, {0, 3, 4, 5, -1, 7, -1, -1, 8, -1, -1, -1, 10, -1, -1}}, -- To view, visit https://review.coreboot.org/28971 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6c433fa04c01ba6315bcdca699030dfce18a169a Gerrit-Change-Number: 28971 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: check for NULL using if statement
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28940 ) Change subject: soc/intel/common/block/gpio: check for NULL using if statement ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/28940/3/src/soc/intel/common/block/gpio/gpi… File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/#/c/28940/3/src/soc/intel/common/block/gpio/gpi… PS3, Line 77: die("gpio_group_index: Failed to get comm->groups."); Prefer using '"%s...", __func__' to using 'gpio_group_index', this function's name, in a string -- To view, visit https://review.coreboot.org/28940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb Gerrit-Change-Number: 28940 Gerrit-PatchSet: 3 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:59:33 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: [WIP] add i945G based mainboard
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/25509 ) Change subject: [WIP] add i945G based mainboard ...................................................................... Patch Set 23: (17 comments) https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… File src/mainboard/nec/945g-m4/romstage.c: https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 140: [ 16.101663] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x2 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 141: [ 16.101785] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x2 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 142: [ 16.101859] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 143: [ 16.101974] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 144: [ 16.102086] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x36 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 145: [ 16.102156] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x38 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 146: [ 16.102250] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x38 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 147: [ 16.103089] snd_intel8x0 0000:00:1e.2: codec_write 0: semaphore is not ready for register 0x10 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/romstage… PS23, Line 151: [ 11.645291] snd_intel8x0m: probe of 0000:00:1e.3 failed with error -13 line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… File src/mainboard/nec/945g-m4/superio_hwm.c: https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 83: //if (get_option(&cpufan_temperature, "cpufan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 90: //if (get_option(&sysfan_temperature, "sysfan_temperature") != CB_SUCCESS) line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 135: hwm_write(0x06, fan_speeds[cpufan_speed].fan_in); // CPUFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 140: temperatures[cpufan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 141: hwm_write(0x06, temperatures[cpufan_temperature].deg_celsius); // CPUFANIN target temperature line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 149: hwm_write(0x05, fan_speeds[sysfan_speed].fan_in); // SYSFANIN target speed line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 154: temperatures[sysfan_temperature].deg_fahrenheit); line over 80 characters https://review.coreboot.org/#/c/25509/23/src/mainboard/nec/945g-m4/superio_… PS23, Line 155: hwm_write(0x05, temperatures[sysfan_temperature].deg_celsius); // SYSFANIN target temperature line over 80 characters -- To view, visit https://review.coreboot.org/25509 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5398b990c26d087afb20e4b1028a7a1cad4b3ee3 Gerrit-Change-Number: 25509 Gerrit-PatchSet: 23 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:59:26 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/27590 ) Change subject: nb/i945: Fix sdram_rcomp_buffer_strength_and_slew for i945gc ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/27590/5/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/27590/5/src/northbridge/intel/i945/raminit.… PS5, Line 1048: int offset = IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM) ? 1 : 0; line over 80 characters -- To view, visit https://review.coreboot.org/27590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iff1705788fdffeacd94fe5e50507733ff7c0f96b Gerrit-Change-Number: 27590 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:59:14 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: cpu/intel/speedstep/acpi.c: Add Netburst CPUs
by build bot (Jenkins) (Code Review) 09 Oct '18

09 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22604 ) Change subject: cpu/intel/speedstep/acpi.c: Add Netburst CPUs ...................................................................... Patch Set 21: (6 comments) https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/acpi.c File src/cpu/intel/speedstep/acpi.c: https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/acpi.c@92 PS21, Line 92: else else is not generally useful after a break or return https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.c File src/cpu/intel/speedstep/speedstep.c: https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.… PS21, Line 45: if (((rdmsr(MSR_EXTENDED_CONFIG).lo >> 27) & 3) == 3) {/*supported and line over 80 characters https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.… PS21, Line 46: enabled bits */ line over 80 characters https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.… PS21, Line 48: params->slfm = SPEEDSTEP_STATE_FROM_MSR(msr.lo, state_mask); line over 80 characters https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.… PS21, Line 77: !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) { line over 80 characters https://review.coreboot.org/#/c/22604/21/src/cpu/intel/speedstep/speedstep.… PS21, Line 79: params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask); line over 80 characters -- To view, visit https://review.coreboot.org/22604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I06e162d3260dedeb3b16583460633507fbcbd52a Gerrit-Change-Number: 22604 Gerrit-PatchSet: 21 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:58:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/superiotool/smsc.c: Add SCH5504 register dump
by Angel Pons (Code Review) 09 Oct '18

09 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/28958 ) Change subject: util/superiotool/smsc.c: Add SCH5504 register dump ...................................................................... Patch Set 2: > Patch Set 1: Code-Review+2 > > might need to be rebased on your other patch that i merged today Looks like it's good to go :) -- To view, visit https://review.coreboot.org/28958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89 Gerrit-Change-Number: 28958 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:42:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/superiotool/smsc.c: Add SCH5504 register dump
by Felix Held (Code Review) 09 Oct '18

09 Oct '18

Felix Held has posted comments on this change. ( https://review.coreboot.org/28958 ) Change subject: util/superiotool/smsc.c: Add SCH5504 register dump ...................................................................... Patch Set 1: Code-Review+2 might need to be rebased on your other patch that i merged today -- To view, visit https://review.coreboot.org/28958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89 Gerrit-Change-Number: 28958 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 18:39:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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