coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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1285 discussions

Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Elyes HAOUAS (Code Review) 08 Oct '18

08 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: (2 comments) this is not a real issue ... as it will write to nothing when external GPU is used. https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.… PS1, Line 2306: : : : > But it shows us what to do if. if "integrated_graphics" is disabled ? https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.… PS1, Line 2764: pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & : (DEVEN_D2F0 | DEVEN_D2F1) > Always true? what I'm trying to explain is : when the chip is not i945GM but a i945G + an external GPU, IGD is disabled. so write to it do not make sense -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Oct 2018 10:11:20 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/google/kahlee: Set PSPP setting to BalancedHigh
by Kevin Chiu (Code Review) 08 Oct '18

08 Oct '18

Kevin Chiu has posted comments on this change. ( https://review.coreboot.org/28967 ) Change subject: mainboard/google/kahlee: Set PSPP setting to BalancedHigh ...................................................................... Patch Set 1: Hi Akshu, as I query on the tracker, we still don't know what the root cause it is. How PSPP impacts audio function? thanks. -- To view, visit https://review.coreboot.org/28967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee Gerrit-Change-Number: 28967 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Akshu Agrawal <akshu.agrawal(a)amd.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Comment-Date: Mon, 08 Oct 2018 10:01:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: correct wifi wake register
by Patrick Georgi (Code Review) 08 Oct '18

08 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28938 ) Change subject: mb/google/poppy/variant/nocturne: correct wifi wake register ...................................................................... mb/google/poppy/variant/nocturne: correct wifi wake register Wifi wake register is incorrectly set in devicetree. Set wifi wake to its correct wake source, GPE0_DW2_01. BUG=b:117330593 TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture, connect wifi to a hotspot, suspend device, echo freeze > /sys/power/state, and then shutdown the hotspot and verify device wakes. Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> Reviewed-on: https://review.coreboot.org/28938 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/poppy/variants/nocturne/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index ddb2e34..919a073 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -393,7 +393,7 @@ end # I2C #4 - Audio device pci 1c.0 on chip drivers/intel/wifi - register "wake" = "GPE0_PCI_EXP" + register "wake" = "GPE0_DW2_01" device pci 00.0 on end end end # PCI Express Port 1 -- To view, visit https://review.coreboot.org/28938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af Gerrit-Change-Number: 28938 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/{gm45, i945, pineview}: Use macro instead of GGC address
by Patrick Georgi (Code Review) 08 Oct '18

08 Oct '18

Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/28909 ) Change subject: nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address ...................................................................... nb/intel/{gm45,i945,pineview}: Use macro instead of GGC address Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/28909 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/gma.c 3 files changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, approved diff --git a/src/northbridge/intel/gm45/iommu.c b/src/northbridge/intel/gm45/iommu.c index 0108116..f424564 100644 --- a/src/northbridge/intel/gm45/iommu.c +++ b/src/northbridge/intel/gm45/iommu.c @@ -46,7 +46,7 @@ MCHBAR32(0x20) = IOMMU_BASE4 | 1; /* all other DMA sources */ /* clear GTT */ - u32 gtt = pci_read_config16(PCI_DEV(0, 0, 0), 0x52); + u16 gtt = pci_read_config16(PCI_DEV(0, 0, 0), D0F0_GGC); if (gtt & 0x400) { /* VT mode */ pci_devfn_t igd = PCI_DEV(0, 2, 0); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 7de2c73..a38874a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -685,7 +685,7 @@ if (reg32 == 0x030000) { printk(BIOS_DEBUG, "PCIe device is VGA. Disabling IGD.\n"); reg16 = (1 << 1); - pci_write_config16(PCI_DEV(0, 0x0, 0), 0x52, reg16); + pci_write_config16(PCI_DEV(0, 0x0, 0), GGC, reg16); reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN); reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1); diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index eb67c65..e075ac1 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -98,7 +98,7 @@ gtt_setup(mmio); - pci_write_config16(vga, 0x52, 0x130); + pci_write_config16(vga, GGC, 0x130); /* Disable VGA. */ write32(mmio + VGACNTRL, VGA_DISP_DISABLE); -- To view, visit https://review.coreboot.org/28909 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I233e835180fd445961b6deb74ea7afc2821c236e Gerrit-Change-Number: 28909 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Nico Huber (Code Review) 08 Oct '18

08 Oct '18

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Change in coreboot[master]: nb/i945: Check if IGD is enabled before R/W to dev(0, 2)
by Nico Huber (Code Review) 08 Oct '18

08 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/28935 ) Change subject: nb/i945: Check if IGD is enabled before R/W to dev(0, 2) ...................................................................... Patch Set 1: (3 comments) > I do not have a datasheet, but, if I'm not wrong, using r2 on > vendor bios of d945gclf (supported board), it seems making a test > before writing : > MEMORY[0xFED14F08] |= 0x6000u; > MEMORY[0xFED14F0A] |= 0x6000u; > MEMORY[0xFED14F0C] |= 0x6000u; What does it test? CAPID[38] maybe? or DEVEN? https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.c File src/northbridge/intel/i945/raminit.c: https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.… PS1, Line 2151: > here by default, IGD is "enabled" even if it is not (case we use an external GPU for example) Again, AFAICS, this code runs before the external GPU decision is made. It can't be disabled yet. https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.… PS1, Line 2306: : : : > as we have : "int integrated_graphics = 1;" […] But it shows us what to do if. https://review.coreboot.org/#/c/28935/1/src/northbridge/intel/i945/raminit.… PS1, Line 2764: pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & : (DEVEN_D2F0 | DEVEN_D2F1) Always true? -- To view, visit https://review.coreboot.org/28935 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51ab94393710ce0222b353ab0cef28621fafaacf Gerrit-Change-Number: 28935 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 08 Oct 2018 09:40:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/mb: Remove dead code
by Elyes HAOUAS (Code Review) 08 Oct '18

08 Oct '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28876 ) Change subject: src/mb: Remove dead code ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28876 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I318de3e7c807bb5b5efdf61fef387d34225a8149 Gerrit-Change-Number: 28876 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/nb/i945: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement
by Elyes HAOUAS (Code Review) 08 Oct '18

08 Oct '18

Elyes HAOUAS has abandoned this change. ( https://review.coreboot.org/28878 ) Change subject: src/nb/i945: Fix "CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8" if statement ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/28878 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I1ff87c76b3aef4af93d88dd9c02a743656aacfc0 Gerrit-Change-Number: 28878 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mainboard/google/kahlee: Set PSPP setting to BalancedHigh
by Akshu Agrawal (Code Review) 08 Oct '18

08 Oct '18

Akshu Agrawal has uploaded this change for review. ( https://review.coreboot.org/28967 Change subject: mainboard/google/kahlee: Set PSPP setting to BalancedHigh ...................................................................... mainboard/google/kahlee: Set PSPP setting to BalancedHigh Setting default PSPP setiing to BalancedLow was causing audio playback issue in most of the units. With BalancedLow either there was no sound or noise on playback. Switching to BalancedHigh as defuault option. BUG=b:116553085, b:112020107 TEST=Test playback and hear proper audio. Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee Signed-off-by: Akshu Agrawal <akshu.agrawal(a)amd.com> --- M src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/28967/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c index 6d34d4a..ae4ad04 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c +++ b/src/mainboard/google/kahlee/variants/baseboard/OemCustomize.c @@ -150,7 +150,7 @@ VOID __weak OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly) { InitEarly->GnbConfig.PcieComplexList = (void *)&PcieComplex; - InitEarly->GnbConfig.PsppPolicy = PsppBalanceLow; + InitEarly->GnbConfig.PsppPolicy = PsppBalanceHigh; InitEarly->PlatformConfig.GnbAzI2sBusSelect = GnbAcpI2sBus; InitEarly->PlatformConfig.GnbAzI2sBusPinConfig = GnbAcp2Tx4RxBluetooth; if ((IS_ENABLED(CONFIG_BOARD_GOOGLE_LIARA)) && (board_id() <= 4)) -- To view, visit https://review.coreboot.org/28967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee Gerrit-Change-Number: 28967 Gerrit-PatchSet: 1 Gerrit-Owner: Akshu Agrawal <akshu.agrawal(a)amd.com>

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Change in coreboot[master]: Documentation: Improve elgon documentation
by Philipp Deppenwiese (Code Review) 08 Oct '18

08 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28966 ) Change subject: Documentation: Improve elgon documentation ...................................................................... Documentation: Improve elgon documentation * Convert PNG to JPG and reduce image quality. * Mark flash IC and USB serial connector. * Mark SPI programming header. * Add programming header pinout. Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/28966 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/mainboard/opencellular/elgon.md A Documentation/mainboard/opencellular/elgon1.jpg D Documentation/mainboard/opencellular/elgon1.png A Documentation/mainboard/opencellular/elgon2.jpg D Documentation/mainboard/opencellular/elgon2.png A Documentation/mainboard/opencellular/elgon_conn_j9.png A Documentation/mainboard/opencellular/elgon_conn_j9_pcb.jpg 7 files changed, 18 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md index 37d05e6..02225a2 100644 --- a/Documentation/mainboard/opencellular/elgon.md +++ b/Documentation/mainboard/opencellular/elgon.md @@ -40,20 +40,32 @@ The EVT board does have a pinheader to flash the SOIC-8 in circuit. Directly connecting a Pomona test-clip on the flash is also possible. -TODO: pinout - **Total board view of EVT** ![][elgon1] -[elgon1]: elgon1.png +[elgon1]: elgon1.jpg -**Closeup view of SOIC-8 flash IC, programming pin header and -USB serial connector of EVT** +**Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)** ![][elgon2] -[elgon2]: elgon2.png +[elgon2]: elgon2.jpg + + +**SPI header (marked blue)** + +![][elgon_conn_j9_pcb] + +[elgon_conn_j9_pcb]: elgon_conn_j9_pcb.jpg + +**SPI header pinout** + +Dediprog compatible pinout. + +![][elgon_conn_j9] + +[elgon_conn_j9]: elgon_conn_j9.png ## Technology diff --git a/Documentation/mainboard/opencellular/elgon1.jpg b/Documentation/mainboard/opencellular/elgon1.jpg new file mode 100644 index 0000000..4bb72cf --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon1.jpg Binary files differ diff --git a/Documentation/mainboard/opencellular/elgon1.png b/Documentation/mainboard/opencellular/elgon1.png deleted file mode 100644 index c1eb544..0000000 --- a/Documentation/mainboard/opencellular/elgon1.png +++ /dev/null Binary files differ diff --git a/Documentation/mainboard/opencellular/elgon2.jpg b/Documentation/mainboard/opencellular/elgon2.jpg new file mode 100644 index 0000000..63c0b6c --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon2.jpg Binary files differ diff --git a/Documentation/mainboard/opencellular/elgon2.png b/Documentation/mainboard/opencellular/elgon2.png deleted file mode 100644 index f12a734..0000000 --- a/Documentation/mainboard/opencellular/elgon2.png +++ /dev/null Binary files differ diff --git a/Documentation/mainboard/opencellular/elgon_conn_j9.png b/Documentation/mainboard/opencellular/elgon_conn_j9.png new file mode 100644 index 0000000..345d616 --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon_conn_j9.png Binary files differ diff --git a/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.jpg b/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.jpg new file mode 100644 index 0000000..9e21769 --- /dev/null +++ b/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.jpg Binary files differ -- To view, visit https://review.coreboot.org/28966 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47 Gerrit-Change-Number: 28966 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018