coreboot-gerrit October 2018

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Change in coreboot[master]: mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings
by Chris Zhou (Code Review) 08 Oct '18

08 Oct '18

Chris Zhou has uploaded this change for review. ( https://review.coreboot.org/28960 Change subject: mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings ...................................................................... mb/google/kahlee/variants/liara: Update H1/TP/TS i2c timings After adjustment on Liara EVT H1: 392.03 KHz TP: 397.87 KHz TS: 397.71 KHz BUG=b:116309237 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a Signed-off-by: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com> --- M src/mainboard/google/kahlee/variants/liara/devicetree.cb 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/28960/1 diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index a213492..0dfe204 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -32,22 +32,22 @@ register "i2c[1]" = "{ .early_init = 1, .speed = I2C_SPEED_FAST, - .rise_time_ns = 45, - .fall_time_ns = 4, + .rise_time_ns = 3, + .fall_time_ns = 2, }" # Enable I2C2 for trackpad, pen at 400kHz register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 48, - .fall_time_ns = 37, + .rise_time_ns = 3, + .fall_time_ns = 2, }" # Enable I2C3 for touchscreen at 400kHz register "i2c[3]" = "{ .speed = I2C_SPEED_FAST, - .rise_time_ns = 82, - .fall_time_ns = 67, + .rise_time_ns = 16, + .fall_time_ns = 8, }" device cpu_cluster 0 on -- To view, visit https://review.coreboot.org/28960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a Gerrit-Change-Number: 28960 Gerrit-PatchSet: 1 Gerrit-Owner: Chris Zhou <chris_zhou(a)compal.corp-partner.google.com>

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Change in coreboot[master]: drivers/intel/fsp2_0: Hook up IntelFSP repo
by Philipp Deppenwiese (Code Review) 07 Oct '18

07 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28593 ) Change subject: drivers/intel/fsp2_0: Hook up IntelFSP repo ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/#/c/28593/8/src/soc/intel/skylake/Kconfig File src/soc/intel/skylake/Kconfig: https://review.coreboot.org/#/c/28593/8/src/soc/intel/skylake/Kconfig@307 PS8, Line 307: #default "3rdparty/fsp/SkylakeFspBinPkg/Include/" if SOC_INTEL_SKYLAKE Remove comments https://review.coreboot.org/#/c/28593/8/src/soc/intel/skylake/Kconfig@314 PS8, Line 314: #default "3rdparty/fsp/SkylakeFspBinPkg/SkylakeFsp.fd" if SOC_INTEL_SKYLAKE Here again -- To view, visit https://review.coreboot.org/28593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Gerrit-Change-Number: 28593 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krystian Hebel (1002088) Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 02:45:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/intel/fsp2_0: Hook up IntelFSP repo
by Philipp Deppenwiese (Code Review) 07 Oct '18

07 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28593 ) Change subject: drivers/intel/fsp2_0: Hook up IntelFSP repo ...................................................................... Patch Set 8: Code-Review+2 @Naresh let's do it in a follow up -- To view, visit https://review.coreboot.org/28593 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7 Gerrit-Change-Number: 28593 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krystian Hebel (1002088) Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Nathaniel L Desimone <nathaniel.l.desimone(a)intel.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 02:43:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/fizz: Prepare sharing directory for variants
by David Wu (Code Review) 07 Oct '18

07 Oct '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/28959 Change subject: mb/google/fizz: Prepare sharing directory for variants ...................................................................... mb/google/fizz: Prepare sharing directory for variants Clean up Kconfig file in order to support variants for fizz. Add BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants to use the common baseboard configs. BUG=b:117066935 BRANCH=Fizz TEST=emerge-fizz coreboot Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/Kconfig.name 2 files changed, 9 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/28959/1 diff --git a/src/mainboard/google/fizz/Kconfig b/src/mainboard/google/fizz/Kconfig index c6e43d8..7f4989b 100644 --- a/src/mainboard/google/fizz/Kconfig +++ b/src/mainboard/google/fizz/Kconfig @@ -1,7 +1,6 @@ -if BOARD_GOOGLE_FIZZ -config BOARD_SPECIFIC_OPTIONS - def_bool y +config BOARD_GOOGLE_BASEBOARD_FIZZ + def_bool n select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_SPI_ACPI @@ -24,6 +23,8 @@ select RT8168_SET_LED_MODE select SPD_READ_BY_WORD +if BOARD_GOOGLE_BASEBOARD_FIZZ + config VBOOT select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_EC_EFS @@ -37,7 +38,7 @@ config GBB_HWID string depends on CHROMEOS - default "FIZZ TEST 5997" + default "FIZZ TEST 5997" if BOARD_GOOGLE_FIZZ config MAINBOARD_DIR string @@ -45,11 +46,11 @@ config MAINBOARD_PART_NUMBER string - default "Fizz" + default "Fizz" if BOARD_GOOGLE_FIZZ config MAINBOARD_FAMILY string - default "Google_Fizz" + default "Google_Fizz" if BOARD_GOOGLE_FIZZ config MAX_CPUS int @@ -71,4 +72,4 @@ bool "Include blobs for audio." select NHLT_RT5663 -endif +endif # BOARD_GOOGLE_BASEBOARD_FIZZ diff --git a/src/mainboard/google/fizz/Kconfig.name b/src/mainboard/google/fizz/Kconfig.name index 12685d9..28c9700 100644 --- a/src/mainboard/google/fizz/Kconfig.name +++ b/src/mainboard/google/fizz/Kconfig.name @@ -1,2 +1,3 @@ config BOARD_GOOGLE_FIZZ bool "Fizz" + select BOARD_GOOGLE_BASEBOARD_FIZZ -- To view, visit https://review.coreboot.org/28959 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3 Gerrit-Change-Number: 28959 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: util/intelvbttool: Rewrite tool
by Philipp Deppenwiese (Code Review) 07 Oct '18

07 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/18902 ) Change subject: util/intelvbttool: Rewrite tool ...................................................................... util/intelvbttool: Rewrite tool * Add Makefile dependency to source file * Add argument support * Add help support * Print usage on wrong arguments * Add support for parsing VBT binary file * Add support for parsing PCI Option ROM * Add support for writing VBT binary file * Add support for patching PCI Option ROM * Keep support for accessing legacy VGA area Option ROM * Keep support for dumping VBT contents to stdout Allows to extract VBT, analyse VBT and patch PCI Option ROMs as needed. The required arguments have been changed: ./intelvbttool --<SOURCECMD> [filename] --<DESTCMD> [filename] SOURCECMD set the VBT source. Supported: inlegacy : Legacy BIOS area at phys. memory 0xc0000 invbt : Read raw Intel VBT file inoprom : Read VBT from Intel Option ROM file DESTCMD set the VBT destination. Supported: outdump : Print VBT in human readable form outvbt : Write raw Intel VBT file patchoprom: Patch existing Intel Option ROM Any combination of SOURCECMD and DESTCMD is possible. Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/18902 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M util/intelvbttool/Makefile M util/intelvbttool/intelvbttool.c 2 files changed, 807 insertions(+), 113 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile index 7d50d30..fb9aade 100644 --- a/util/intelvbttool/Makefile +++ b/util/intelvbttool/Makefile @@ -15,12 +15,13 @@ PROGRAM = intelvbttool CC ?= gcc -CFLAGS ?= -O2 +CFLAGS ?= -O2 -g CFLAGS += -Wall -Werror +CFLAGS += -I../../src/commonlib/include all: $(PROGRAM) -$(PROGRAM): +$(PROGRAM): $(PROGRAM).c $(CC) $(CFLAGS) $(CPPFLAGS) $(PROGRAM).c -o $(PROGRAM) clean: diff --git a/util/intelvbttool/intelvbttool.c b/util/intelvbttool/intelvbttool.c index f0216dd..c8b973e 100644 --- a/util/intelvbttool/intelvbttool.c +++ b/util/intelvbttool/intelvbttool.c @@ -20,7 +20,10 @@ #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> +#include <getopt.h> #include <errno.h> +#include <stdarg.h> +#include <commonlib/helpers.h> typedef uint8_t u8; typedef uint16_t u16; @@ -30,11 +33,28 @@ typedef struct { u16 signature; u8 size; - u8 reserved[21]; + u8 entrypoint[4]; + u8 checksum; + u8 reserved[16]; u16 pcir_offset; u16 vbt_offset; } __attribute__ ((packed)) optionrom_header_t; +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + struct vbt_header { u8 signature[20]; u16 version; @@ -221,6 +241,8 @@ } __attribute__ ((packed)); +static const size_t ignore_checksum = 1; + #define BDB_GENERAL_FEATURES 1 #define BDB_GENERAL_DEFINITIONS 2 @@ -233,143 +255,370 @@ #define BDB_SKIP 254 -static void parse_vbt(const void *vbt) +/* print helpers */ +static void print(const char *format, ...) { - const struct vbt_header *head = vbt; + va_list args; + fprintf(stdout, "VBTTOOL: "); + va_start(args, format); + vfprintf(stdout, format, args); + va_end(args); +} + +static void printt(const char *format, ...) +{ + va_list args; + fprintf(stdout, "\t"); + va_start(args, format); + vfprintf(stdout, format, args); + va_end(args); +} + +static void printwarn(const char *format, ...) +{ + va_list args; + fprintf(stderr, "VBTTOOL: WARN: "); + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +} + +static void printerr(const char *format, ...) +{ + va_list args; + fprintf(stderr, "VBTTOOL: ERR: "); + va_start(args, format); + vfprintf(stderr, format, args); + va_end(args); +} + +struct fileobject { + unsigned char *data; + size_t size; +}; + +/* file object helpers */ + +/* + * Alloc a file object of given size. + * Returns NULL on error. + */ +static struct fileobject *malloc_fo(const size_t size) +{ + struct fileobject *fo; + if (!size) + return NULL; + + fo = malloc(sizeof(*fo)); + if (!fo) + return NULL; + fo->data = malloc(size); + if (!fo->data) { + free(fo); + return NULL; + } + fo->size = size; + + return fo; +} + +/* Free a fileobject structure */ +static void free_fo(struct fileobject *fo) +{ + if (fo) { + free(fo->data); + free(fo); + } +} + +/* Resize file object and keep memory content */ +static struct fileobject *remalloc_fo(struct fileobject *old, + const size_t size) +{ + struct fileobject *fo = old; + + if (!old || !size) + return NULL; + + fo->data = realloc(fo->data, size); + + if (!fo->data) + return NULL; + + fo->size = size; + + return fo; +} + +/* + * Creates a new subregion copy of fileobject. + * Returns NULL if offset is greater than fileobject size. + * Returns NULL on error. + */ +static struct fileobject *malloc_fo_sub(const struct fileobject *old, + const size_t off) +{ + struct fileobject *fo; + + if (!old || off > old->size) + return NULL; + + fo = malloc_fo(old->size - off); + if (!fo) + return NULL; + + memcpy(fo->data, old->data + off, fo->size); + + return fo; +} + +/* file helpers */ + +/* Create fileobject from file */ +static struct fileobject *read_file(const char *filename) +{ + FILE *fd = fopen(filename, "rb"); + + if (!fd) { + printerr("%s open failed: %s\n", filename, strerror(errno)); + return NULL; + } + + if (fseek(fd, 0, SEEK_END)) { + printerr("%s seek failed: %s\n", filename, strerror(errno)); + fclose(fd); + return NULL; + } + + const off_t size = ftell(fd); + if (size < 0 || size > SIZE_MAX) { + printerr("%s tell failed: %s\n", filename, strerror(errno)); + fclose(fd); + return NULL; + } + + if (fseek(fd, 0, SEEK_SET)) { + printerr("%s seek failed: %s\n", filename, strerror(errno)); + fclose(fd); + return NULL; + } + + struct fileobject *fo = malloc_fo(size); + if (!fo) { + printerr("malloc failed\n"); + fclose(fd); + return NULL; + } + + if (fread(fo->data, 1, size, fd) != size) { + fclose(fd); + free_fo(fo); + return NULL; + } + + if (fclose(fd)) { + printerr("%s close failed: %s\n", filename, strerror(errno)); + free_fo(fo); + return NULL; + } + + fo->size = size; + + return fo; +} + +/* Create fileobject from physical memory at given address of size 64 KiB */ +static struct fileobject *read_physmem(size_t addr) +{ + const int fd = open("/dev/mem", O_RDONLY); + const size_t size = 64 * 2 * KiB; + if (fd < 0) { + printerr("/dev/mem open failed: %s\n", strerror(errno)); + return NULL; + } + + const void *data = mmap(0, size, PROT_READ, MAP_SHARED, fd, addr); + if (data == MAP_FAILED) { + close(fd); + printerr("mmap failed: %s\n", strerror(errno)); + return NULL; + } + + struct fileobject *fo = malloc_fo(size); + if (!fo) { + printerr("malloc failed\n"); + munmap((void *)data, size); + close(fd); + return NULL; + } + + memcpy(fo->data, data, size); + munmap((void *)data, size); + + if (close(fd)) { + printerr("/dev/mem close failed: %s\n", strerror(errno)); + free_fo(fo); + return NULL; + } + + return fo; +} + +/* Write fileobject contents to file */ +static int write_file(const char *filename, const struct fileobject *fo) +{ + FILE *fd_out = fopen(filename, "wb"); + + if (!fd_out) { + printerr("%s open failed: %s\n", filename, strerror(errno)); + return 1; + } + if (fwrite(fo->data, 1, fo->size, fd_out) != fo->size) { + fclose(fd_out); + return 1; + } + return fclose(fd_out); +} + +/* dump VBT contents in human readable form */ +static void dump_vbt(const struct fileobject *fo) +{ + if (fo->size < sizeof(struct vbt_header)) + return; + + const struct vbt_header *head = (const struct vbt_header *)fo->data; const struct bdb_header *bdb; - int i; const u8 *ptr; + int i; int is_first_skip = 1; - if (memcmp(head->signature, "$VBT", 4) != 0) { - fprintf(stderr, "invalid VBT signature\n"); - exit(1); - } - printf("signature: <%20.20s>\n", head->signature); - printf("version: %d.%02d\n", head->version / 100, + printt("signature: <%20.20s>\n", head->signature); + printt("version: %d.%02d\n", head->version / 100, head->version % 100); if (head->header_size != sizeof(struct vbt_header)) - printf("header size: 0x%x\n", head->header_size); - printf("VBT size: 0x%x\n", head->vbt_size); - printf("VBT checksum: 0x%x\n", head->vbt_checksum); + printt("header size: 0x%x\n", head->header_size); + printt("VBT size: 0x%x\n", head->vbt_size); + printt("VBT checksum: 0x%x\n", head->vbt_checksum); if (head->reserved0) - printf("header reserved0: 0x%x\n", head->reserved0); + printt("header reserved0: 0x%x\n", head->reserved0); if (head->bdb_offset != sizeof(struct vbt_header)) - printf("BDB offset: 0x%x\n", head->bdb_offset); + printt("BDB offset: 0x%x\n", head->bdb_offset); for (i = 0; i < 4; i++) if (head->aim_offset[i]) - printf("AIM[%d] offset: 0x%x\n", i, + printt("AIM[%d] offset: 0x%x\n", i, head->aim_offset[i]); - bdb = (const void *) ((const char *) vbt + head->bdb_offset); + if (head->bdb_offset + sizeof(*bdb) > fo->size) + return; + bdb = (const void *) (fo->data + head->bdb_offset); if (memcmp("BIOS_DATA_BLOCK ", bdb->signature, 16) != 0) { - fprintf(stderr, "invalid BDB signature:%s\n", + printerr("invalid BDB signature:%s\n", bdb->signature); exit(1); } - printf("BDB version: %d.%02d\n", bdb->version / 100, + printt("BDB version: %d.%02d\n", bdb->version / 100, bdb->version % 100); if (bdb->header_size != sizeof(struct bdb_header)) - printf("BDB header size: 0x%x\n", bdb->header_size); + printt("BDB header size: 0x%x\n", bdb->header_size); if (bdb->bdb_size != head->vbt_size - head->bdb_offset) - printf("BDB size: 0x%x\n", bdb->bdb_size); + printt("BDB size: 0x%x\n", bdb->bdb_size); for (ptr = (const u8 *) bdb + bdb->header_size; ptr < (const u8 *) bdb + bdb->bdb_size;) { u16 secsz = (ptr[1] | (ptr[2] << 8)); u8 sectype = ptr[0]; const u8 *section = ptr + 3; - printf("section type %d, size 0x%x\n", sectype, secsz); + printt("section type %d, size 0x%x\n", sectype, secsz); ptr += secsz + 3; switch (sectype) { case BDB_GENERAL_FEATURES:{ const struct bdb_general_features *sec = (const void *) section; - printf("General features:\n"); + printt("General features:\n"); if (sec->panel_fitting) - printf("\tpanel_fitting = 0x%x\n", + printt("\tpanel_fitting = 0x%x\n", sec->panel_fitting); if (sec->flexaim) - printf("\tflexaim = 0x%x\n", + printt("\tflexaim = 0x%x\n", sec->flexaim); if (sec->msg_enable) - printf("\tmsg_enable = 0x%x\n", + printt("\tmsg_enable = 0x%x\n", sec->msg_enable); if (sec->clear_screen) - printf("\tclear_screen = 0x%x\n", + printt("\tclear_screen = 0x%x\n", sec->clear_screen); if (sec->color_flip) - printf("\tcolor_flip = 0x%x\n", + printt("\tcolor_flip = 0x%x\n", sec->color_flip); if (sec->download_ext_vbt) - printf + printt ("\tdownload_ext_vbt = 0x%x\n", sec->download_ext_vbt); - printf("\t*enable_ssc = 0x%x\n", + printt("\t*enable_ssc = 0x%x\n", sec->enable_ssc); - printf("\t*ssc_freq = 0x%x\n", + printt("\t*ssc_freq = 0x%x\n", sec->ssc_freq); if (sec->enable_lfp_on_override) - printf + printt ("\tenable_lfp_on_override = 0x%x\n", sec->enable_lfp_on_override); if (sec->disable_ssc_ddt) - printf + printt ("\tdisable_ssc_ddt = 0x%x\n", sec->disable_ssc_ddt); if (sec->rsvd7) - printf("\trsvd7 = 0x%x\n", + printt("\trsvd7 = 0x%x\n", sec->rsvd7); - printf("\t*display_clock_mode = 0x%x\n", + printt("\t*display_clock_mode = 0x%x\n", sec->display_clock_mode); if (sec->rsvd8) - printf("\trsvd8 = 0x%x\n", + printt("\trsvd8 = 0x%x\n", sec->rsvd8); - printf("\tdisable_smooth_vision = 0x%x\n", + printt("\tdisable_smooth_vision = 0x%x\n", sec->disable_smooth_vision); if (sec->single_dvi) - printf("\tsingle_dvi = 0x%x\n", + printt("\tsingle_dvi = 0x%x\n", sec->single_dvi); if (sec->rsvd9) - printf("\trsvd9 = 0x%x\n", + printt("\trsvd9 = 0x%x\n", sec->rsvd9); - printf + printt ("\t*fdi_rx_polarity_inverted = 0x%x\n", sec->fdi_rx_polarity_inverted); if (sec->rsvd10) - printf("\trsvd10 = 0x%x\n", + printt("\trsvd10 = 0x%x\n", sec->rsvd10); if (sec->legacy_monitor_detect) - printf + printt ("\tlegacy_monitor_detect = 0x%x\n", sec->legacy_monitor_detect); - printf("\t*int_crt_support = 0x%x\n", + printt("\t*int_crt_support = 0x%x\n", sec->int_crt_support); - printf("\t*int_tv_support = 0x%x\n", + printt("\t*int_tv_support = 0x%x\n", sec->int_tv_support); if (sec->int_efp_support) - printf + printt ("\tint_efp_support = 0x%x\n", sec->int_efp_support); if (sec->dp_ssc_enb) - printf("\tdp_ssc_enb = 0x%x\n", + printt("\tdp_ssc_enb = 0x%x\n", sec->dp_ssc_enb); if (sec->dp_ssc_freq) - printf("\tdp_ssc_freq = 0x%x\n", + printt("\tdp_ssc_freq = 0x%x\n", sec->dp_ssc_freq); if (sec->rsvd11) - printf("\trsvd11 = 0x%x\n", + printt("\trsvd11 = 0x%x\n", sec->rsvd11); break; } case BDB_DRIVER_FEATURES:{ const struct bdb_driver_features *sec = (const void *) section; - printf("\t*LVDS config: %d\n", + printt("\t*LVDS config: %d\n", sec->lvds_config); - printf("\t*Dual frequency: %d\n", + printt("\t*Dual frequency: %d\n", sec->dual_frequency); break; @@ -377,7 +626,7 @@ case BDB_SDVO_LVDS_OPTIONS:{ const struct bdb_sdvo_lvds_options *sec = (const void *) section; - printf("\t*Panel type: %d\n", + printt("\t*Panel type: %d\n", sec->panel_type); break; @@ -386,29 +635,29 @@ const struct bdb_general_definitions *sec = (const void *) section; int ndev; - printf("\t*CRT DDC GMBUS pin: %d\n", + printt("\t*CRT DDC GMBUS pin: %d\n", sec->crt_ddc_gmbus_pin); - printf("\tDPMS ACPI: %d\n", + printt("\tDPMS ACPI: %d\n", sec->dpms_acpi); - printf("\tSkip boot CRT detect: %d\n", + printt("\tSkip boot CRT detect: %d\n", sec->skip_boot_crt_detect); - printf("\tDPMS aim: %d\n", sec->dpms_aim); + printt("\tDPMS aim: %d\n", sec->dpms_aim); if (sec->rsvd1) - printf("\trsvd1: 0x%x\n", + printt("\trsvd1: 0x%x\n", sec->rsvd1); - printf("\tboot_display: { %x, %x }\n", + printt("\tboot_display: { %x, %x }\n", sec->boot_display[0], sec->boot_display[1]); if (sec->child_dev_size != sizeof(struct common_child_dev_config)) - printf("\tchild_dev_size: %d\n", + printt("\tchild_dev_size: %d\n", sec->child_dev_size); ndev = (secsz - sizeof(*sec)) / sizeof(struct common_child_dev_config); - printf("\t%d devices\n", ndev); + printt("\t%d devices\n", ndev); for (i = 0; i < ndev; i++) { - printf("\t*device type: %x ", + printt("\t*device type: %x ", sec->devices[i]. device_type); #define DEVICE_TYPE_INT_LFP 0x1022 @@ -416,35 +665,35 @@ #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 switch (sec->devices[i].device_type) { case DEVICE_TYPE_INT_LFP: - printf("(flat panel)\n"); + printt("(flat panel)\n"); break; case DEVICE_TYPE_INT_TV: - printf("(TV)\n"); + printt("(TV)\n"); break; case DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR: - printf + printt ("(DVI)\n"); break; case 0: - printf("(Empty)\n"); + printt("(Empty)\n"); break; default: - printf("(Unknown)\n"); + printt("(Unknown)\n"); break; } if (!sec->devices[i].device_type) continue; - printf("\t *dvo_port: %x\n", + printt("\t *dvo_port: %x\n", sec->devices[i].dvo_port); - printf("\t *i2c_pin: %x\n", + printt("\t *i2c_pin: %x\n", sec->devices[i].i2c_pin); - printf("\t *slave_addr: %x\n", + printt("\t *slave_addr: %x\n", sec->devices[i].slave_addr); - printf("\t *ddc_pin: %x\n", + printt("\t *ddc_pin: %x\n", sec->devices[i].ddc_pin); - printf("\t *dvo_wiring: %x\n", + printt("\t *dvo_wiring: %x\n", sec->devices[i].dvo_wiring); - printf("\t edid_ptr: %x\n", + printt("\t edid_ptr: %x\n", sec->devices[i].edid_ptr); } @@ -456,84 +705,528 @@ if (!is_first_skip) break; is_first_skip = 0; - printf("\ttype: %x\n", sec->type); - printf("\trelstage: %x\n", sec->relstage); - printf("\tchipset: %x\n", sec->chipset); - printf(sec->lvds_present ? "\tLVDS\n" + printt("\ttype: %x\n", sec->type); + printt("\trelstage: %x\n", sec->relstage); + printt("\tchipset: %x\n", sec->chipset); + printt(sec->lvds_present ? "\tLVDS\n" : "\tNo LVDS\n"); - printf(sec->tv_present ? "\tTV\n" + printt(sec->tv_present ? "\tTV\n" : "\tNo TV\n"); if (sec->rsvd2) - printf("\trsvd2: 0x%x\n", + printt("\trsvd2: 0x%x\n", sec->rsvd2); for (i = 0; i < 4; i++) if (sec->rsvd3[i]) - printf + printt ("\trsvd3[%d]: 0x%x\n", i, sec->rsvd3[i]); - printf("\tSignon: %.155s\n", sec->signon); - printf("\tCopyright: %.155s\n", + printt("\tSignon: %.155s\n", sec->signon); + printt("\tCopyright: %.155s\n", sec->copyright); - printf("\tCode segment: %x\n", + printt("\tCode segment: %x\n", sec->code_segment); - printf("\tDOS Boot mode: %x\n", + printt("\tDOS Boot mode: %x\n", sec->dos_boot_mode); - printf("\tBandwidth percent: %x\n", + printt("\tBandwidth percent: %x\n", sec->bandwidth_percent); if (sec->rsvd4) - printf("\trsvd4: 0x%x\n", + printt("\trsvd4: 0x%x\n", sec->rsvd4); - printf("\tBandwidth percent: %x\n", + printt("\tBandwidth percent: %x\n", sec->resize_pci_bios); if (sec->rsvd5) - printf("\trsvd5: 0x%x\n", + printt("\trsvd5: 0x%x\n", sec->rsvd5); break; } } } - } -static void parse_vbios(const void *ptr) +/* Returns a new fileobject containing a valid VBT */ +static void parse_vbt(const struct fileobject *fo, + struct fileobject **vbt) { - const optionrom_header_t *oh; - oh = ptr; + *vbt = NULL; + + if (fo->size < sizeof(struct vbt_header)) { + printerr("image is to small\n"); + return; + } + + const struct vbt_header *head = + (const struct vbt_header *)fo->data; + + if (memcmp(head->signature, "$VBT", 4) != 0) { + printerr("invalid VBT signature\n"); + return; + } + + if (!head->vbt_size || head->vbt_size > fo->size) { + printerr("invalid VBT size\n"); + return; + } + + if (!head->bdb_offset || + head->bdb_offset > fo->size - sizeof(struct bdb_header)) { + printerr("invalid BDB offset\n"); + return; + } + + if (!head->header_size || head->header_size > fo->size) { + printerr("invalid header size\n"); + return; + } + + const struct bdb_header *const bdb_head = + (const struct bdb_header *)((const u8 *)head + head->bdb_offset); + if (memcmp(bdb_head->signature, "BIOS_DATA_BLOCK ", 16) != 0) { + printerr("invalid BDB signature\n"); + return; + } + + if (!bdb_head->header_size || bdb_head->header_size > fo->size) { + printerr("invalid BDB header size\n"); + return; + } + + /* Duplicate fo as caller is owner and remalloc frees the object */ + *vbt = remalloc_fo(malloc_fo_sub(fo, 0), head->vbt_size); +} + +/* Option ROM checksum */ +static u8 checksum_vbios(const optionrom_header_t *oh) +{ + const u8 *ptr = (const u8 *)oh; + size_t i; + + u8 cksum = 0; + for (i = 0; i < ((MIN(oh->size, 128)) * 512); i++) + cksum += ptr[i]; + + return cksum; +} + +/* Verify Option ROM contents */ +static int is_valid_vbios(const struct fileobject *fo) +{ + if (fo->size > 64 * 2 * KiB) { + printerr("VBIOS is to big\n"); + return 0; + } + + if (fo->size < sizeof(optionrom_header_t)) { + printerr("VBIOS is to small\n"); + return 0; + } + + const optionrom_header_t *oh = (const optionrom_header_t *)fo->data; + if (oh->signature != 0xaa55) { - fprintf(stderr, "bad oprom signature: %x\n", - oh->signature); - return; + printerr("bad oprom signature: 0x%x\n", oh->signature); + return 0; } + + if (oh->size == 0 || oh->size > 0x80 || oh->size * 512 > fo->size) { + printerr("bad oprom size: 0x%x\n", oh->size); + return 0; + } + + const u8 cksum = checksum_vbios(oh); + if (cksum) { + if (!ignore_checksum) { + printerr("bad oprom checksum: 0x%x\n", cksum); + return 0; + } + printwarn("bad oprom checksum: 0x%x\n", cksum); + } + + if (oh->pcir_offset + sizeof(optionrom_pcir_t) > fo->size) { + printerr("bad pcir offset: 0x%x\n", oh->pcir_offset); + return 0; + } + + if (oh->pcir_offset) { + const optionrom_pcir_t *pcir; + pcir = (const optionrom_pcir_t *) + ((const u8 *)oh + oh->pcir_offset); + + if (pcir->signature != 0x52494350) { + printerr("Invalid PCIR signature\n"); + return 0; + } + + if (pcir->vendor != 0x8086) { + printerr("Not an Intel VBIOS\n"); + return 0; + } + + if (pcir->classcode[0] != 0 || pcir->classcode[1] != 0 || + pcir->classcode[2] != 3) { + printerr("Not a VGA Option Rom\n"); + return 0; + } + } else { + printwarn("no PCIR header found\n"); + } + + return 1; +} + +/* + * Parse Option ROM and return a valid VBT fileobject. + * Caller has to make sure that it is a valid VBIOS. + * Return a NULL fileobject on error. + */ +static void parse_vbios(const struct fileobject *fo, + struct fileobject **vbt) +{ + const optionrom_header_t *oh = (const optionrom_header_t *)fo->data; + const struct vbt_header *head; + size_t i; + + *vbt = NULL; + if (!oh->vbt_offset) { - fprintf(stderr, "no VBT found\n"); + printerr("no VBT found\n"); return; } - parse_vbt((const char *) ptr + oh->vbt_offset); + + if (oh->vbt_offset > (fo->size - sizeof(struct vbt_header))) { + printerr("invalid VBT offset\n"); + return; + } + + head = (const struct vbt_header *)fo->data; + if (memcmp(head->signature, "$VBT", 4) == 0) { + parse_vbt(fo, vbt); + if (*vbt) + return; + } + + printwarn("VBT wasn't found at specified offset\n"); + + for (i = sizeof(optionrom_header_t); + i <= fo->size - sizeof(struct vbt_header); i++) { + struct fileobject *fo_vbt = malloc_fo_sub(fo, i); + if (!fo_vbt) + continue; + + head = (const struct vbt_header *)fo_vbt->data; + if (memcmp(head->signature, "$VBT", 4) == 0) + parse_vbt(fo_vbt, vbt); + + free_fo(fo_vbt); + + if (*vbt) + return; + } +} + +/* Short VBT summary in human readable form */ +static void print_vbt(const struct fileobject *fo) +{ + const struct bdb_header *bdb; + + if (fo->size < sizeof(struct vbt_header)) + return; + + const struct vbt_header *head = (const struct vbt_header *)fo->data; + + print("Found VBT:\n"); + printt("signature: <%20.20s>\n", head->signature); + printt("version: %d.%02d\n", head->version / 100, head->version % 100); + if (head->header_size != sizeof(struct vbt_header)) + printt("header size: 0x%x\n", head->header_size); + printt("VBT size: 0x%x\n", head->vbt_size); + printt("VBT checksum: 0x%x\n", head->vbt_checksum); + + if (head->bdb_offset > (fo->size - sizeof(struct bdb_header))) { + printerr("invalid BDB offset\n"); + return; + } + bdb = (const struct bdb_header *) + ((const char *)head + head->bdb_offset); + + if (memcmp("BIOS_DATA_BLOCK ", bdb->signature, 16) != 0) { + printerr("invalid BDB signature:%s\n", bdb->signature); + return; + } + printt("BDB version: %u.%02u\n", bdb->version / 100, + bdb->version % 100); +} + +static void print_usage(const char *argv0, struct option *long_options) +{ + size_t i = 0; + printf("\nUsage:\n"); + printf("%s --<SOURCECMD> [filename] --<DESTCMD> [filename]\n\n", argv0); + printf("SOURCECMD set the VBT source. Supported:\n"); + printf(" %-10s: Legacy BIOS area at phys. memory 0xc0000\n", + "inlegacy"); + printf(" %-10s: Read raw Intel VBT file\n", "invbt"); + printf(" %-10s: Read VBT from Intel Option ROM file\n\n", "inoprom"); + printf("DESTCMD set the VBT destination. Supported:\n"); + printf(" %-10s: Print VBT in human readable form\n", "outdump"); + printf(" %-10s: Write raw Intel VBT file\n", "outvbt"); + printf(" %-10s: Patch existing Intel Option ROM\n\n", "patchoprom"); + + printf("Supported arguments:\n"); + while (long_options[i].name) { + printf("\t-%c --%s %s\n", long_options[i].val, + long_options[i].name, long_options[i].has_arg ? + "<path>" : ""); + i++; + }; +} + +/* Open a VBIOS file, calculate the checksum and fix it */ +static int fix_vbios_checksum(const char *filename) +{ + struct fileobject *fo = read_file(filename); + if (!fo) { + printerr("%s open failed\n", filename); + return 1; + } + + if (fo->size < sizeof(optionrom_header_t)) + return 1; + + optionrom_header_t *oh = (optionrom_header_t *)fo->data; + + if (oh->size * 512 > fo->size) + return 1; + + /* fix checksum */ + oh->checksum = -(checksum_vbios(oh) - oh->checksum); + + if (write_file(filename, fo)) { + printerr("%s write failed\n", filename); + free_fo(fo); + return 1; + } + free_fo(fo); + + return 0; +} + +/* Return the VBT structure size in bytes */ +static size_t vbt_size(const struct fileobject *fo) +{ + if (!fo || fo->size < sizeof(struct vbt_header)) + return 0; + const struct vbt_header *head = (const struct vbt_header *)fo->data; + + return head->vbt_size; +} + +/* + * Patch an Intel Option ROM with new VBT. + * Caller has to make sure that VBIOS and VBT are valid. + * Return 1 on error. + */ +static int patch_vbios(struct fileobject *fo, + const struct fileobject *fo_vbt) +{ + optionrom_header_t *oh = (optionrom_header_t *)fo->data; + struct vbt_header *head; + + struct fileobject *old_vbt = NULL; + parse_vbios(fo, &old_vbt); + + if (old_vbt) { + if (oh->vbt_offset + vbt_size(old_vbt) == fo->size) { + /* Located at the end of file - reduce file size */ + if (fo->size < vbt_size(old_vbt)) + return 1; + fo = remalloc_fo(fo, fo->size - vbt_size(old_vbt)); + if (!fo) { + printerr("Failed to allocate memory\n"); + return 1; + } + oh->vbt_offset = 0; + } else if (vbt_size(old_vbt) < vbt_size(fo_vbt)) { + /* In the middle of the file - Remove old VBT */ + memset(fo->data + oh->vbt_offset, 0xff, + vbt_size(old_vbt)); + oh->vbt_offset = 0; + } else { + /* New VBT overwrites existing one - Clear memory */ + memset(fo->data + oh->vbt_offset, 0xff, + vbt_size(old_vbt)); + } + + free_fo(old_vbt); + } + + if (!oh->vbt_offset) { + print("increasing VBIOS to append VBT\n"); + if ((fo->size + vbt_size(fo_vbt)) >= 64 * KiB) { + printerr("VBT won't fit\n"); + return 1; + } + + oh->vbt_offset = fo->size; + fo = remalloc_fo(fo, fo->size + vbt_size(fo_vbt)); + if (!fo) { + printerr("Failed to allocate memory\n"); + return 1; + } + oh->size = (fo->size + 512 - 1) / 512; + } + + head = (struct vbt_header *)((u8 *)oh + oh->vbt_offset); + memcpy(head, fo_vbt->data, vbt_size(fo_vbt)); + + return 0; } int main(int argc, char **argv) { - const void *ptr; - int fd; - off_t offset; - if (argc == 2) { - fd = open(argv[1], O_RDONLY); - offset = 0; - } else { - fd = open("/dev/mem", O_RDONLY); - offset = 0xc0000; + int opt, option_index = 0; + + size_t has_input = 0, has_output = 0; + size_t dump = 0, in_legacy = 0; + char *in_vbt = NULL, *in_oprom = NULL; + char *out_vbt = NULL, *patch_oprom = NULL; + static struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"outdump", 0, 0, 'd'}, + {"inlegacy", 0, 0, 'l'}, + {"invbt", required_argument, 0, 'f'}, + {"inoprom", required_argument, 0, 'o'}, + {"outvbt", required_argument, 0, 'v'}, + {"patchoprom", required_argument, 0, 'p'}, + {0, 0, 0, 0} + }; + + while ((opt = getopt_long(argc, argv, "hdlf:o:v:p:i", + long_options, &option_index)) != EOF) { + switch (opt) { + case 'd': + dump = 1; + has_output = 1; + break; + case 'l': + in_legacy = 1; + has_input = 1; + break; + case 'f': + in_vbt = strdup(optarg); + has_input = 1; + break; + case 'o': + in_oprom = strdup(optarg); + has_input = 1; + break; + case 'v': + out_vbt = strdup(optarg); + has_output = 1; + break; + case 'p': + patch_oprom = strdup(optarg); + has_output = 1; + break; + case '?': + case 'h': + print_usage(argv[0], long_options); + exit(0); + break; + } } - if (fd < 0) { - fprintf(stderr, "open failed: %s\n", strerror(errno)); + + if (!has_input) + printerr("No input specified !\n"); + if (!has_output) + printerr("No output specified !\n"); + if (argc < 2 || argc > 6 || !has_input || !has_output) { + print_usage(argv[0], long_options); return 1; } - ptr = mmap(0, 65536, PROT_READ, MAP_SHARED, fd, offset); - if (ptr == MAP_FAILED) { - fprintf(stderr, "mmap failed: %s\n", strerror(errno)); + struct fileobject *fo; + + if (in_legacy) + fo = read_physmem(0xc0000); + else if (in_vbt) + fo = read_file(in_vbt); + else + fo = read_file(in_oprom); + + if (!fo) { + printerr("Failed to read input file\n"); return 1; } - parse_vbios(ptr); - close(fd); + + struct fileobject *vbt = NULL; + if (in_legacy || in_oprom) { + if (!is_valid_vbios(fo)) { + printerr("Invalid input file\n"); + + free_fo(fo); + return 1; + } + parse_vbios(fo, &vbt); + } else + parse_vbt(fo, &vbt); + + free_fo(fo); + + if (!vbt) { + printerr("Failed to find VBT.\n"); + return 1; + } + + if (!dump) + print_vbt(vbt); + + if (dump) { + dump_vbt(vbt); + } else if (out_vbt) { + if (write_file(out_vbt, vbt)) + printerr("Failed to write VBT\n"); + else + print("VBT written to %s\n", out_vbt); + } else if (patch_oprom) { + fo = read_file(patch_oprom); + if (!fo) { + printerr("Failed to read input file\n"); + return 1; + } + if (!is_valid_vbios(fo)) { + printerr("Invalid input file\n"); + free_fo(fo); + return 1; + } + if (patch_vbios(fo, vbt)) { + printerr("Failed to patch VBIOS\n"); + free_fo(fo); + return 1; + } + if (write_file(patch_oprom, fo)) { + printerr("Failed to write VBIOS\n"); + free_fo(fo); + return 1; + } + free_fo(fo); + if (fix_vbios_checksum(patch_oprom)) { + printerr("Failed to fix checksum\n"); + return 1; + } + print("VBIOS %s successfully patched\n", patch_oprom); + } + + /* cleanup */ + if (patch_oprom) + free(patch_oprom); + if (out_vbt) + free(out_vbt); + if (in_vbt) + free(in_vbt); + if (in_oprom) + free(in_oprom); + + free_fo(vbt); + return 0; } -- To view, visit https://review.coreboot.org/18902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76 Gerrit-Change-Number: 18902 Gerrit-PatchSet: 17 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: util/intelvbttool: Rewrite tool
by Philipp Deppenwiese (Code Review) 07 Oct '18

07 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/18902 ) Change subject: util/intelvbttool: Rewrite tool ...................................................................... Patch Set 16: Code-Review+2 -- To view, visit https://review.coreboot.org/18902 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8cbde042c7f5632f36648419becd23e248ba6f76 Gerrit-Change-Number: 18902 Gerrit-PatchSet: 16 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Samuel Holland <samuel(a)sholland.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 08 Oct 2018 02:32:43 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src: Standardize PCI_DEV(0, 0x1f, 0) name
by Martin Roth (Code Review) 07 Oct '18

07 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/28956 ) Change subject: src: Standardize PCI_DEV(0, 0x1f, 0) name ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/#/c/28956/5/src/southbridge/intel/bd82x6x/pch.h File src/southbridge/intel/bd82x6x/pch.h: https://review.coreboot.org/#/c/28956/5/src/southbridge/intel/bd82x6x/pch.h… PS5, Line 133: LPC_DEV PCI_DEV(0, 0x1f, 0) But now this doesn't match all of the other #defines for the platform. We have the same issue on many other platforms. I appreciate the effort, but I'm not positive it makes sense to try to standardize it across all platforms. Are we going to standardize all of the others as well? -- To view, visit https://review.coreboot.org/28956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0be00e5e9c733bbeb863250bd51eea8d33f54300 Gerrit-Change-Number: 28956 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martinroth(a)google.com> Gerrit-Comment-Date: Sun, 07 Oct 2018 20:12:40 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: util/superiotool/smsc.c: Add SCH5504 register dump
by Angel Pons (Code Review) 07 Oct '18

07 Oct '18

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28958 Change subject: util/superiotool/smsc.c: Add SCH5504 register dump ...................................................................... util/superiotool/smsc.c: Add SCH5504 register dump There is no datasheet available for this SuperIO, but dumping all possible registers on a Dell Optiplex GX520 resulted in data that was similar to other supported chips. Data also matches what is set in the BIOS, e.g. the parallel and serial ports' addresses. Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M util/superiotool/smsc.c 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/28958/1 diff --git a/util/superiotool/smsc.c b/util/superiotool/smsc.c index 21763ec..2ec6c0e 100644 --- a/util/superiotool/smsc.c +++ b/util/superiotool/smsc.c @@ -715,7 +715,32 @@ {0x30,0x60,0x61,0x62,0x63,0xf0,0xf1,0xf2,EOT}, {0x00,0x00,0x00,0x00,0x00,NANA,RSVD,0x04,EOT}}, {EOT}}}, - {0x79, "SCH5504", { /* From sensors-detect (no datasheet) */ + {0x79, "SCH5504", { /* No datasheet, reverse-engineered */ + {NOLDN, NULL, /* FIXME: Is this correct? */ + {0x02,0x03,0x21,0x22,0x23,0x24,0x26,0x27, + 0x28,0x2a,0x2b,0x2c,0x2d,0x2e,0x2f,EOT}, + {0x00,RSVD,MISC,0x00,0x00,0x04,MISC,0x00, + RSVD,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,0x00,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,0xf2,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x02,0x03,EOT}}, + {0x7, "Keyboard", + {0x30,0x70,0x72,0xf0,EOT}, + {0x00,0x00,0x00,0x00,EOT}}, + {0xa, "Runtime registers", /* FIXME: Is this correct? */ + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x00,RSVD,EOT}}, {EOT}}}, {0x7a, "LPC47N217", { /* Found in Toshiba Satellite A80-117. */ {NOLDN, NULL, -- To view, visit https://review.coreboot.org/28958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I768e4b5ec1e73c53e1a2355e0a0657b7a5ccbb89 Gerrit-Change-Number: 28958 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com>

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Change in coreboot[master]: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"
by Elyes HAOUAS (Code Review) 07 Oct '18

07 Oct '18

Hello build bot (Jenkins), Patrick Georgi, I'd like you to reexamine a change. Please visit https://review.coreboot.org/28957 to look at the new patch set (#2). Change subject: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)" ...................................................................... src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)" Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/google/stout/chromeos.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c 24 files changed, 200 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28957/2 -- To view, visit https://review.coreboot.org/28957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 Gerrit-Change-Number: 28957 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"
by Elyes HAOUAS (Code Review) 07 Oct '18

07 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/28957 Change subject: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)" ...................................................................... src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)" Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbook21/romstage.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/asus/p5gc-mx/romstage.c M src/mainboard/foxconn/d41s/romstage.c M src/mainboard/getac/p470/romstage.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/google/stout/chromeos.c M src/mainboard/ibase/mb899/romstage.c M src/mainboard/intel/d510mo/romstage.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dcp847ske/early_southbridge.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t60/romstage.c M src/mainboard/lenovo/x201/romstage.c M src/mainboard/lenovo/x60/romstage.c M src/mainboard/lenovo/z61t/romstage.c M src/mainboard/packardbell/ms2290/romstage.c M src/mainboard/packardbell/ms2290/smihandler.c M src/mainboard/roda/rk886ex/romstage.c M src/mainboard/sapphire/pureplatinumh61/romstage.c 24 files changed, 200 insertions(+), 164 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/28957/1 diff --git a/src/mainboard/apple/macbook21/romstage.c b/src/mainboard/apple/macbook21/romstage.c index ee322ae..3d76f56 100644 --- a/src/mainboard/apple/macbook21/romstage.c +++ b/src/mainboard/apple/macbook21/romstage.c @@ -33,10 +33,12 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* I/O Decode Ranges * X60: 0x0210 == 00000010 00010000 @@ -46,7 +48,7 @@ * 00 = 378h - 37Fh and 778h - 77Fh * 10 = 3BCh - 3BEh and 7BCh - 7BEh */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* LPC_EN--LPC I/F Enables Register * X60: 0x1f0d == 00011111 00001101 @@ -100,7 +102,7 @@ * interface. This range is selected in the LPC_COM Decode * Range Register (D31:F0:80h, bits 3:2). */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); @@ -126,19 +128,19 @@ * 1 = Enable the GEN1 I/O range to be forwarded to the LPC * I/F */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0681); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0681); /* GEN2_DEC, LPC Interface Generic Decode Range 2 * X60: 0x15e1 0x000c == 00000000 00001100 00010101 11100001 * Macbook21: 0x1641 0x000c == 00000000 00001100 00010110 01000001 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c1641); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c1641); /* GEN4_DEC, LPC Interface Generic Decode Range 4 * X60: 0x0000 0x0000 * Macbook21: 0x0301 0x001c == 00000000 00011100 00000011 00000001 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x001c0301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x001c0301); } static void rcba_config(void) @@ -188,14 +190,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/apple/macbookair4_2/early_southbridge.c b/src/mainboard/apple/macbookair4_2/early_southbridge.c index d189ae2..51fcb55 100644 --- a/src/mainboard/apple/macbookair4_2/early_southbridge.c +++ b/src/mainboard/apple/macbookair4_2/early_southbridge.c @@ -23,15 +23,17 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <cbfs.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0681); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c1641); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x001c0301); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00fc0701); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); + pci_write_config16(LPC_DEV, 0x82, 0x3f0f); + pci_write_config32(LPC_DEV, 0x84, 0x000c0681); + pci_write_config32(LPC_DEV, 0x88, 0x000c1641); + pci_write_config32(LPC_DEV, 0x8c, 0x001c0301); + pci_write_config32(LPC_DEV, 0x90, 0x00fc0701); + pci_write_config16(LPC_DEV, 0x80, 0x0070); + pci_write_config32(LPC_DEV, 0xac, 0x80000000); } void mainboard_rcba_config(void) diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index 90df5390..7c75bba 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -77,11 +77,11 @@ static void ich7_enable_lpc(void) { - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0291); } void mainboard_romstage_entry(unsigned long bist) diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c index dacc396..783df6b 100644 --- a/src/mainboard/asus/p5gc-mx/romstage.c +++ b/src/mainboard/asus/p5gc-mx/romstage.c @@ -39,6 +39,7 @@ #include <cpu/intel/speedstep.h> #include <arch/cpu.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) @@ -105,15 +106,15 @@ static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00040291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00040291); } static void rcba_config(void) @@ -138,14 +139,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/foxconn/d41s/romstage.c b/src/mainboard/foxconn/d41s/romstage.c index 3f81e67..871a331 100644 --- a/src/mainboard/foxconn/d41s/romstage.c +++ b/src/mainboard/foxconn/d41s/romstage.c @@ -36,6 +36,7 @@ #include <romstage_handoff.h> #include <timestamp.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8721F_SP1) /* Early mainboard specific GPIO setup */ @@ -56,16 +57,16 @@ static void nm10_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + pci_write_config16(LPC_DEV, LPC_IO_DEC, + pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); /* Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); } static void rcba_config(void) diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 7498247..71f2df1 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -33,6 +33,8 @@ #include <timestamp.h> #include "option_table.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void setup_special_ich7_gpios(void) { u32 gpios; @@ -60,19 +62,19 @@ lpt_en = LPT_LPC_EN; // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN| lpt_en | COMB_LPC_EN | COMA_LPC_EN); // Enable 0x02e0 - 0x2ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x001c02e1); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x001c02e1); // Enable 0x600 - 0x6ff - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601); // Enable 0x68 - 0x6f - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -192,14 +194,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c index 49a25af..4790e9e 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c @@ -34,6 +34,7 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) @@ -66,17 +67,17 @@ static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0000); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0000); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0801); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x000c0801); /* LPC decode range 2: Environment Controller */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00040291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00040291); } static void rcba_config(void) @@ -100,14 +101,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 13c888e..997c74b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -32,6 +32,7 @@ #include <northbridge/intel/x4x/iomap.h> #include <timestamp.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) #define EC_DEV PNP_DEV(0x2e, IT8718F_EC) @@ -118,14 +119,14 @@ static void ich7_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x007c0291); } void mainboard_romstage_entry(unsigned long bist) diff --git a/src/mainboard/google/stout/chromeos.c b/src/mainboard/google/stout/chromeos.c index 6d77a2a..d9e9b59 100644 --- a/src/mainboard/google/stout/chromeos.c +++ b/src/mainboard/google/stout/chromeos.c @@ -26,6 +26,8 @@ #include "ec.h" #include <ec/quanta/it8518/ec.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + #ifndef __PRE_RAM__ #include <boot/coreboot_tables.h> @@ -97,7 +99,7 @@ int get_recovery_mode_switch(void) { #ifdef __PRE_RAM__ - pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = LPC_DEV; #else static int ec_in_rec_mode = 0; static int ec_rec_flag_good = 0; diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 78ec5ed..84dc356 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -31,23 +31,24 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1/COM2/KBD/SuperIO1+2 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); // Enable HWM at 0x290 - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0291); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0291); // io 0x300 decode - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301); } /* This box has one superio @@ -155,14 +156,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index 77384ee..00c5cb8 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -35,6 +35,7 @@ #include <romstage_handoff.h> #include <timestamp.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #define SUPERIO_DEV PNP_DEV(0x4e, 0) @@ -57,15 +58,15 @@ static void nm10_enable_lpc(void) { /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0x00); /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, - pci_read_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC) | 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_IO_DEC, + pci_read_config16(LPC_DEV, LPC_IO_DEC) | 0x0010); + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x7c0291); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x7c0291); } static void rcba_config(void) diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 57f32c2..9f09391 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -29,20 +29,21 @@ #include <northbridge/intel/i945/raminit.h> #include <southbridge/intel/i82801gx/i82801gx.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1) #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME) static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // Set COM1/COM2 decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); // Enable COM1 - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | KBC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); // Enable SuperIO Power Management Events - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c0681); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c0681); } static void rcba_config(void) @@ -80,14 +81,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index c4be4d50..5c18135 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -33,12 +33,14 @@ #define DEBUG_UART_EN COMA_LPC_EN #endif +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | DEBUG_UART_EN); /* Decode SuperIO 0x0a00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, 0x00fc0a01); } void mainboard_rcba_config(void) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 467606a..6b0ec5b 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -33,6 +33,7 @@ #include "option_table.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void ich7_enable_lpc(void) @@ -42,21 +43,21 @@ lpt_en = LPT_LPC_EN; /* enable LPT */ /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* Set COM1/COM2 decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0010); /* Enable COM1/COM2/KBD/SuperIO1+2 */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN | COMB_LPC_EN | lpt_en); /* Enable HWM at 0xa00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x00fc0a01); /* COM3 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000403e9); /* COM4 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x000402e9); /* io 0x300 decode */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); + pci_write_config32(LPC_DEV, GEN4_DEC, 0x00000301); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -245,14 +246,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 0f6ffed..cd0bb08 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -23,13 +23,15 @@ #include <southbridge/intel/bd82x6x/pch.h> #include <southbridge/intel/common/gpio.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0c); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); + pci_write_config16(LPC_DEV, 0x82, 0x3c0c); + pci_write_config32(LPC_DEV, 0x84, 0x007c1611); + pci_write_config32(LPC_DEV, 0x88, 0x00040069); + pci_write_config32(LPC_DEV, 0x8c, 0x000c0701); + pci_write_config32(LPC_DEV, 0x90, 0x00000000); } void mainboard_rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 7e002d4..0e6df78 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -28,22 +28,23 @@ #include <southbridge/intel/common/gpio.h> #include "ec.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SPD_LEN 256 void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x0c00); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); + pci_write_config16(LPC_DEV, 0x82, 0x0c00); + pci_write_config32(LPC_DEV, 0x84, 0x00000000); + pci_write_config32(LPC_DEV, 0x88, 0x000c0701); + pci_write_config32(LPC_DEV, 0x8c, 0x000c0069); + pci_write_config32(LPC_DEV, 0x90, 0x000c06a1); + pci_write_config32(LPC_DEV, ETR3, 0x10000); /* Memory map KB9012 EC registers */ pci_write_config32( - PCI_DEV(0, 0x1f, 0), 0x98, + LPC_DEV, 0x98, CONFIG_EC_BASE_ADDRESS | 1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xd8, 0xffc0); + pci_write_config16(LPC_DEV, 0xd8, 0xffc0); /* Enable external USB port power. */ if (IS_ENABLED(CONFIG_USBDEBUG)) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index e4a8efb..a52ea6d 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -36,25 +36,27 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601); /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1); /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -120,14 +122,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -181,9 +183,9 @@ ich7_enable_lpc(); /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map); dock_err = dlpc_init(); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index d241422..66dee90 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -43,6 +43,8 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void pch_enable_lpc(void) { /* X201 EC Decode Range Port60/64, Port62/66 */ @@ -215,7 +217,7 @@ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(LPC_DEV, 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 81ee5da..9b86b4f 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -36,24 +36,26 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN | MC_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601); /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1); /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -119,14 +121,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -177,8 +179,8 @@ enable_lapic(); /* Enable GPIOs */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c, 0x10); /* 0x4c == GC */ + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config8(LPC_DEV, 0x4c, 0x10); /* 0x4c == GC */ setup_pch_gpios(&mainboard_gpio_map); ich7_enable_lpc(); diff --git a/src/mainboard/lenovo/z61t/romstage.c b/src/mainboard/lenovo/z61t/romstage.c index 94c8a8f..59afc7f 100644 --- a/src/mainboard/lenovo/z61t/romstage.c +++ b/src/mainboard/lenovo/z61t/romstage.c @@ -36,25 +36,27 @@ #include <southbridge/intel/common/gpio.h> #include "dock.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { // Enable Serial IRQ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0210); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0210); // decode range - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMA_LPC_EN); /* range 0x1600 - 0x167f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x007c1601); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x007c1601); /* range 0x15e0 - 0x15ef */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000c15e1); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x000c15e1); /* range 0x1680 - 0x169f */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x001c1681); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x001c1681); } static void early_superio_config(void) @@ -120,14 +122,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); // reset rtc power status - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); // usb transient disconnect - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); @@ -181,9 +183,9 @@ ich7_enable_lpc(); /* We want early GPIO setup, to be able to detect legacy I/O module */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIOBASE, DEFAULT_GPIOBASE | 1); + pci_write_config32(LPC_DEV, GPIOBASE, DEFAULT_GPIOBASE | 1); /* Enable GPIOs */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x4c /* GC */ , 0x10); + pci_write_config8(LPC_DEV, 0x4c /* GC */, 0x10); setup_pch_gpios(&mainboard_gpio_map); dock_err = dlpc_init(); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index adb0cec..2507c8b 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -41,6 +41,8 @@ #include <northbridge/intel/nehalem/raminit.h> #include <southbridge/intel/ibexpeak/me.h> +#define LPC_DEV LPC_DEV + static void pch_enable_lpc(void) { /* Enable EC, PS/2 Keyboard/Mouse */ @@ -214,7 +216,7 @@ printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { u8 reg8; - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + reg8 = pci_read_config8(LPC_DEV, 0xa2); printk(BIOS_DEBUG, "a2: %02x\n", reg8); if (!(reg8 & 0x20)) { outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); diff --git a/src/mainboard/packardbell/ms2290/smihandler.c b/src/mainboard/packardbell/ms2290/smihandler.c index 926650a..7b3e9d6 100644 --- a/src/mainboard/packardbell/ms2290/smihandler.c +++ b/src/mainboard/packardbell/ms2290/smihandler.c @@ -24,6 +24,8 @@ #include <ec/acpi/ec.h> #include <delay.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void mainboard_smm_init(void) { printk(BIOS_DEBUG, "initializing SMI\n"); @@ -74,16 +76,16 @@ mainboard_finalized = 1; break; case APM_CNT_ACPI_ENABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp = pci_read_config8(LPC_DEV, 0xbb); tmp &= ~0x03; tmp |= 0x02; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + pci_write_config8(LPC_DEV, 0xbb, tmp); break; case APM_CNT_ACPI_DISABLE: - tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp = pci_read_config8(LPC_DEV, 0xbb); tmp &= ~0x03; tmp |= 0x01; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + pci_write_config8(LPC_DEV, 0xbb, tmp); break; default: break; diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index 7f233e8..b921382 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -35,6 +35,8 @@ #include <southbridge/intel/i82801gx/i82801gx.h> #include "option_table.h" +#define LPC_DEV PCI_DEV(0, 0x1f, 0) + static void ich7_enable_lpc(void) { int lpt_en = 0; @@ -42,19 +44,19 @@ lpt_en = LPT_LPC_EN; /* enable LPT */ /* Enable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); + pci_write_config8(LPC_DEV, SERIRQ_CNTL, 0xd0); /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007); + pci_write_config16(LPC_DEV, LPC_IO_DEC, 0x0007); /* decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + pci_write_config16(LPC_DEV, LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN | GAMEL_LPC_EN | FDD_LPC_EN | lpt_en | COMB_LPC_EN | COMA_LPC_EN); /* COM3 and COM4 decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x1c02e1); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x1c02e1); /* ??decode?? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x00fc0601); + pci_write_config32(LPC_DEV, GEN2_DEC, 0x00fc0601); /* EC decode? */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x00040069); + pci_write_config32(LPC_DEV, GEN3_DEC, 0x00040069); } /* This box has two superios, so enabling serial becomes slightly excessive. @@ -158,14 +160,14 @@ pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); /* reset rtc power status */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); + reg8 = pci_read_config8(LPC_DEV, 0xa4); reg8 &= ~(1 << 2); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); + pci_write_config8(LPC_DEV, 0xa4, reg8); /* usb transient disconnect */ - reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); + reg8 = pci_read_config8(LPC_DEV, 0xad); reg8 |= (3 << 0); - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); + pci_write_config8(LPC_DEV, 0xad, reg8); reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); reg32 |= (1 << 29) | (1 << 17); diff --git a/src/mainboard/sapphire/pureplatinumh61/romstage.c b/src/mainboard/sapphire/pureplatinumh61/romstage.c index da825a9..cdc5993 100644 --- a/src/mainboard/sapphire/pureplatinumh61/romstage.c +++ b/src/mainboard/sapphire/pureplatinumh61/romstage.c @@ -25,16 +25,17 @@ #include <northbridge/intel/sandybridge/raminit_native.h> #include <southbridge/intel/bd82x6x/pch.h> +#define LPC_DEV PCI_DEV(0, 0x1f, 0) void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x000c0291); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0a01); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00000000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); + pci_write_config16(LPC_DEV, 0x82, 0x2400); + pci_write_config32(LPC_DEV, 0x84, 0x000c0291); + pci_write_config32(LPC_DEV, 0x88, 0x000c0a01); + pci_write_config32(LPC_DEV, 0x8c, 0x00000000); + pci_write_config32(LPC_DEV, 0x90, 0x00000000); + pci_write_config16(LPC_DEV, 0x80, 0x0000); + pci_write_config32(LPC_DEV, 0xac, 0x00010000); } void mainboard_rcba_config(void) -- To view, visit https://review.coreboot.org/28957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e340d42cc9498740fa7158f76472e26b5509695 Gerrit-Change-Number: 28957 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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coreboot-gerrit October 2018