Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/28966 )
Change subject: Documentation: Improve elgon documentation
......................................................................
Patch Set 2: Code-Review+2
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Gerrit-Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28965
to look at the new patch set (#3).
Change subject: mb/google/fizz: Provide nhlt variant API
......................................................................
mb/google/fizz: Provide nhlt variant API
Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/fizz/mainboard.c
M src/mainboard/google/fizz/variants/baseboard/Makefile.inc
M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/fizz/variants/baseboard/nhlt.c
4 files changed, 48 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28965/3
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Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/28966
Change subject: Documentation: Improve elgon documentation
......................................................................
Documentation: Improve elgon documentation
* Mark flash IC and USB serial connector.
* Mark SPI programming header.
* Add programming header pinout.
Change-Id: Ica5958545ed23573a0d48dfa422ad1a822d06b47
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M Documentation/mainboard/opencellular/elgon.md
M Documentation/mainboard/opencellular/elgon2.png
A Documentation/mainboard/opencellular/elgon_conn_j9.png
A Documentation/mainboard/opencellular/elgon_conn_j9_pcb.png
4 files changed, 16 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/28966/1
diff --git a/Documentation/mainboard/opencellular/elgon.md b/Documentation/mainboard/opencellular/elgon.md
index 37d05e6..aac2d16 100644
--- a/Documentation/mainboard/opencellular/elgon.md
+++ b/Documentation/mainboard/opencellular/elgon.md
@@ -40,21 +40,33 @@
The EVT board does have a pinheader to flash the SOIC-8 in circuit.
Directly connecting a Pomona test-clip on the flash is also possible.
-TODO: pinout
-
**Total board view of EVT**
![][elgon1]
[elgon1]: elgon1.png
-**Closeup view of SOIC-8 flash IC, programming pin header and
-USB serial connector of EVT**
+**Closeup view of SOIC-8 flash IC and USB serial connector of EVT (marked blue)**
![][elgon2]
[elgon2]: elgon2.png
+
+**SPI header (marked blue)**
+
+![][elgon_conn_j9_pcb]
+
+[elgon_conn_j9_pcb]: elgon_conn_j9_pcb.png
+
+**SPI header pinout**
+
+Dediprog compatible pinout.
+
+![][elgon_conn_j9]
+
+[elgon_conn_j9]: elgon_conn_j9.png
+
## Technology
```eval_rst
diff --git a/Documentation/mainboard/opencellular/elgon2.png b/Documentation/mainboard/opencellular/elgon2.png
index f12a734..dec6d96 100644
--- a/Documentation/mainboard/opencellular/elgon2.png
+++ b/Documentation/mainboard/opencellular/elgon2.png
Binary files differ
diff --git a/Documentation/mainboard/opencellular/elgon_conn_j9.png b/Documentation/mainboard/opencellular/elgon_conn_j9.png
new file mode 100644
index 0000000..345d616
--- /dev/null
+++ b/Documentation/mainboard/opencellular/elgon_conn_j9.png
Binary files differ
diff --git a/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.png b/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.png
new file mode 100644
index 0000000..19f13fa
--- /dev/null
+++ b/Documentation/mainboard/opencellular/elgon_conn_j9_pcb.png
Binary files differ
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/28950 )
Change subject: lenovo/x230: introduce FHD variant
......................................................................
Patch Set 3:
> I am trying to compile after a `make distclean` and noticed if
> building with an existing .config it will error complaining that
> data.vbt cannot be found.
Reusing a *complete* .config for an older coreboot revision is
always somehow fragile and discouraged. The best option you
have currently is to use `make savedefconfig` (with a checkout
of the older revision). It will create a `defconfig` file with
only those settings that differ from the defaults. Then use
this `defconfig` as your .config after switching to the new
revision. Note, this `defconfig` is also stored inside the
CBFS of your coreboot image.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/28957 )
Change subject: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"
......................................................................
Patch Set 2: Code-Review-1
I don't like number hiding macros. Well, in the case of LPC_DEV, most
people probably know that it's 0x1f. But some don't.
And for this device in particular, LPC ist just the historical name.
It has nothing to do with the functions actually configured.
I remember from the gm45/ich9 port that we used macros like D0F0,
D31F0 etc. That's a good trade-off, IMO, if you want to save some
line length.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28956 )
Change subject: src: Standardize PCI_DEV(0, 0x1f, 0) name
......................................................................
Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/28956/5/src/southbridge/intel/ibexpeak/pch.h
File src/southbridge/intel/ibexpeak/pch.h:
https://review.coreboot.org/#/c/28956/5/src/southbridge/intel/ibexpeak/pch.…
PS5, Line 110: #define LPC_DEV PCI_DEV(0, 0x1f, 0)
Should start with PCH_ as all other defines in this file
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28957 )
Change subject: src/mainboard: Use macro instead of "PCI_DEV(0, 0x1f, 0)"
......................................................................
Patch Set 2:
Please define it in a public southbridge header, instead of every file.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28965
to look at the new patch set (#2).
Change subject: mb/google/fizz: Provide nhlt variant API
......................................................................
mb/google/fizz: Provide nhlt variant API
Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/fizz/mainboard.c
M src/mainboard/google/fizz/variants/baseboard/Makefile.inc
M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h
A src/mainboard/google/fizz/variants/baseboard/nhlt.c
4 files changed, 47 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/28965/2
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Hello build bot (Jenkins),
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Change subject: mb/google/fizz: Provide cros_gpio variant API
......................................................................
mb/google/fizz: Provide cros_gpio variant API
Add support for ChromeOS GPIO ACPI table information by providing weak
implementation from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h
3 files changed, 18 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/28964/2
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: mb/google/fizz: Add variant API for gpio
......................................................................
mb/google/fizz: Add variant API for gpio
Provide API for gpio table functionality. Default weak
implementations are provided from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314
Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/fizz/bootblock.c
M src/mainboard/google/fizz/ramstage.c
A src/mainboard/google/fizz/variants/baseboard/Makefile.inc
A src/mainboard/google/fizz/variants/baseboard/gpio.c
M src/mainboard/google/fizz/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/google/fizz/variants/baseboard/include/baseboard/variants.h
6 files changed, 316 insertions(+), 248 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/28963/2
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