Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/28975 )
Change subject: soc/cavium: dynamic UART initialization for cavium cn8100
......................................................................
Patch Set 4: Code-Review+2
Tested on Cavium CN8100 SFF EVB. Still boots into linux and only shows configured UARTs.
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Gerrit-Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62
Gerrit-Change-Number: 28975
Gerrit-PatchSet: 4
Gerrit-Owner: Jens Drenhaus <jens.drenhaus(a)9elements.com>
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Gerrit-Comment-Date: Wed, 10 Oct 2018 07:23:10 +0000
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28984
to look at the new patch set (#2).
Change subject: mb/google/poppy/var/nocturne: Provide override for ec eventinfo
......................................................................
mb/google/poppy/var/nocturne: Provide override for ec eventinfo
This change implements the callback to provide google_chromeec_event_info
structure in nocturne variant and sets MKBP SCI based on board id.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/poppy/variants/nocturne/Makefile.inc
A src/mainboard/google/poppy/variants/nocturne/ec.c
M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h
3 files changed, 39 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28984/2
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Gerrit-Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323
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Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/28983 )
Change subject: mb/google/poppy: Allow variants to provide event info at runtime
......................................................................
mb/google/poppy: Allow variants to provide event info at runtime
This change adds a variant callback to read google_chromeec_event_info
from variant at runtime to allow override of any events based on
factors like board id.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/poppy/ec.c
M src/mainboard/google/poppy/variants/baseboard/include/baseboard/variants.h
2 files changed, 15 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/28983/2
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Gerrit-Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Gerrit-Change-Number: 28983
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PraveenX Hodagatta Pranesh has uploaded this change for review. ( https://review.coreboot.org/28985
Change subject: src/drivers/intel: Add coffee lake FSP CAR support
......................................................................
src/drivers/intel: Add coffee lake FSP CAR support
CPU_MICROCODE_CBFS_LEN and CPU_MICROCODE_CBFS_LOC configs passes the CPU
microcode length and base address in CBFS to FSPT binary as init parameters.
Add new config FSP_T_XIP in Kconfig, which is selected by platform config.
If FSP_T_XIP is selected, then relocate FSPT binary while adding it in CBFS
so that it can be executed in place.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successfull CAR setup.
Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.inc
2 files changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/28985/1
diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig
index 4c4dfb2..31556ee 100644
--- a/src/drivers/intel/fsp2_0/Kconfig
+++ b/src/drivers/intel/fsp2_0/Kconfig
@@ -53,6 +53,20 @@
Display the user specified product data prior to memory
initialization.
+config CPU_MICROCODE_CBFS_LEN
+ hex "Microcode update region length in bytes"
+ depends on FSP_CAR
+ default 0x0
+ help
+ The length in bytes of the microcode update region.
+
+config CPU_MICROCODE_CBFS_LOC
+ hex "Microcode update base address in CBFS"
+ depends on FSP_CAR
+ default 0x0
+ help
+ The location (base address) in CBFS that contains the microcode update binary.
+
config FSP_T_CBFS
string "Name of FSP-T in CBFS"
depends on FSP_CAR
@@ -97,6 +111,13 @@
help
Select this value when FSP-M is execute-in-place.
+config FSP_T_XIP
+ bool "Is FSP-T XIP"
+ depends on FSP_CAR
+ default n
+ help
+ Select this value when FSP-T is execute-in-place.
+
config FSP_USES_CB_STACK
bool
default n
diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc
index d5709ad..68200b0 100644
--- a/src/drivers/intel/fsp2_0/Makefile.inc
+++ b/src/drivers/intel/fsp2_0/Makefile.inc
@@ -52,6 +52,9 @@
cbfs-files-$(CONFIG_FSP_CAR) += $(CONFIG_FSP_T_CBFS)
$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE))
$(CONFIG_FSP_T_CBFS)-type := fsp
+ifeq ($(CONFIG_FSP_T_XIP),y)
+$(CONFIG_FSP_T_CBFS)-options := --xip
+endif
cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS)
$(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE))
--
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Gerrit-Change-Id: Ic46e0bb9ee13c38ff322979119c4813653c61029
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build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/28983 )
Change subject: mb/google/poppy: Allow variants to provide event info at runtime
......................................................................
Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/28983/1/src/mainboard/google/poppy/ec.c
File src/mainboard/google/poppy/ec.c:
https://review.coreboot.org/#/c/28983/1/src/mainboard/google/poppy/ec.c@37
PS1, Line 37: google_chromeec_events_init(variant_get_event_info(), acpi_is_wakeup_s3());
line over 80 characters
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Gerrit-Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Gerrit-Change-Number: 28983
Gerrit-PatchSet: 1
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Comment-Date: Wed, 10 Oct 2018 07:00:33 +0000
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Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/28984
Change subject: mb/google/poppy/var/nocturne: Provide override for ec eventinfo
......................................................................
mb/google/poppy/var/nocturne: Provide override for ec eventinfo
This change implements the callback to provide google_chromeec_event_info
structure in nocturne variant and sets MKBP SCI based on board id.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323
Signed-off-by: Furquan Shaikh <furquan(a)google.com>
---
M src/mainboard/google/poppy/variants/nocturne/Makefile.inc
A src/mainboard/google/poppy/variants/nocturne/ec.c
M src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h
3 files changed, 39 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/28984/1
diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc
index c17a49c..f202ef1 100644
--- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc
+++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc
@@ -20,3 +20,5 @@
ramstage-y += gpio.c
ramstage-y += nhlt.c
ramstage-y += mainboard.c
+
+smm-y += ec.c
diff --git a/src/mainboard/google/poppy/variants/nocturne/ec.c b/src/mainboard/google/poppy/variants/nocturne/ec.c
new file mode 100644
index 0000000..13c4a42
--- /dev/null
+++ b/src/mainboard/google/poppy/variants/nocturne/ec.c
@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/variants.h>
+#include <boardid.h>
+#include <ec/google/chromeec/ec.h>
+
+#include <variant/ec.h>
+
+const struct google_chromeec_event_info *variant_get_event_info(void)
+{
+ static struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ if (board_id() <= 2)
+ info.sci_events |= EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP);
+
+ return &info;
+}
diff --git a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h
index ba481e4..46e848b 100644
--- a/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h
+++ b/src/mainboard/google/poppy/variants/nocturne/include/variant/ec.h
@@ -34,7 +34,6 @@
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
- EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\
EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
#define MAINBOARD_EC_SMI_EVENTS \
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Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Hello Patrick Rudolph, Philipp Deppenwiese, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/28975
to look at the new patch set (#4).
Change subject: soc/cavium: dynamic UART initialization for cavium cn8100
......................................................................
soc/cavium: dynamic UART initialization for cavium cn8100
Now only those UARTs that are enabled in devicetree.cb are initialized.
Tested on Opencellular Elgon.
Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62
Signed-off-by: Jens Drenhaus <jens.drenhaus(a)9elements.com>
---
M src/mainboard/cavium/cn8100_sff_evb/mainboard.c
M src/mainboard/opencellular/elgon/mainboard.c
M src/soc/cavium/cn81xx/soc.c
3 files changed, 28 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/28975/4
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