Nico Huber has posted comments on this change. ( https://review.coreboot.org/29388 )
Change subject: sb/intel/lynxpoint: Deduplicate `acpi_fill_madt()`
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
https://review.coreboot.org/#/c/29388/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29388/1//COMMIT_MSG@11
PS1, Line 11: copied from sb/intel/bd82x6x
Maybe sb/intel/common/ is a better place for the things you copied
from bd82x6x? Many things actually didn't change from ICH7 to PCH9
(Wildcat Point), so this might apply to many more systems.
https://review.coreboot.org/#/c/29388/1/src/southbridge/intel/lynxpoint/mad…
File src/southbridge/intel/lynxpoint/madt.c:
https://review.coreboot.org/#/c/29388/1/src/southbridge/intel/lynxpoint/mad…
PS1, Line 16: #include <types.h>
: #include <string.h>
: #include <cbmem.h>
: #include <console/console.h>
: #include <arch/acpi.h>
: #include <arch/ioapic.h>
: #include <arch/acpigen.h>
: #include <arch/smp/mpspec.h>
That can't be all needed.
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/29383 )
Change subject: cpu/intel/haswell: Allow use of TSC for the monotonic timer
......................................................................
Patch Set 1: Code-Review+2
(1 comment)
https://review.coreboot.org/#/c/29383/1//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/29383/1//COMMIT_MSG@20
PS1, Line 20: only exists on
: Haswell-ULT CPUs
that is correct
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/29382 )
Change subject: sb/intel/lynxpoint: Provide a function for mainboard super I/O config
......................................................................
Patch Set 1: Code-Review+2
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/29393
to look at the new patch set (#2).
Change subject: src/soc/intel/braswell/include/soc/irq.h: Set bit 7 if PIRQ register to disable
......................................................................
src/soc/intel/braswell/include/soc/irq.h: Set bit 7 if PIRQ register to disable
PIRQ register is not set to disabled.
Set bit 7 of the PIRQ registers to disable the PIRQ
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com>
---
M src/soc/intel/braswell/include/soc/irq.h
1 file changed, 2 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29393/2
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/29379 )
Change subject: nb/intel/haswell: Add a PCI ID for a Mini-HD audio controller
......................................................................
Patch Set 1: Code-Review+2
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Gerrit-Comment-Date: Wed, 31 Oct 2018 13:34:27 +0000
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