coreboot-gerrit October 2018

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Change in coreboot[master]: northbridge/intel/fsp_*: Remove legacy SoCs
by Philipp Deppenwiese (Code Review) 31 Oct '18

31 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29402 Change subject: northbridge/intel/fsp_*: Remove legacy SoCs ...................................................................... northbridge/intel/fsp_*: Remove legacy SoCs * Remove FSP Sandy/Ivybrige which are unused. * Open Source implementation isn't final but good enough to replace FSP version. * For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE and NORTHBRIDGE_INTEL_SANDYBRIDGE Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Signed-off-by: zaolin <zaolin.daisuki(a)gmail.com> --- M src/cpu/intel/Makefile.inc D src/cpu/intel/fsp_model_206ax/Kconfig D src/cpu/intel/fsp_model_206ax/Makefile.inc D src/cpu/intel/fsp_model_206ax/acpi.c D src/cpu/intel/fsp_model_206ax/acpi/cpu.asl D src/cpu/intel/fsp_model_206ax/bootblock.c D src/cpu/intel/fsp_model_206ax/chip.h D src/cpu/intel/fsp_model_206ax/finalize.c D src/cpu/intel/fsp_model_206ax/model_206ax.h D src/cpu/intel/fsp_model_206ax/model_206ax_init.c D src/mainboard/intel/cougar_canyon2/Kconfig D src/mainboard/intel/cougar_canyon2/Kconfig.name D src/mainboard/intel/cougar_canyon2/acpi/ec.asl D src/mainboard/intel/cougar_canyon2/acpi/hostbridge_pci_irqs.asl D src/mainboard/intel/cougar_canyon2/acpi/mainboard.asl D src/mainboard/intel/cougar_canyon2/acpi/platform.asl D src/mainboard/intel/cougar_canyon2/acpi/superio.asl D src/mainboard/intel/cougar_canyon2/acpi_tables.c D src/mainboard/intel/cougar_canyon2/board_info.txt D src/mainboard/intel/cougar_canyon2/cmos.layout D src/mainboard/intel/cougar_canyon2/devicetree.cb D src/mainboard/intel/cougar_canyon2/dsdt.asl D src/mainboard/intel/cougar_canyon2/gpio.h D src/mainboard/intel/cougar_canyon2/hda_verb.c D src/mainboard/intel/cougar_canyon2/mainboard.c D src/mainboard/intel/cougar_canyon2/mainboard_smi.c D src/mainboard/intel/cougar_canyon2/romstage.c D src/mainboard/intel/cougar_canyon2/thermal.h D src/mainboard/intel/stargo2/Kconfig D src/mainboard/intel/stargo2/Kconfig.name D src/mainboard/intel/stargo2/acpi/ec.asl D src/mainboard/intel/stargo2/acpi/hostbridge_pci_irqs.asl D src/mainboard/intel/stargo2/acpi/mainboard.asl D src/mainboard/intel/stargo2/acpi/platform.asl D src/mainboard/intel/stargo2/acpi/superio.asl D src/mainboard/intel/stargo2/acpi_tables.c D src/mainboard/intel/stargo2/board_info.txt D src/mainboard/intel/stargo2/cmos.layout D src/mainboard/intel/stargo2/devicetree.cb D src/mainboard/intel/stargo2/dsdt.asl D src/mainboard/intel/stargo2/gpio.h D src/mainboard/intel/stargo2/mainboard.c D src/mainboard/intel/stargo2/mainboard_smi.c D src/mainboard/intel/stargo2/romstage.c D src/mainboard/intel/stargo2/thermal.h D src/northbridge/intel/fsp_sandybridge/Kconfig D src/northbridge/intel/fsp_sandybridge/Makefile.inc D src/northbridge/intel/fsp_sandybridge/acpi.c D src/northbridge/intel/fsp_sandybridge/acpi/hostbridge.asl D src/northbridge/intel/fsp_sandybridge/acpi/sandybridge.asl D src/northbridge/intel/fsp_sandybridge/bootblock.c D src/northbridge/intel/fsp_sandybridge/chip.h D src/northbridge/intel/fsp_sandybridge/early_init.c D src/northbridge/intel/fsp_sandybridge/finalize.c D src/northbridge/intel/fsp_sandybridge/fsp/Kconfig D src/northbridge/intel/fsp_sandybridge/fsp/Makefile.inc D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c D src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.h D src/northbridge/intel/fsp_sandybridge/gma.c D src/northbridge/intel/fsp_sandybridge/northbridge.c D src/northbridge/intel/fsp_sandybridge/northbridge.h D src/northbridge/intel/fsp_sandybridge/northbridge_pci_devs.h D src/northbridge/intel/fsp_sandybridge/ram_calc.c D src/northbridge/intel/fsp_sandybridge/raminit.c D src/northbridge/intel/fsp_sandybridge/raminit.h D src/northbridge/intel/fsp_sandybridge/report_platform.c M src/vendorcode/intel/Kconfig D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspapi.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspffs.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspfv.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsphob.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fspplatform.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/fsptypes.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/mem_config.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/include/peifsp.h D src/vendorcode/intel/fsp1_0/ivybridge_bd82x6x/srx/fsphob.c D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsp_vpd.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspapi.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspffs.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspfv.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsphob.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspinfoheader.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fspplatform.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/fsptypes.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/mem_config.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/include/peifsp.h D src/vendorcode/intel/fsp1_0/ivybridge_i89xx/srx/fsphob.c 88 files changed, 0 insertions(+), 9,572 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/29402/1 -- To view, visit https://review.coreboot.org/29402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e Gerrit-Change-Number: 29402 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: amd/mtrr: Fix IORR MTRR
by Richard Spiegel (Code Review) 31 Oct '18

31 Oct '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29352 ) Change subject: amd/mtrr: Fix IORR MTRR ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 15:37:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/icelake: Include path for FSP headers
by Subrata Banik (Code Review) 31 Oct '18

31 Oct '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29400 Change subject: soc/intel/icelake: Include path for FSP headers ...................................................................... soc/intel/icelake: Include path for FSP headers This patch includes Icelake specific FSP headers for coreboot build. Change-Id: I34ddf35740d44bd73adb877f194d3851c0d17acd Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/icelake/Makefile.inc 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/29400/1 diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index a81edd4..2a08401 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -74,6 +74,8 @@ verstage-y += spi.c verstage-$(CONFIG_UART_DEBUG) += uart.c +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/icelake + CPPFLAGS_common += -I$(src)/soc/intel/icelake CPPFLAGS_common += -I$(src)/soc/intel/icelake/include -- To view, visit https://review.coreboot.org/29400 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I34ddf35740d44bd73adb877f194d3851c0d17acd Gerrit-Change-Number: 29400 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Remove unused _STA method from cnvi.asl
by Subrata Banik (Code Review) 31 Oct '18

31 Oct '18

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/29399 Change subject: soc/intel/cannonlake: Remove unused _STA method from cnvi.asl ...................................................................... soc/intel/cannonlake: Remove unused _STA method from cnvi.asl Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/acpi/cnvi.asl 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/29399/1 diff --git a/src/soc/intel/cannonlake/acpi/cnvi.asl b/src/soc/intel/cannonlake/acpi/cnvi.asl index f9aeeb0..dd4f528 100644 --- a/src/soc/intel/cannonlake/acpi/cnvi.asl +++ b/src/soc/intel/cannonlake/acpi/cnvi.asl @@ -24,9 +24,4 @@ Name (_S3W, 3) /* D3 can wake system from S3 */ Name (_PRW, Package() { PME_B0_EN_BIT, 3 }) - - Method (_STA, 0) - { - Return (0xF) - } } -- To view, visit https://review.coreboot.org/29399 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118 Gerrit-Change-Number: 29399 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix get_cpu_count()
by Raul Rangel (Code Review) 31 Oct '18

31 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/29367 ) Change subject: soc/amd/stoneyridge: Fix get_cpu_count() ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Gerrit-Change-Number: 29367 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 15:13:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add ASRock H81M-HDS
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29390 to look at the new patch set (#3). Change subject: mainboard: Add ASRock H81M-HDS ...................................................................... mainboard: Add ASRock H81M-HDS Tested with GRUB 2.02 as a payload, booting Debian GNU/Linux 9.5 with kernel 4.9. This board works quite well under coreboot. A list of what works and what doesn't can be found in the documentation part of this commit. The file `data.vbt` matches the VBT in the latest stable version of the vendor firmware (version 2.20). Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- A Documentation/mainboard/asrock/h81m-hds.md M Documentation/mainboard/index.md A src/mainboard/asrock/h81m-hds/Kconfig A src/mainboard/asrock/h81m-hds/Kconfig.name A src/mainboard/asrock/h81m-hds/Makefile.inc A src/mainboard/asrock/h81m-hds/acpi/ec.asl A src/mainboard/asrock/h81m-hds/acpi/platform.asl A src/mainboard/asrock/h81m-hds/acpi/superio.asl A src/mainboard/asrock/h81m-hds/acpi_tables.c A src/mainboard/asrock/h81m-hds/board_info.txt A src/mainboard/asrock/h81m-hds/cmos.default A src/mainboard/asrock/h81m-hds/cmos.layout A src/mainboard/asrock/h81m-hds/data.vbt A src/mainboard/asrock/h81m-hds/devicetree.cb A src/mainboard/asrock/h81m-hds/dsdt.asl A src/mainboard/asrock/h81m-hds/gma-mainboard.ads A src/mainboard/asrock/h81m-hds/gpio.h A src/mainboard/asrock/h81m-hds/hda_verb.c A src/mainboard/asrock/h81m-hds/mainboard.c A src/mainboard/asrock/h81m-hds/romstage.c 20 files changed, 1,043 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/29390/3 -- To view, visit https://review.coreboot.org/29390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I53483bb9fa335e86e85dfc487fef03fce4b85e2a Gerrit-Change-Number: 29390 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29389 to look at the new patch set (#3). Change subject: sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors ...................................................................... sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors If the file `southbridge/intel/lynxpoint/nvs.h` is included in a file that does not already include <stdint.h>, compilation errors result. Adding the necessary <stdint.h> inclusions fixes compilation for an ASRock H81M-HDS. Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/nvs.h M src/vendorcode/google/chromeos/gnvs.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29389/3 -- To view, visit https://review.coreboot.org/29389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825 Gerrit-Change-Number: 29389 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/lynxpoint: Generate the ACPI FADT with a common function
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29387 to look at the new patch set (#3). Change subject: sb/intel/lynxpoint: Generate the ACPI FADT with a common function ...................................................................... sb/intel/lynxpoint: Generate the ACPI FADT with a common function The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x. Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux 4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel log. System reset, poweroff, and S3 suspend/resume continue to work. General improvements -------------------- - `fadt->preferred_pm_profile` is set based on the value of `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded. - Constants are used instead of magic values in more locations. - `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set appropriately depending on whether the system uses Lynx Point LP or not. - The C2 and C3 latencies can be set in the devicetree. If unset, the FADT will indicate that the C-state is unsupported. - Boards can indicate docking support in the FADT via the devicetree. Changes to existing Lynx Point boards ------------------------------------- - `header->asl_compiler_revision` changes from 1 to 0. - `fadt->model` is left at 0 instead of being set to 1. This field is only needed for ACPI 1.0 compatibility. - `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is because their values are ignored, since `ACPI_FADT_WBINVD` is set in `fadt->flags`. - `fadt->duty_offset` is set to 0 instead of 1. None of the existing boards indicate support for changing the processor duty cycle (as `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not currently need to be set. - Access sizes of registers are set. - On mb/intel/baskingridge, the pmbase is now read using the common function `get_pmbase()` instead of `pci_read_config16(...)`. - On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width` changes from 64 to 128. The correct value should be 128 (bits), to match `fadt->gpe0_blk_len`, which is set to 16 (bytes). - On Lynx Point LP systems, the unused extended address `fadt->x_gpe0_blk` sets its address space ID to be consistent with other unused extended addresses. Such a change should not alter the interpretation of the registers as being unused. Why not set them all to zero? Simply because the existing practice, in both coreboot and some other vendors' firmware, has them set in such a case. A diff of the FADT from a Google Peppy board is below: --- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300 +++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300 @@ -1,179 +1,179 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018 + * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : 61 +[009h 0009 1] Checksum : 6E [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" -[020h 0032 4] Asl Compiler Revision : 00000001 +[020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] FACS Address : 7BF46240 [028h 0040 4] DSDT Address : 7BF46280 -[02Ch 0044 1] Model : 01 +[02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 02 [Mobile] [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : E1 [035h 0053 1] ACPI Disable Value : 1E [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 [038h 0056 4] PM1A Event Block Address : 00001000 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00001004 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00001050 [04Ch 0076 4] PM Timer Block Address : 00001008 [050h 0080 4] GPE0 Block Address : 00001080 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 01 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 20 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 00 [05Fh 0095 1] _CST Support : 00 [060h 0096 2] C2 Latency : 0001 [062h 0098 2] C3 Latency : 0057 -[064h 0100 2] CPU Cache Size : 0400 -[066h 0102 2] Cache Flush Stride : 0010 -[068h 0104 1] Duty Cycle Offset : 01 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 [069h 0105 1] Duty Cycle Width : 00 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 00 [06Dh 0109 2] Boot Flags (decoded below) : 0003 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 1 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 CMOS RTC Not Present (V5) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 00008CAD WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 1 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 1 Sealed Case (V3) : 1 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 1 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 0 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 01 [SystemIO] [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 -[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[077h 0119 1] Encoded Access Width : 01 [Byte Access:8] [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 2] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 [083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 000000007BF46240 [08Ch 0140 8] DSDT Address : 000000007BF46280 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 01 [SystemIO] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 -[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[097h 0151 1] Encoded Access Width : 02 [Word Access:16] [098h 0152 8] Address : 0000000000001000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 01 [SystemIO] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : [Generic Address Structure] [0ACh 0172 1] Space ID : 01 [SystemIO] [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 -[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16] [0B0h 0176 8] Address : 0000000000001004 [0B8h 0184 12] PM1B Control Block : [Generic Address Structure] [0B8h 0184 1] Space ID : 01 [SystemIO] [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : [Generic Address Structure] [0C4h 0196 1] Space ID : 01 [SystemIO] [0C5h 0197 1] Bit Width : 08 [0C6h 0198 1] Bit Offset : 00 -[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8] [0C8h 0200 8] Address : 0000000000001050 [0D0h 0208 12] PM Timer Block : [Generic Address Structure] [0D0h 0208 1] Space ID : 01 [SystemIO] [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 -[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32] [0D4h 0212 8] Address : 0000000000001008 [0DCh 0220 12] GPE0 Block : [Generic Address Structure] -[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DCh 0220 1] Space ID : 01 [SystemIO] [0DDh 0221 1] Bit Width : 00 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] [0E0h 0224 8] Address : 0000000000000000 [0E8h 0232 12] GPE1 Block : [Generic Address Structure] [0E8h 0232 1] Space ID : 01 [SystemIO] [0E9h 0233 1] Bit Width : 00 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] [0ECh 0236 8] Address : 0000000000000000 Raw Table Data: Length 244 (0xF4) - 0000: 46 41 43 50 F4 00 00 00 04 61 43 4F 52 45 20 20 // FACP.....aCORE + 0000: 46 41 43 50 F4 00 00 00 04 6E 43 4F 52 45 20 20 // FACP.....nCORE 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE - 0020: 01 00 00 00 40 62 F4 7B 80 62 F4 7B 01 02 09 00 // ....(a)b.{.b.{.... + 0020: 00 00 00 00 40 62 F4 7B 80 62 F4 7B 00 02 09 00 // ....(a)b.{.b.{.... 0030: B2 00 00 00 E1 1E 00 00 00 10 00 00 00 00 00 00 // ................ 0040: 04 10 00 00 00 00 00 00 50 10 00 00 08 10 00 00 // ........P....... 0050: 80 10 00 00 00 00 00 00 04 02 01 04 20 00 00 00 // ............ ... - 0060: 01 00 57 00 00 04 10 00 01 00 0D 00 00 03 00 00 // ..W............. - 0070: AD 8C 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0060: 01 00 57 00 00 00 00 00 00 00 0D 00 00 03 00 00 // ..W............. + 0070: AD 8C 00 00 01 08 00 01 F9 0C 00 00 00 00 00 00 // ................ 0080: 06 00 00 00 40 62 F4 7B 00 00 00 00 80 62 F4 7B // ....@b.{.....b.{ - 0090: 00 00 00 00 01 20 00 00 00 10 00 00 00 00 00 00 // ..... .......... - 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 0090: 00 00 00 00 01 20 00 02 00 10 00 00 00 00 00 00 // ..... .......... + 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 02 // ................ 00B0: 04 10 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ - 00C0: 00 00 00 00 01 08 00 00 50 10 00 00 00 00 00 00 // ........P....... - 00D0: 01 20 00 00 08 10 00 00 00 00 00 00 00 00 00 00 // . .............. + 00C0: 00 00 00 00 01 08 00 01 50 10 00 00 00 00 00 00 // ........P....... + 00D0: 01 20 00 03 08 10 00 00 00 00 00 00 01 00 00 00 // . .............. 00E0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ 00F0: 00 00 00 00 // .... Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/devicetree.cb D src/mainboard/google/beltino/fadt.c D src/mainboard/google/slippy/fadt.c M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb D src/mainboard/intel/baskingridge/fadt.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lpc.c 12 files changed, 172 insertions(+), 453 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29387/3 -- To view, visit https://review.coreboot.org/29387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Gerrit-Change-Number: 29387 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/lynxpoint: Add a common platform.asl file
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29386 to look at the new patch set (#3). Change subject: sb/intel/lynxpoint: Add a common platform.asl file ...................................................................... sb/intel/lynxpoint: Add a common platform.asl file The platform.asl file is copied from sb/intel/bd82x6x, and also matches the contents deleted from each mainboard's platform.asl. Tested on an ASRock H81M-HDS and a Google Peppy board (variant of Slippy). No issues arose from this patch. Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/acpi/platform.asl M src/mainboard/google/slippy/acpi/platform.asl M src/mainboard/intel/baskingridge/acpi/platform.asl A src/southbridge/intel/lynxpoint/acpi/platform.asl 4 files changed, 56 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29386/3 -- To view, visit https://review.coreboot.org/29386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Gerrit-Change-Number: 29386 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/intel/haswell/gma: Support boards that have DDI E connected
by Tristan Corrick (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29385 to look at the new patch set (#3). Change subject: nb/intel/haswell/gma: Support boards that have DDI E connected ...................................................................... nb/intel/haswell/gma: Support boards that have DDI E connected On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to initialise the display when lanes are not configured to be shared between DDI A and DDI E. Intel's reference manual [1] states that the decision to share lanes between DDI A and DDI E is "based on board configuration". Hence, add a new field to the devicetree that boards can set. All existing Haswell boards have this unset, thus taking a value of 0, so there is no change to existing behaviour. [1]: Intel Open Source Graphics Programmer's Reference Manual (PRM) Volume 2c: Command Reference: Registers (Haswell) https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013… Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29385/3 -- To view, visit https://review.coreboot.org/29385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b Gerrit-Change-Number: 29385 Gerrit-PatchSet: 3 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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