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Change in coreboot[master]: NOT_FOR_MERGE soc/amd/stoneridge: Add DRAM check for s3
by build bot (Jenkins) (Code Review) 31 Oct '18

31 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29406 ) Change subject: NOT_FOR_MERGE soc/amd/stoneridge: Add DRAM check for s3 ...................................................................... Patch Set 1: (6 comments) https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… File src/soc/amd/stoneyridge/s3test_util.c: https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 249: wbinvd(); code indent should use tabs where possible https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 249: wbinvd(); please, no space before tabs https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 249: wbinvd(); please, no spaces at the start of a line https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 251: err = 0; code indent should use tabs where possible https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 251: err = 0; please, no space before tabs https://review.coreboot.org/#/c/29406/1/src/soc/amd/stoneyridge/s3test_util… PS1, Line 251: err = 0; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/29406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Gerrit-Change-Number: 29406 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 20:34:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: NOT_FOR_MERGE soc/amd/stoneridge: Add DRAM check for s3
by Marshall Dawson (Code Review) 31 Oct '18

31 Oct '18

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/29406 Change subject: NOT_FOR_MERGE soc/amd/stoneridge: Add DRAM check for s3 ...................................................................... NOT_FOR_MERGE soc/amd/stoneridge: Add DRAM check for s3 Allocate cbmem space to store DRAM check data during S3. Verify the the data is unchanged during the resume. Due to where the save and verify steps are placed, the test cannot capture 100% of potential memory corruption causes in coreboot. The ranges to verify are determined by the coreboot tables that are constructed at the end of POST. If a failure occurs within RAM available to the OS, the test reports "ERROR" to force suspend_stress_test to stop. Otherwise, the mismatch is reported as "FYI", e.g. in memory owned by coreboot. The granularity of blocks to check within each range is configurable, and defaults to 1MB. The size of data stored for each block is 32 bits. Both parameters may be changed if desired. CAUTION: This test must not be deployed in a shipping system. It disables TSEG, and its protections, in order to allow the performance to be at an acceptable level. TODO: Add the capability of checking DRAM above 4GB. TEST=Suspend and resume grunt. Verify mismatch with induced error. BUG=b:118157730 Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/amd_resume_final.c M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/amd/stoneyridge/finalize.c M src/soc/amd/stoneyridge/include/soc/iomap.h A src/soc/amd/stoneyridge/include/soc/s3test_util.h A src/soc/amd/stoneyridge/s3test_util.c M src/soc/amd/stoneyridge/smihandler.c 8 files changed, 431 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/29406/1 diff --git a/src/soc/amd/common/block/pi/amd_resume_final.c b/src/soc/amd/common/block/pi/amd_resume_final.c index a282665..7ee6470 100644 --- a/src/soc/amd/common/block/pi/amd_resume_final.c +++ b/src/soc/amd/common/block/pi/amd_resume_final.c @@ -15,10 +15,22 @@ #include <bootstate.h> #include <amdblocks/agesawrapper_call.h> +#include <soc/s3test_util.h> static void agesawrapper_s3finalrestore(void *unused) { do_agesawrapper(agesawrapper_amds3finalrestore, "amds3finalrestore"); + + /* todo: wrong place re. stoneyridge, but place here for now to ensure + * verification is as late as possible, and after AGESA. + * + * However, note that the ramstage copy and everything else in TSEG + * will be inaccessable if the BS_OS_RESUME, BS_ON_ENTRY soc_finalize() + * happens to run before this entry. That scenario will guarantee a + * mismatch if TSEG is tested. + */ + if (IS_ENABLED(CONFIG_DEBUG_CHECKSUM_DRAM_ON_S3)) + verify_dram_checksums(); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 4411984..1344d8b 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -385,4 +385,16 @@ return to S0. Otherwise the system will remain in S5 once power is restored. +config DEBUG_CHECKSUM_DRAM_ON_S3 + bool "Store checksums for DRAM during suspend" + default y # todo - y for convenience but change to n + help + During a suspend cycle, checksum the DRAM and store the results in + cbmem. Compare the values during a resume and dump any discrepancies + to the console. Certain errors may be reasonable, depending on their + addresses. + + This is a test feature and must never be deployed in production + systems. + endif # SOC_AMD_STONEYRIDGE_FP4 || SOC_AMD_STONEYRIDGE_FT4 diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index c54b652..a2d317e 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -117,6 +117,7 @@ ramstage-$(CONFIG_SPI_FLASH) += spi.c ramstage-y += finalize.c ramstage-y += nb_util.c +ramstage-$(CONFIG_DEBUG_CHECKSUM_DRAM_ON_S3) += s3test_util.c smm-y += monotonic_timer.c smm-y += smihandler.c @@ -127,6 +128,7 @@ smm-$(CONFIG_SPI_FLASH) += spi.c smm-y += nb_util.c smm-y += gpio.c +smm-$(CONFIG_DEBUG_CHECKSUM_DRAM_ON_S3) += s3test_util.c CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge CPPFLAGS_common += -I$(src)/soc/amd/stoneyridge/include diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 45e6595..dbe06b0 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -31,7 +31,12 @@ if (IS_ENABLED(CONFIG_SMM_TSEG)) { mask = rdmsr(SMM_MASK_MSR); - mask.lo |= SMM_TSEG_VALID; + /* If TSEG is marked valid, the CPU enforces UC memory type + * outside of SMRAM while in the SMI handler. Skipping this + * step allows the test to perform at an acceptable speed. + */ + if (!IS_ENABLED(CONFIG_DEBUG_CHECKSUM_DRAM_ON_S3)) + mask.lo |= SMM_TSEG_VALID; wrmsr(SMM_MASK_MSR, mask); } diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 3e86564..5bcd084 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -72,6 +72,8 @@ #define SYS_RESET 0xcf9 /* BiosRam Ranges at 0xfed80500 or I/O 0xcd4/0xcd5 */ +#define BIOSRAM_S3DRAM_CHECK_BASE 0xe8 /* 4 bytes */ +#define BIOSRAM_S3DRAM_LBMEM_BASE 0xec /* 4 bytes */ #define BIOSRAM_CBMEM_TOP 0xf0 /* 4 bytes */ #define BIOSRAM_UMA_SIZE 0xf4 /* 4 bytes */ #define BIOSRAM_UMA_BASE 0xf8 /* 8 bytes */ diff --git a/src/soc/amd/stoneyridge/include/soc/s3test_util.h b/src/soc/amd/stoneyridge/include/soc/s3test_util.h new file mode 100644 index 0000000..a6dcdea --- /dev/null +++ b/src/soc/amd/stoneyridge/include/soc/s3test_util.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __PI_STONEYRIDGE_S3_TESTUTIL_H__ +#define __PI_STONEYRIDGE_S3_TESTUTIL_H__ + +void store_dram_checksums(void); +void verify_dram_checksums(void); + +#endif /* __PI_STONEYRIDGE_S3_TESTUTIL_H__ */ diff --git a/src/soc/amd/stoneyridge/s3test_util.c b/src/soc/amd/stoneyridge/s3test_util.c new file mode 100644 index 0000000..0aa76de --- /dev/null +++ b/src/soc/amd/stoneyridge/s3test_util.c @@ -0,0 +1,368 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Advanced Micro Devices + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/southbridge.h> +#include <soc/s3test_util.h> +#include <soc/iomap.h> +#include <memrange.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <console/console.h> +#include <memlayout.h> +#include <cbmem.h> +#include <bootstate.h> +#include <commonlib/coreboot_tables.h> + +#define CHECK_TYPE_SAVE 0 +#define CHECK_TYPE_VERIFY 1 + +#define MAX_CHECK_RANGES 8 + +/* + * Adjust the block size as necessary to narrow in on the location of a failure. + * Normally a DWORD is stored for each 1MB test range, but this can be made + * smaller if space is a concern. + */ +#define TESTBLOCK_SZ (1 * MiB) +#define USE_SUM_SIZE32 + +#ifdef USE_SUM_SIZE8 +typedef uint8_t sum_t; +#endif +#ifdef USE_SUM_SIZE16 +typedef uint16_t sum_t; +#endif +#ifdef USE_SUM_SIZE32 +typedef uint32_t sum_t; +#endif +#ifdef USE_SUM_SIZE64 +typedef uint64_t sum_t; +#endif + +/* source code shorteners */ +#define FOUR_GB ((uint64_t)4 * GiB) +#define CL_SIZE ARCH_CACHELINE_ALIGN_SIZE + +static void write_dram_check_addr(void *base) +{ + biosram_write32(BIOSRAM_S3DRAM_CHECK_BASE, (uintptr_t)base); +} + +static void *read_dram_check_addr(void) +{ + return (void *)biosram_read32(BIOSRAM_S3DRAM_CHECK_BASE); +} + +static void write_lbmem_addr(void *base) +{ + biosram_write32(BIOSRAM_S3DRAM_LBMEM_BASE, (uintptr_t)base); +} + +static void *read_lbmem_addr(void) +{ + return (void *)biosram_read32(BIOSRAM_S3DRAM_LBMEM_BASE); +} + +#define MEM_RANGE_COUNT(_rec) \ + (((_rec)->size - sizeof(*(_rec))) / sizeof((_rec)->map[0])) + +#define MEM_RANGE_PTR(_rec, _idx) \ + (void *)(((u8 *) (_rec)) + sizeof(*(_rec)) \ + + (sizeof((_rec)->map[0]) * (_idx))) + +static inline resource_t lb_unpack64(struct lb_uint64 val) +{ + return (((resource_t) val.hi) << 32) | val.lo; +} + +/* These need to be consistent across POST and SMM but since those don't + * naturally share data, build the info from scratch. + * todo: convert to use devicetree instead? or maybe coreboot tables' + * knowledge of non-reserved memory? + */ +static int range_causes_error[MAX_CHECK_RANGES]; +static struct range_entry check_ranges[MAX_CHECK_RANGES]; +static struct memranges ranges = { + .entries = check_ranges, +}; + +/* + * Parse coreboot's memory ranges to decide what to test and whether a modified + * range constitutes a failure. + * + * todo: This file doesn't do above 4GB so cap the ranges + */ +static void fill_check_ranges(void) +{ + struct lb_memory *mem = (struct lb_memory *)read_lbmem_addr(); + int count; + int lb_rng, chk_rng; + + if (!mem) { + printk(BIOS_ERR, "ERROR: Can't find saved pointer to lb tables\n"); + return; + } + + count = MEM_RANGE_COUNT(mem); + if (count > MAX_CHECK_RANGES) { + /* maybe not really, as some won't be used... */ + printk(BIOS_ERR, "ERROR: Need to increase MAX_CHECK_RANGES\n"); + count = MAX_CHECK_RANGES; + } + + chk_rng = 0; + for (lb_rng = 0 ; lb_rng < count ; lb_rng++) { + struct lb_memory_range *range = MEM_RANGE_PTR(mem, lb_rng); + + if (range->type == LB_MEM_RESERVED + || range->type == LB_MEM_VENDOR_RSVD + || range->type == LB_MEM_UNUSABLE) + continue; + + /* Still can't do >=4GB */ + if (lb_unpack64(range->start) >= FOUR_GB) + continue; + + if (chk_rng) + check_ranges[chk_rng - 1].next = &check_ranges[chk_rng]; + + range_entry_init(check_ranges + chk_rng, + lb_unpack64(range->start), + MIN(FOUR_GB, lb_unpack64(range->start) + + lb_unpack64(range->size)), + chk_rng); + range_causes_error[chk_rng] = range->type == LB_MEM_RAM ? 1 : 0; + chk_rng++; + } +} + +/* If necessary, fold a 64-bit value enough times to fit into sum_t */ +static sum_t sum_to_sumt(uint64_t sum64) +{ + if (sizeof(sum_t) == sizeof(uint64_t)) + return sum64; + + uint32_t sum32 = (uint32_t)(sum64 + (sum64 >> 32)); + if (sizeof(sum_t) == sizeof(uint32_t)) + return sum32; + + uint16_t sum16 = (uint16_t)(sum32 + (sum32 >> 16)); + if (sizeof(sum_t) == sizeof(uint16_t)) + return sum16; + + uint8_t sum8 = (uint8_t)(sum16 + (sum16 >> 8)); + return sum8; +} + +/* + * todo: this function cannot access >4GB + */ +static sum_t calc_range(resource_t rstart, resource_t rlimit) +{ + uint64_t sum; + const uint8_t *start, *end; + const uint8_t *aligned_start; + const uint8_t *aligned_end; + int pre_aligned_num; + int post_aligned_num; + int lines; + int i; + const uint8_t *i8; + const uint64_t *i64; + + sum = 0; + + /* since we don't do 4GB yet, help this function be prettier */ + start = (u8 *)(uintptr_t)rstart; + end = (u8 *)(uintptr_t)rlimit + 1; /* treat end like start + size */ + + aligned_start = (uint8_t *)ALIGN_UP((uintptr_t)start, CL_SIZE); + aligned_end = (uint8_t *)ALIGN_DOWN((uintptr_t)end, CL_SIZE); + + pre_aligned_num = (uintptr_t)aligned_start - (uintptr_t)start; + post_aligned_num = (uintptr_t)end - (uintptr_t)aligned_end; + + lines = ((uintptr_t)aligned_end - (uintptr_t)aligned_start) / CL_SIZE; + + /* Do all unaligned as bytes, regardless of how many */ + for (i8 = start ; i8 < aligned_start ; i8++) + sum += *i8; + + i64 = (uint64_t *)aligned_start; + for (i = 0 ; i < lines ; i++) { /* unroll one cacheline worth */ + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + sum += *(i64++); + } + + for (i8 = aligned_end ; i8 < end ; i++) + sum += *i8; + + return sum_to_sumt(sum); +} + +static void print_fail(resource_t begin, resource_t end, int e) +{ + printk(BIOS_ERR, " %s: Mismatch found in 0x%llx-0x%llx\n", + range_causes_error[e] ? "ERROR" : "FYI", begin, end); +} + +static void do_dram_checksums(int type) +{ + printk(BIOS_DEBUG, "Begin calculating DRAM check data...\n"); + + sum_t *save_area = read_dram_check_addr(); + struct range_entry *re; + resource_t blk; + int err; + + if (!save_area) { + printk(BIOS_ERR, "Error: no DRAM check save error, exiting test.\n"); + return; + } + + fill_check_ranges(); + + /* + * Don't rely on this function being called after the SMM handler has + * already written back the cache contents. Resume shouldn't make a + * difference worth caring about. + */ + wbinvd(); + + err = 0; + memranges_each_entry(re, &ranges) { + printk(BIOS_DEBUG, " Calculate range 0x%llx-0x%llx\n", + re->begin, re->end); + for (blk = re->begin ; blk < re->end ; blk += TESTBLOCK_SZ) { + resource_t end = MIN(blk + TESTBLOCK_SZ - 1, re->end); + + if (type == CHECK_TYPE_SAVE) + *(save_area) = calc_range(blk, end); + else + if (*save_area != calc_range(blk, end)) + print_fail(blk, end, err); + save_area++; + } + err++; + } +} + +static void highest_performance(void) +{ + /* todo: abstract better, especially if it moves out of stoneyridge + * + * The performance hit probably isn't substantial enough to worry + * about as long as we can cache outside of SMRAM. + */ + + /* CPU P-State to 0 */ + msr_t pst = rdmsr(0xc0010062); // no define for this yet!? + pst.lo &= ~7; + wrmsr(0xc0010062, pst); +} + +void store_dram_checksums(void) +{ + printk(BIOS_DEBUG, "Begin calculating DRAM check data...\n"); + + highest_performance(); + do_dram_checksums(CHECK_TYPE_SAVE); +} + +void verify_dram_checksums(void) +{ + printk(BIOS_DEBUG, "|| S3 memory check beginning. Certain miscompares should\n" + "|| be anticipated. Addresses may be verified against the\n" + "|| coreboot table written at the end of POST.\n"); + do_dram_checksums(CHECK_TYPE_VERIFY); +} + +/* + * During POST, ensure we have adequate cbmem space reserved for storing the + * check info. This function should also be safe to call during a resume. + * + * Note that cbmem functions aren't available in SMM, but the file still builds + * OK since functions like this aren't referenced. + */ +static void setup_s3_dram_debug(int unused) +{ + uint64_t installed; + size_t size; + msr_t tom2 = rdmsr(TOP_MEM2); + void *mem; + + /* simple inference for installed memory, won't work for if <4 GB! */ + installed = tom2.hi; + installed *= 4; + installed *= GiB; + size = installed / TESTBLOCK_SZ * sizeof(sum_t); + + /* cheat without making a new ID, currently only used for Family 10h */ + mem = cbmem_add(CBMEM_ID_AMDMCT_MEMINFO, size); + + if (!mem) + printk(BIOS_ERR, "Error, can't allocate cbmem to store DRAM S3 check data\n"); + + write_dram_check_addr(mem); +} + +/* + * Use coreboot's calculations to determine what memory to test. Right now + * save a pointer away and parse the info as needed. + */ +static void find_lb_tables_in_mem(void *unused) +{ + struct lb_header *header; + uint8_t *ptr = (uint8_t *)cbmem_find(CBMEM_ID_CBTABLE); + int i; + + if (!ptr) { + printk(BIOS_ERR, "Error, S3 DRAM test setup: can't find the lb tables\n"); + return; + } + + header = (struct lb_header *)ptr; + + if (strncmp((const char *)header->signature, "LBIO", 4)) { + printk(BIOS_ERR, "Error, S3 DRAM test setup: don't recognize the lb tables @0x%p\n", + header); + return; + } + + ptr += header->header_bytes; + for (i = 0; i < header->table_entries; i++) { + struct lb_record *rec = (struct lb_record *)ptr; + + if (rec->tag != LB_TAG_MEMORY) { + ptr += rec->size; + continue; + } + + write_lbmem_addr(rec); + return; + } + printk(BIOS_ERR, "Error, S3 DRAM test setup: No LB_TAG_MEMORY found\n"); + write_lbmem_addr(NULL); +} + +RAMSTAGE_CBMEM_INIT_HOOK(setup_s3_dram_debug) +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, find_lb_tables_in_mem, NULL); diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c index 8985257..6782d20 100644 --- a/src/soc/amd/stoneyridge/smihandler.c +++ b/src/soc/amd/stoneyridge/smihandler.c @@ -24,6 +24,7 @@ #include <device/pci_def.h> #include <soc/smi.h> #include <soc/southbridge.h> +#include <soc/s3test_util.h> #include <elog.h> /* bits in smm_io_trap */ @@ -153,6 +154,12 @@ } if (slp_typ >= ACPI_S3) { + /* + * todo: how can I call this sooner? This is the earliest + * opportunity when we're sure we're on our way to S3. + */ + store_dram_checksums(); + /* Sleep Type Elog S3, S4, and S5 entry */ if (IS_ENABLED(CONFIG_ELOG_GSMI)) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); -- To view, visit https://review.coreboot.org/29406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I375dd7ea9a3ab8992f1616126bcbd9724e4fc9a0 Gerrit-Change-Number: 29406 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: sb/intel/common/pciehp.h: Fix missing license header
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29404 to look at the new patch set (#3). Change subject: sb/intel/common/pciehp.h: Fix missing license header ...................................................................... sb/intel/common/pciehp.h: Fix missing license header also add missing include stdint.h Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/pciehp.h 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/29404/3 -- To view, visit https://review.coreboot.org/29404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia669b25683c138d96be00db90d01cf406db4c2eb Gerrit-Change-Number: 29404 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29405 Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> This is part #3 follows Change-Id: I6a9d71e69 and Change-Id: Idf10a0974 Change-Id: Iaf0fa38daf858bcd668962f14ffcbaf359113413 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/x86/include/arch/registers.h M src/cpu/intel/smm/gen1/smi.h M src/cpu/ti/am335x/uart.h M src/drivers/aspeed/common/ast_dram_tables.h M src/drivers/elog/elog_internal.h M src/drivers/generic/ioapic/chip.h M src/drivers/i2c/ck505/chip.h M src/drivers/i2c/max98373/chip.h M src/drivers/i2c/rt5663/chip.h M src/drivers/i2c/rtd2132/chip.h M src/drivers/i2c/w83795/chip.h M src/drivers/intel/fsp2_0/include/fsp/upd.h M src/drivers/intel/gma/intel_bios.h M src/drivers/maxim/max77686/max77686.h M src/drivers/net/chip.h M src/drivers/parade/ps8625/ps8625.h M src/drivers/ricoh/rce822/chip.h M src/drivers/siemens/nc_fpga/nc_fpga.h M src/drivers/spi/spi_flash_internal.h M src/drivers/usb/ehci.h M src/drivers/usb/usb_ch9.h M src/drivers/xgi/common/vb_util.h M src/ec/hp/kbc1126/chip.h M src/ec/lenovo/h8/chip.h M src/ec/quanta/ene_kb3940q/ec.h M src/ec/quanta/it8518/ec.h M src/ec/smsc/mec1308/ec.h M src/include/cpu/amd/powernow.h M src/include/cpu/amd/vr.h M src/include/cpu/intel/l2_cache.h M src/include/device/dram/common.h M src/include/elog.h M src/include/pc80/i8259.h M src/include/swab.h M src/mainboard/advansus/a785e-i/mb_sysconf.h M src/mainboard/amd/bimini_fam10/mb_sysconf.h M src/mainboard/amd/mahogany_fam10/mb_sysconf.h M src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h M src/mainboard/amd/tilapia_fam10/mb_sysconf.h M src/mainboard/amd/torpedo/pmio.h M src/mainboard/asus/kcma-d8/mb_sysconf.h M src/mainboard/asus/kgpe-d16/mb_sysconf.h M src/mainboard/asus/m4a78-em/mb_sysconf.h M src/mainboard/asus/m4a785-m/mb_sysconf.h M src/mainboard/asus/m5a88-v/mb_sysconf.h M src/mainboard/avalue/eax-785e/mb_sysconf.h M src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h M src/mainboard/getac/p470/ec_oem.h M src/mainboard/gigabyte/ma785gm/mb_sysconf.h M src/mainboard/google/cyan/spd/spd_util.h M src/mainboard/google/urara/urara_boardid.h M src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h M src/mainboard/pcengines/apu1/gpio_ftns.h M src/mainboard/pcengines/apu2/gpio_ftns.h M src/mainboard/scaleway/tagada/bmcinfo.h M src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h M src/northbridge/amd/amdfam10/ht_config.h M src/northbridge/amd/amdmct/amddefs.h M src/northbridge/intel/e7505/raminit.h M src/northbridge/intel/haswell/pei_data.h M src/northbridge/intel/i945/raminit.h M src/northbridge/intel/sandybridge/gma.h M src/northbridge/intel/sandybridge/pei_data.h M src/northbridge/intel/sandybridge/raminit_common.h M src/northbridge/intel/sandybridge/raminit_patterns.h M src/security/tpm/tss/tcg-1.2/tss_commands.h M src/security/tpm/tss/tcg-1.2/tss_internal.h M src/security/tpm/tss_errors.h M src/soc/broadcom/cygnus/include/soc/tz.h M src/soc/cavium/cn81xx/include/soc/cpu.h M src/soc/cavium/common/include/soc/bootblock.h M src/soc/intel/apollolake/include/soc/usb.h M src/soc/intel/broadwell/chip.h M src/soc/intel/broadwell/include/soc/igd.h M src/soc/intel/broadwell/include/soc/iobp.h M src/soc/intel/broadwell/include/soc/pch.h M src/soc/intel/cannonlake/include/soc/ebda.h M src/soc/intel/denverton_ns/chip.h M src/soc/intel/icelake/include/soc/ebda.h M src/soc/intel/quark/include/soc/i2c.h M src/soc/intel/skylake/include/soc/ebda.h M src/soc/intel/skylake/include/soc/me.h M src/soc/nvidia/tegra210/include/soc/flow_ctrl.h M src/soc/qualcomm/ipq806x/include/soc/ebi2.h M src/soc/sifive/fu540/include/soc/otp.h M src/southbridge/amd/cimx/sb800/gpio_oem.h M src/southbridge/amd/cimx/sb900/chip.h M src/southbridge/amd/pi/hudson/chip.h M src/southbridge/amd/rs780/chip.h M src/southbridge/amd/sb700/pmio.h M src/southbridge/amd/sb800/chip.h M src/southbridge/intel/bd82x6x/chip.h M src/southbridge/intel/bd82x6x/me.h M src/southbridge/intel/common/smbus.h M src/southbridge/intel/fsp_bd82x6x/chip.h M src/southbridge/intel/fsp_i89xx/chip.h M src/southbridge/intel/i82801dx/chip.h M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/lynxpoint/chip.h M src/superio/nuvoton/npcd378/npcd378.h M src/superio/nuvoton/wpcm450/wpcm450.h M src/superio/smsc/sio1007/chip.h 104 files changed, 216 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/29405/1 diff --git a/src/arch/x86/include/arch/registers.h b/src/arch/x86/include/arch/registers.h index 08f83ac..1d3b90a 100644 --- a/src/arch/x86/include/arch/registers.h +++ b/src/arch/x86/include/arch/registers.h @@ -17,6 +17,8 @@ #define __ARCH_REGISTERS_H #if !defined(__ASSEMBLER__) +#include <stdint.h> + #define DOWNTO8(A) \ union { \ struct { \ diff --git a/src/cpu/intel/smm/gen1/smi.h b/src/cpu/intel/smm/gen1/smi.h index f4cbbc3..117cc17 100644 --- a/src/cpu/intel/smm/gen1/smi.h +++ b/src/cpu/intel/smm/gen1/smi.h @@ -12,6 +12,9 @@ */ /* These helpers are for performing SMM relocation. */ + +#include <stdint.h> + void southbridge_smm_init(void); void southbridge_trigger_smi(void); void southbridge_clear_smi_status(void); diff --git a/src/cpu/ti/am335x/uart.h b/src/cpu/ti/am335x/uart.h index 000a45d..fe9197f 100644 --- a/src/cpu/ti/am335x/uart.h +++ b/src/cpu/ti/am335x/uart.h @@ -15,6 +15,8 @@ #ifndef AM335X_UART_H #define AM335X_UART_H +#include <stdint.h> + #define AM335X_UART0_BASE 0x44e09000 #define AM335X_UART1_BASE 0x48020000 #define AM335X_UART2_BASE 0x48024000 diff --git a/src/drivers/aspeed/common/ast_dram_tables.h b/src/drivers/aspeed/common/ast_dram_tables.h index 1d46ca6..fd03088 100644 --- a/src/drivers/aspeed/common/ast_dram_tables.h +++ b/src/drivers/aspeed/common/ast_dram_tables.h @@ -18,6 +18,8 @@ #ifndef AST_DRAM_TABLES_H #define AST_DRAM_TABLES_H +#include <stdint.h> + /* DRAM timing tables */ struct ast_dramstruct { u16 index; diff --git a/src/drivers/elog/elog_internal.h b/src/drivers/elog/elog_internal.h index afcee57..2b32bc5 100644 --- a/src/drivers/elog/elog_internal.h +++ b/src/drivers/elog/elog_internal.h @@ -16,6 +16,8 @@ #ifndef ELOG_INTERNAL_H_ #define ELOG_INTERNAL_H_ +#include <stdint.h> + /* ELOG header */ struct elog_header { u32 magic; diff --git a/src/drivers/generic/ioapic/chip.h b/src/drivers/generic/ioapic/chip.h index a941ae1..b9021f4 100644 --- a/src/drivers/generic/ioapic/chip.h +++ b/src/drivers/generic/ioapic/chip.h @@ -17,6 +17,8 @@ #ifndef DRIVERS_GENERIC_IOAPIC_CHIP_H #define DRIVERS_GENERIC_IOAPIC_CHIP_H +#include <stdint.h> + typedef struct drivers_generic_ioapic_config { u32 version; u8 apicid; diff --git a/src/drivers/i2c/ck505/chip.h b/src/drivers/i2c/ck505/chip.h index 8ce297c..c7a8479 100644 --- a/src/drivers/i2c/ck505/chip.h +++ b/src/drivers/i2c/ck505/chip.h @@ -17,6 +17,8 @@ #ifndef DRIVERS_CK505_CHIP_H #define DRIVERS_CK505_CHIP_H +#include <stdint.h> + struct drivers_i2c_ck505_config { const int nregs; const u8 regs[32]; diff --git a/src/drivers/i2c/max98373/chip.h b/src/drivers/i2c/max98373/chip.h index ad81395..dcaf357 100644 --- a/src/drivers/i2c/max98373/chip.h +++ b/src/drivers/i2c/max98373/chip.h @@ -16,6 +16,9 @@ /* * Maxim MAX98373 audio codec devicetree bindings */ + +#include <stdint.h> + struct drivers_i2c_max98373_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ uint32_t bus_speed; diff --git a/src/drivers/i2c/rt5663/chip.h b/src/drivers/i2c/rt5663/chip.h index 1b367c9..5720b18 100644 --- a/src/drivers/i2c/rt5663/chip.h +++ b/src/drivers/i2c/rt5663/chip.h @@ -16,6 +16,9 @@ /* * Realtek RT5663 audio codec devicetree bindings */ + +#include <stdint.h> + struct drivers_i2c_rt5663_config { /* I2C Bus Frequency in Hertz (default 400kHz) */ unsigned int bus_speed; diff --git a/src/drivers/i2c/rtd2132/chip.h b/src/drivers/i2c/rtd2132/chip.h index 2906fde..a091fe4 100644 --- a/src/drivers/i2c/rtd2132/chip.h +++ b/src/drivers/i2c/rtd2132/chip.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <stdint.h> + struct drivers_i2c_rtd2132_config { /* Panel Power Sequencing. All units in ms. */ u16 t1; /* Delay from panel Vcc enable to LVDS output enable. */ diff --git a/src/drivers/i2c/w83795/chip.h b/src/drivers/i2c/w83795/chip.h index b48c523..e3426de 100644 --- a/src/drivers/i2c/w83795/chip.h +++ b/src/drivers/i2c/w83795/chip.h @@ -13,6 +13,8 @@ * GNU General Public License for more details. */ +#include <stdint.h> + struct drivers_i2c_w83795_config { uint8_t fanin_ctl1; uint8_t fanin_ctl2; diff --git a/src/drivers/intel/fsp2_0/include/fsp/upd.h b/src/drivers/intel/fsp2_0/include/fsp/upd.h index 15094df..19c5423 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/upd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/upd.h @@ -12,6 +12,8 @@ #ifndef _FSP2_0_UPD_H_ #define _FSP2_0_UPD_H_ +#include <stdint.h> + struct FSP_UPD_HEADER { /// /// UPD Region Signature. This signature will be diff --git a/src/drivers/intel/gma/intel_bios.h b/src/drivers/intel/gma/intel_bios.h index 8bf44ee..bf08539 100644 --- a/src/drivers/intel/gma/intel_bios.h +++ b/src/drivers/intel/gma/intel_bios.h @@ -28,6 +28,8 @@ #ifndef _I830_BIOS_H_ #define _I830_BIOS_H_ +#include <stdint.h> + struct vbt_header { u8 signature[20]; /**< Always starts with 'VBT$' */ u16 version; /**< decimal */ diff --git a/src/drivers/maxim/max77686/max77686.h b/src/drivers/maxim/max77686/max77686.h index 63cdf69..4ae5f37 100644 --- a/src/drivers/maxim/max77686/max77686.h +++ b/src/drivers/maxim/max77686/max77686.h @@ -16,6 +16,8 @@ #ifndef __MAX77686_H_ #define __MAX77686_H_ +#include <stdint.h> + enum max77686_regnum { PMIC_BUCK1 = 0, PMIC_BUCK2, diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 383614f..985a85a 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -14,6 +14,8 @@ #ifndef __DRIVERS_R8168_CHIP_H__ #define __DRIVERS_R8168_CHIP_H__ +#include <stdint.h> + struct drivers_net_config { uint16_t customized_leds; unsigned wake; /* Wake pin for ACPI _PRW */ diff --git a/src/drivers/parade/ps8625/ps8625.h b/src/drivers/parade/ps8625/ps8625.h index 1fbb01c..a5132f1 100644 --- a/src/drivers/parade/ps8625/ps8625.h +++ b/src/drivers/parade/ps8625/ps8625.h @@ -16,6 +16,8 @@ #ifndef __PS8625_H__ #define __PS8625_H__ +#include <stdint.h> + struct parade_write { uint8_t offset; uint8_t reg; diff --git a/src/drivers/ricoh/rce822/chip.h b/src/drivers/ricoh/rce822/chip.h index 832a3d3..b06bbcf 100644 --- a/src/drivers/ricoh/rce822/chip.h +++ b/src/drivers/ricoh/rce822/chip.h @@ -17,6 +17,8 @@ #ifndef DRIVERS_RICOH_RC822_CHIP_H #define DRIVERS_RICOH_RC822_CHIP_H +#include <stdint.h> + struct drivers_ricoh_rce822_config { u8 sdwppol:1; u8 disable_mask; diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.h b/src/drivers/siemens/nc_fpga/nc_fpga.h index fe5f612..f1982d2 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.h +++ b/src/drivers/siemens/nc_fpga/nc_fpga.h @@ -16,6 +16,8 @@ #ifndef _SIEMENS_NC_FPGA_H_ #define _SIEMENS_NC_FPGA_H_ +#include <stdint.h> + #define NC_MAGIC_OFFSET 0x020 #define NC_FPGA_MAGIC 0x4E433746 #define NC_CAP1_OFFSET 0x080 diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index b42df59..4bb35ea 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -7,6 +7,8 @@ #ifndef SPI_FLASH_INTERNAL_H #define SPI_FLASH_INTERNAL_H +#include <stdint.h> + /* Common parameters -- kind of high, but they should only occur when there * is a problem (and well your system already is broken), so err on the side * of caution in case we're dealing with slower SPI buses and/or processors. diff --git a/src/drivers/usb/ehci.h b/src/drivers/usb/ehci.h index e86286a..6bd2195 100644 --- a/src/drivers/usb/ehci.h +++ b/src/drivers/usb/ehci.h @@ -19,6 +19,8 @@ #ifndef EHCI_H #define EHCI_H +#include <stdint.h> + /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ /* Section 2.2 Host Controller Capability Registers */ diff --git a/src/drivers/usb/usb_ch9.h b/src/drivers/usb/usb_ch9.h index 79f1654..bd796ef 100644 --- a/src/drivers/usb/usb_ch9.h +++ b/src/drivers/usb/usb_ch9.h @@ -17,6 +17,8 @@ #ifndef USB_CH9_H #define USB_CH9_H +#include <stdint.h> + #define USB_DIR_OUT 0 /* to device */ #define USB_DIR_IN 0x80 /* to host */ diff --git a/src/drivers/xgi/common/vb_util.h b/src/drivers/xgi/common/vb_util.h index d5d30ed..03134fb 100644 --- a/src/drivers/xgi/common/vb_util.h +++ b/src/drivers/xgi/common/vb_util.h @@ -15,6 +15,9 @@ #ifndef _VBUTIL_ #define _VBUTIL_ + +#include <stdint.h> + extern void xgifb_reg_set(unsigned long, u8, u8); extern u8 xgifb_reg_get(unsigned long, u8); extern void xgifb_reg_or(unsigned long, u8, unsigned); diff --git a/src/ec/hp/kbc1126/chip.h b/src/ec/hp/kbc1126/chip.h index 009aa6b..3923dcf 100644 --- a/src/ec/hp/kbc1126/chip.h +++ b/src/ec/hp/kbc1126/chip.h @@ -17,6 +17,8 @@ #ifndef _EC_HP_KBC1126_CHIP_H #define _EC_HP_KBC1126_CHIP_H +#include <stdint.h> + struct ec_hp_kbc1126_config { u16 ec_data_port; diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 25512bc..a0e8c7e 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -16,6 +16,8 @@ #ifndef EC_LENOVO_H8EC_CHIP_H #define EC_LENOVO_H8EC_CHIP_H +#include <stdint.h> + struct ec_lenovo_h8_config { u8 config0; diff --git a/src/ec/quanta/ene_kb3940q/ec.h b/src/ec/quanta/ene_kb3940q/ec.h index b04809e..ba295ba 100644 --- a/src/ec/quanta/ene_kb3940q/ec.h +++ b/src/ec/quanta/ene_kb3940q/ec.h @@ -20,6 +20,8 @@ #ifndef _EC_QUANTA_ENE_KB3940Q_EC_H #define _EC_QUANTA_ENE_KB3940Q_EC_H +#include <stdint.h> + #define EC_IO 0x380 /* Mainboard specific. Could be Kconfig option */ #define EC_IO_HIGH EC_IO + 1 #define EC_IO_LOW EC_IO + 2 diff --git a/src/ec/quanta/it8518/ec.h b/src/ec/quanta/it8518/ec.h index 6fca3b9..1f55d8d 100644 --- a/src/ec/quanta/it8518/ec.h +++ b/src/ec/quanta/it8518/ec.h @@ -20,6 +20,8 @@ #ifndef _EC_QUANTA_IT8518_EC_H #define _EC_QUANTA_IT8518_EC_H +#include <stdint.h> + #define EC_IO 0x100 /* Mainboard specific. Could be Kconfig option */ #define EC_IO_HIGH EC_IO + 1 #define EC_IO_LOW EC_IO + 2 diff --git a/src/ec/smsc/mec1308/ec.h b/src/ec/smsc/mec1308/ec.h index feedfb9..06b4c8b 100644 --- a/src/ec/smsc/mec1308/ec.h +++ b/src/ec/smsc/mec1308/ec.h @@ -18,6 +18,8 @@ #ifndef _EC_SMSC_MEC1308_EC_H #define _EC_SMSC_MEC1308_EC_H +#include <stdint.h> + #define EC_TIMEOUT 0xfff #define EC_MAILBOX_COMMAND 0x82 // Send a command #define EC_MAILBOX_DATA 0x84 // Send data with a command diff --git a/src/include/cpu/amd/powernow.h b/src/include/cpu/amd/powernow.h index 77df7b0..c39318b 100644 --- a/src/include/cpu/amd/powernow.h +++ b/src/include/cpu/amd/powernow.h @@ -18,6 +18,8 @@ #ifndef POWERNOW_H #define POWERNOW_H +#include <stdint.h> + void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP); void amd_powernow_update_fadt(acpi_fadt_t *fadt); diff --git a/src/include/cpu/amd/vr.h b/src/include/cpu/amd/vr.h index e5ab840..8c62e44 100644 --- a/src/include/cpu/amd/vr.h +++ b/src/include/cpu/amd/vr.h @@ -7,6 +7,8 @@ #ifndef CPU_AMD_VR_H #define CPU_AMD_VR_H +#include <stdint.h> + #define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register #define VR_UNLOCK 0xFC53 // Virtual register unlock code diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 1303148..31eb49d 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -27,6 +27,8 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H +#include <stdint.h> + #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index 31cdb2b..dd04bfe 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -18,6 +18,8 @@ #ifndef DEVICE_DRAM_COMMON_H #define DEVICE_DRAM_COMMON_H +#include <stdint.h> + /** * \brief Convenience definitions for TCK values * diff --git a/src/include/elog.h b/src/include/elog.h index 8aecf2c..301f554 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -16,6 +16,8 @@ #ifndef ELOG_H_ #define ELOG_H_ +#include <stdint.h> + /* SMI command code for GSMI event logging */ #define ELOG_GSMI_APM_CNT 0xEF diff --git a/src/include/pc80/i8259.h b/src/include/pc80/i8259.h index 857c5c8..2cb48ea 100644 --- a/src/include/pc80/i8259.h +++ b/src/include/pc80/i8259.h @@ -17,6 +17,8 @@ #ifndef PC80_I8259_H #define PC80_I8259_H +#include <stdint.h> + /* * IRQ numbers and common usage * If an IRQ does not say it is 'Reserved' diff --git a/src/include/swab.h b/src/include/swab.h index 7d781a0..956cfa5 100644 --- a/src/include/swab.h +++ b/src/include/swab.h @@ -1,6 +1,3 @@ -#ifndef _SWAB_H -#define _SWAB_H - /* * linux/byteorder/swab.h * Byte-swapping, independently from CPU endianness @@ -18,6 +15,12 @@ /* casts are necessary for constants, because we never know how for sure * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way. */ + +#ifndef _SWAB_H +#define _SWAB_H + +#include <stdint.h> + #define swab16(x) \ ((unsigned short)( \ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \ diff --git a/src/mainboard/advansus/a785e-i/mb_sysconf.h b/src/mainboard/advansus/a785e-i/mb_sysconf.h index d3383f9..88b6ba3 100644 --- a/src/mainboard/advansus/a785e-i/mb_sysconf.h +++ b/src/mainboard/advansus/a785e-i/mb_sysconf.h @@ -16,6 +16,8 @@ #ifndef MB_SYSCONF_H #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/amd/bimini_fam10/mb_sysconf.h b/src/mainboard/amd/bimini_fam10/mb_sysconf.h index 1a5b67c..7f111fd 100644 --- a/src/mainboard/amd/bimini_fam10/mb_sysconf.h +++ b/src/mainboard/amd/bimini_fam10/mb_sysconf.h @@ -16,6 +16,8 @@ #ifndef MB_SYSCONF_H #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/amd/mahogany_fam10/mb_sysconf.h +++ b/src/mainboard/amd/mahogany_fam10/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h index 7d8cf00..99afc61 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_8132_0; u8 bus_8132_1; diff --git a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/amd/tilapia_fam10/mb_sysconf.h +++ b/src/mainboard/amd/tilapia_fam10/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/amd/torpedo/pmio.h b/src/mainboard/amd/torpedo/pmio.h index ed38eed..c5a80f8 100644 --- a/src/mainboard/amd/torpedo/pmio.h +++ b/src/mainboard/amd/torpedo/pmio.h @@ -17,6 +17,8 @@ #ifndef _PMIO_H_ #define _PMIO_H_ +#include <stdint.h> + #define PM_INDEX 0xCD6 #define PM_DATA 0xCD7 #define PM2_INDEX 0xCD0 diff --git a/src/mainboard/asus/kcma-d8/mb_sysconf.h b/src/mainboard/asus/kcma-d8/mb_sysconf.h index 7db0d9f..cc603b2 100644 --- a/src/mainboard/asus/kcma-d8/mb_sysconf.h +++ b/src/mainboard/asus/kcma-d8/mb_sysconf.h @@ -15,9 +15,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/asus/kgpe-d16/mb_sysconf.h b/src/mainboard/asus/kgpe-d16/mb_sysconf.h index 7db0d9f..cc603b2 100644 --- a/src/mainboard/asus/kgpe-d16/mb_sysconf.h +++ b/src/mainboard/asus/kgpe-d16/mb_sysconf.h @@ -15,9 +15,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/asus/m4a78-em/mb_sysconf.h b/src/mainboard/asus/m4a78-em/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/asus/m4a78-em/mb_sysconf.h +++ b/src/mainboard/asus/m4a78-em/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/asus/m4a785-m/mb_sysconf.h b/src/mainboard/asus/m4a785-m/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/asus/m4a785-m/mb_sysconf.h +++ b/src/mainboard/asus/m4a785-m/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/asus/m5a88-v/mb_sysconf.h b/src/mainboard/asus/m5a88-v/mb_sysconf.h index d3383f9..88b6ba3 100644 --- a/src/mainboard/asus/m5a88-v/mb_sysconf.h +++ b/src/mainboard/asus/m5a88-v/mb_sysconf.h @@ -16,6 +16,8 @@ #ifndef MB_SYSCONF_H #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/avalue/eax-785e/mb_sysconf.h b/src/mainboard/avalue/eax-785e/mb_sysconf.h index d3383f9..88b6ba3 100644 --- a/src/mainboard/avalue/eax-785e/mb_sysconf.h +++ b/src/mainboard/avalue/eax-785e/mb_sysconf.h @@ -16,6 +16,8 @@ #ifndef MB_SYSCONF_H #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h index 903ebaa..8f1e24c 100644 --- a/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h +++ b/src/mainboard/emulation/qemu-i440fx/fw_cfg_if.h @@ -17,6 +17,8 @@ * Copyed over from qemu soure tree, include/hw/nvram/fw_cfg.h */ +#include <stdint.h> + #define FW_CFG_SIGNATURE 0x00 #define FW_CFG_ID 0x01 #define FW_CFG_UUID 0x02 diff --git a/src/mainboard/getac/p470/ec_oem.h b/src/mainboard/getac/p470/ec_oem.h index 5d56107..8b536c8 100644 --- a/src/mainboard/getac/p470/ec_oem.h +++ b/src/mainboard/getac/p470/ec_oem.h @@ -17,6 +17,8 @@ #ifndef _MAINBOARD_EC_OEM_H #define _MAINBOARD_EC_OEM_H +#include <stdint.h> + #define EC_OEM_DATA 0x68 #define EC_OEM_SC 0x6c diff --git a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/gigabyte/ma785gm/mb_sysconf.h +++ b/src/mainboard/gigabyte/ma785gm/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/google/cyan/spd/spd_util.h b/src/mainboard/google/cyan/spd/spd_util.h index 11d6eaa..333293e 100644 --- a/src/mainboard/google/cyan/spd/spd_util.h +++ b/src/mainboard/google/cyan/spd/spd_util.h @@ -16,6 +16,8 @@ #ifndef SPD_UTIL_H #define SPD_UTIL_H +#include <stdint.h> + uint8_t get_ramid(void); int get_variant_spd_index(int ram_id, int *dual); diff --git a/src/mainboard/google/urara/urara_boardid.h b/src/mainboard/google/urara/urara_boardid.h index 7c7c045..fbd9179 100644 --- a/src/mainboard/google/urara/urara_boardid.h +++ b/src/mainboard/google/urara/urara_boardid.h @@ -16,6 +16,8 @@ #ifndef __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ #define __MAINBOARD_GOOGLE_URARA_URARA_BOARDID_H__ +#include <stdint.h> + /* * List of URARA derivatives board ID definitions. They are stored in uint8_t * across the code, using #defines here not to imply any specific size. diff --git a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h +++ b/src/mainboard/iei/kino-780am2-fam10/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/mainboard/pcengines/apu1/gpio_ftns.h b/src/mainboard/pcengines/apu1/gpio_ftns.h index 8eadebd..fce8afe 100644 --- a/src/mainboard/pcengines/apu1/gpio_ftns.h +++ b/src/mainboard/pcengines/apu1/gpio_ftns.h @@ -16,6 +16,8 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H +#include <stdint.h> + uintptr_t find_gpio_base(void); void configure_gpio(uintptr_t base_addr, u32 gpio, u8 iomux_ftn, u8 setting); u8 read_gpio(uintptr_t base_addr, u32 gpio); diff --git a/src/mainboard/pcengines/apu2/gpio_ftns.h b/src/mainboard/pcengines/apu2/gpio_ftns.h index 24d6a7f..ff22a0c 100644 --- a/src/mainboard/pcengines/apu2/gpio_ftns.h +++ b/src/mainboard/pcengines/apu2/gpio_ftns.h @@ -16,6 +16,8 @@ #ifndef GPIO_FTNS_H #define GPIO_FTNS_H +#include <stdint.h> + void configure_gpio(u32 iomux_gpio, u8 iomux_ftn, u32 gpio, u32 setting); u8 read_gpio(u32 gpio); void write_gpio(u32 gpio, u8 value); diff --git a/src/mainboard/scaleway/tagada/bmcinfo.h b/src/mainboard/scaleway/tagada/bmcinfo.h index 8e64a84..723a348 100644 --- a/src/mainboard/scaleway/tagada/bmcinfo.h +++ b/src/mainboard/scaleway/tagada/bmcinfo.h @@ -16,6 +16,8 @@ #ifndef MAINBOARD_BMCINFO_H #define MAINBOARD_BMCINFO_H +#include <stdint.h> + // Do not place disks in boot order #define BOOT_OPTION_NIC_ONLY 0 // Boot to disk first (before network) diff --git a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h index 5986116..7f111fd 100644 --- a/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h +++ b/src/mainboard/supermicro/h8scm_fam10/mb_sysconf.h @@ -14,9 +14,10 @@ */ #ifndef MB_SYSCONF_H - #define MB_SYSCONF_H +#include <stdint.h> + struct mb_sysconf_t { u8 bus_isa; u8 bus_8132_0; diff --git a/src/northbridge/amd/amdfam10/ht_config.h b/src/northbridge/amd/amdfam10/ht_config.h index 748a981..cb814bd 100644 --- a/src/northbridge/amd/amdfam10/ht_config.h +++ b/src/northbridge/amd/amdfam10/ht_config.h @@ -16,6 +16,8 @@ #ifndef __AMDFAM10_HT_CONFIG_H__ #define __AMDFAM10_HT_CONFIG_H__ +#include <stdint.h> + typedef struct amdfam10_sysconf_t sys_info_conf_t; /* FIXME */ diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 1a44208..8dedfd7 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -16,6 +16,8 @@ #ifndef AMDDEFS_H #define AMDDEFS_H +#include <stdint.h> + /* FIXME: this file should be moved to include/cpu/amd/amddefs.h */ /* Public Revisions - USE THESE VERSIONS TO MAKE COMPARE WITH CPULOGICALID RETURN VALUE*/ diff --git a/src/northbridge/intel/e7505/raminit.h b/src/northbridge/intel/e7505/raminit.h index 1581b82..cdfc92a 100644 --- a/src/northbridge/intel/e7505/raminit.h +++ b/src/northbridge/intel/e7505/raminit.h @@ -14,6 +14,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <stdint.h> + #define MAX_DIMM_SOCKETS_PER_CHANNEL 4 #define MAX_NUM_CHANNELS 2 #define MAX_DIMM_SOCKETS (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL) diff --git a/src/northbridge/intel/haswell/pei_data.h b/src/northbridge/intel/haswell/pei_data.h index 319b9e7..dfc34d8 100644 --- a/src/northbridge/intel/haswell/pei_data.h +++ b/src/northbridge/intel/haswell/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <stdint.h> + typedef void (*tx_byte_func)(unsigned char byte); #define PEI_VERSION 15 diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 98bdc02..cb8c0b3 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -16,6 +16,8 @@ #ifndef RAMINIT_H #define RAMINIT_H +#include <stdint.h> + #define DIMM_SOCKETS 2 #define DIMM_TCO_BASE 0x30 diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 5b10920..24d16c5 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -16,6 +16,8 @@ #ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H #define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H +#include <stdint.h> + struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 00534ca..0a60707 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -30,6 +30,8 @@ #ifndef PEI_DATA_H #define PEI_DATA_H +#include <stdint.h> + typedef struct { uint16_t mode; // 0: Disable, 1: Enable, 2: Auto, 3: Smart Auto uint16_t hs_port_switch_mask; // 4 bit mask, 1: switchable, 0: not switchable diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 317071c..afffbb0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -18,6 +18,8 @@ #ifndef RAMINIT_COMMON_H #define RAMINIT_COMMON_H +#include <stdint.h> + #define BASEFREQ 133 #define tDLLK 512 diff --git a/src/northbridge/intel/sandybridge/raminit_patterns.h b/src/northbridge/intel/sandybridge/raminit_patterns.h index 01183f1..a1d9f04 100644 --- a/src/northbridge/intel/sandybridge/raminit_patterns.h +++ b/src/northbridge/intel/sandybridge/raminit_patterns.h @@ -14,6 +14,8 @@ #ifndef SANDYBRIDGE_RAMINIT_PATTERNS_H #define SANDYBRIDGE_RAMINIT_PATTERNS_H +#include <stdint.h> + const u32 pattern[][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, diff --git a/src/security/tpm/tss/tcg-1.2/tss_commands.h b/src/security/tpm/tss/tcg-1.2/tss_commands.h index 9d30bfc..acdc8be 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_commands.h +++ b/src/security/tpm/tss/tcg-1.2/tss_commands.h @@ -14,6 +14,8 @@ * GNU General Public License for more details. */ +#include <stdint.h> + const struct s_tpm_extend_cmd{ uint8_t buffer[34]; uint16_t pcrNum; diff --git a/src/security/tpm/tss/tcg-1.2/tss_internal.h b/src/security/tpm/tss/tcg-1.2/tss_internal.h index 01912bb..e999cb9 100644 --- a/src/security/tpm/tss/tcg-1.2/tss_internal.h +++ b/src/security/tpm/tss/tcg-1.2/tss_internal.h @@ -6,6 +6,8 @@ #ifndef TCG_TSS_INTERNAL_H_ #define TCG_TSS_INTERNAL_H_ +#include <stdint.h> + /* * These numbers derive from adding the sizes of command fields as shown in the * TPM commands manual. diff --git a/src/security/tpm/tss_errors.h b/src/security/tpm/tss_errors.h index c80ffa1..316661c 100644 --- a/src/security/tpm/tss_errors.h +++ b/src/security/tpm/tss_errors.h @@ -12,6 +12,8 @@ #ifndef TSS_ERRORS_H_ #define TSS_ERRORS_H_ +#include <stdint.h> + #define TPM_E_BASE 0x0 #define TPM_E_NON_FATAL 0x800 diff --git a/src/soc/broadcom/cygnus/include/soc/tz.h b/src/soc/broadcom/cygnus/include/soc/tz.h index a6777fd..1d5d234 100644 --- a/src/soc/broadcom/cygnus/include/soc/tz.h +++ b/src/soc/broadcom/cygnus/include/soc/tz.h @@ -14,6 +14,8 @@ #ifndef __SOC_BROADCOM_CYGNUS_TZ_H__ #define __SOC_BROADCOM_CYGNUS_TZ_H__ +#include <stdint.h> + #define TZ_STATE_SECURE 0 #define TZ_STATE_NON_SECURE 1 diff --git a/src/soc/cavium/cn81xx/include/soc/cpu.h b/src/soc/cavium/cn81xx/include/soc/cpu.h index b2472d7..1c6a30d 100644 --- a/src/soc/cavium/cn81xx/include/soc/cpu.h +++ b/src/soc/cavium/cn81xx/include/soc/cpu.h @@ -17,6 +17,8 @@ #ifndef __SOC_CAVIUM_CN81XX_CPU_H__ #define __SOC_CAVIUM_CN81XX_CPU_H__ +#include <stdint.h> + /** * Number of the Core on which the program is currently running. * diff --git a/src/soc/cavium/common/include/soc/bootblock.h b/src/soc/cavium/common/include/soc/bootblock.h index 76fd4a15..1df444f 100644 --- a/src/soc/cavium/common/include/soc/bootblock.h +++ b/src/soc/cavium/common/include/soc/bootblock.h @@ -16,6 +16,8 @@ #ifndef SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ #define SRC_SOC_CAVIUM_COMMON_INCLUDE_SOC_BOOTBLOCK_H_ +#include <stdint.h> + void bootblock_mainboard_early_init(void); void bootblock_soc_early_init(void); void bootblock_soc_init(void); diff --git a/src/soc/intel/apollolake/include/soc/usb.h b/src/soc/intel/apollolake/include/soc/usb.h index 7220023..7dd9ec0 100644 --- a/src/soc/intel/apollolake/include/soc/usb.h +++ b/src/soc/intel/apollolake/include/soc/usb.h @@ -18,6 +18,8 @@ #ifndef _SOC_APOLLOLAKE_USB_H_ #define _SOC_APOLLOLAKE_USB_H_ +#include <stdint.h> + #define APOLLOLAKE_USB2_PORT_MAX 8 struct usb2_eye_per_port { diff --git a/src/soc/intel/broadwell/chip.h b/src/soc/intel/broadwell/chip.h index 46c2c1d..0885c2d 100644 --- a/src/soc/intel/broadwell/chip.h +++ b/src/soc/intel/broadwell/chip.h @@ -17,6 +17,8 @@ #ifndef _SOC_INTEL_BROADWELL_CHIP_H_ #define _SOC_INTEL_BROADWELL_CHIP_H_ +#include <stdint.h> + struct soc_intel_broadwell_config { /* * Interrupt Routing configuration diff --git a/src/soc/intel/broadwell/include/soc/igd.h b/src/soc/intel/broadwell/include/soc/igd.h index cdbee4b..31f75cf 100644 --- a/src/soc/intel/broadwell/include/soc/igd.h +++ b/src/soc/intel/broadwell/include/soc/igd.h @@ -14,6 +14,8 @@ #ifndef SOC_INTEL_BROADWELL_GMA_H #define SOC_INTEL_BROADWELL_GMA_H +#include <stdint.h> + u32 igd_get_reg_em4(void); u32 igd_get_reg_em5(void); diff --git a/src/soc/intel/broadwell/include/soc/iobp.h b/src/soc/intel/broadwell/include/soc/iobp.h index 7734601..22012b9 100644 --- a/src/soc/intel/broadwell/include/soc/iobp.h +++ b/src/soc/intel/broadwell/include/soc/iobp.h @@ -16,6 +16,8 @@ #ifndef _BROADWELL_IOBP_H_ #define _BROADWELL_IOBP_H_ +#include <stdint.h> + u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); diff --git a/src/soc/intel/broadwell/include/soc/pch.h b/src/soc/intel/broadwell/include/soc/pch.h index 19ba2e0b..4066af5 100644 --- a/src/soc/intel/broadwell/include/soc/pch.h +++ b/src/soc/intel/broadwell/include/soc/pch.h @@ -17,6 +17,8 @@ #ifndef _BROADWELL_PCH_H_ #define _BROADWELL_PCH_H_ +#include <stdint.h> + /* Haswell ULT Pch (LynxPoint-LP) */ #define PCH_LPT_LP_SAMPLE 0x9c41 #define PCH_LPT_LP_PREMIUM 0x9c43 diff --git a/src/soc/intel/cannonlake/include/soc/ebda.h b/src/soc/intel/cannonlake/include/soc/ebda.h index 15a9d28..ad62394 100644 --- a/src/soc/intel/cannonlake/include/soc/ebda.h +++ b/src/soc/intel/cannonlake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/denverton_ns/chip.h b/src/soc/intel/denverton_ns/chip.h index bfa6a01..f2a67dd 100644 --- a/src/soc/intel/denverton_ns/chip.h +++ b/src/soc/intel/denverton_ns/chip.h @@ -17,6 +17,8 @@ #ifndef SOC_INTEL_DENVERTON_NS_CHIP_H #define SOC_INTEL_DENVERTON_NS_CHIP_H +#include <stdint.h> + struct soc_intel_denverton_ns_config { /** * Interrupt Routing configuration diff --git a/src/soc/intel/icelake/include/soc/ebda.h b/src/soc/intel/icelake/include/soc/ebda.h index 9c44a50..f4d89e9 100644 --- a/src/soc/intel/icelake/include/soc/ebda.h +++ b/src/soc/intel/icelake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/quark/include/soc/i2c.h b/src/soc/intel/quark/include/soc/i2c.h index 85ae7b9..f3c585f 100644 --- a/src/soc/intel/quark/include/soc/i2c.h +++ b/src/soc/intel/quark/include/soc/i2c.h @@ -16,6 +16,8 @@ #ifndef _QUARK_I2C_H_ #define _QUARK_I2C_H_ +#include <stdint.h> + typedef volatile struct _I2C_REGS { volatile uint32_t ic_con; /* 00: Control Register */ volatile uint32_t ic_tar; /* 04: Master Target Address */ diff --git a/src/soc/intel/skylake/include/soc/ebda.h b/src/soc/intel/skylake/include/soc/ebda.h index 15a9d28..ad62394 100644 --- a/src/soc/intel/skylake/include/soc/ebda.h +++ b/src/soc/intel/skylake/include/soc/ebda.h @@ -16,6 +16,8 @@ #ifndef SOC_EBDA_H #define SOC_EBDA_H +#include <stdint.h> + struct ebda_config { uint32_t signature; /* 0x00 - EBDA signature */ uint32_t tolum_base; /* 0x04 - coreboot memory start */ diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5a9acd5..0a65875 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -18,6 +18,8 @@ #ifndef _SKYLAKE_ME_H_ #define _SKYLAKE_ME_H_ +#include <stdint.h> + /* * Management Engine PCI registers */ diff --git a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h index 2dd1f9f..602c75c 100644 --- a/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h +++ b/src/soc/nvidia/tegra210/include/soc/flow_ctrl.h @@ -16,6 +16,8 @@ #ifndef _TEGRA210_FLOW_CTRL_H_ #define _TEGRA210_FLOW_CTRL_H_ +#include <stdint.h> + void flowctrl_cpu_off(int cpu); void flowctrl_cpu_on(int cpu); void flowctrl_cpu_suspend(int cpu); diff --git a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h index 3e99c3b..5dcd9b8 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/ebi2.h +++ b/src/soc/qualcomm/ipq806x/include/soc/ebi2.h @@ -19,6 +19,8 @@ #ifndef __SOC_QUALCOMM_IPQ806X_EBI2_H_ #define __SOC_QUALCOMM_IPQ806X_EBI2_H_ +#include <stdint.h> + #define EBI2CR_BASE (0x1A600000) struct ebi2cr_regs { diff --git a/src/soc/sifive/fu540/include/soc/otp.h b/src/soc/sifive/fu540/include/soc/otp.h index a5b4ca8..325871a 100644 --- a/src/soc/sifive/fu540/include/soc/otp.h +++ b/src/soc/sifive/fu540/include/soc/otp.h @@ -16,6 +16,8 @@ #ifndef __SOC_SIFIVE_HIFIVE_U_OTP_H__ #define __SOC_SIFIVE_HIFIVE_U_OTP_H__ +#include <stdint.h> + u32 otp_read_word(u16 idx); u32 otp_read_serial(void); diff --git a/src/southbridge/amd/cimx/sb800/gpio_oem.h b/src/southbridge/amd/cimx/sb800/gpio_oem.h index 9063b2b..7c7faae 100644 --- a/src/southbridge/amd/cimx/sb800/gpio_oem.h +++ b/src/southbridge/amd/cimx/sb800/gpio_oem.h @@ -14,6 +14,8 @@ #ifndef _CIMX_SB_GPIO_OEM_H_ #define _CIMX_SB_GPIO_OEM_H_ +#include <stdint.h> + #define SB_GPIO_REG02 2 #define SB_GPIO_REG09 9 #define SB_GPIO_REG10 10 diff --git a/src/southbridge/amd/cimx/sb900/chip.h b/src/southbridge/amd/cimx/sb900/chip.h index 73561c0..69357b7 100644 --- a/src/southbridge/amd/cimx/sb900/chip.h +++ b/src/southbridge/amd/cimx/sb900/chip.h @@ -16,6 +16,8 @@ #ifndef _CIMX_SB900_CHIP_H_ #define _CIMX_SB900_CHIP_H_ +#include <stdint.h> + /* * configuration set in mainboard/devicetree.cb * boot_switch_sata_ide: diff --git a/src/southbridge/amd/pi/hudson/chip.h b/src/southbridge/amd/pi/hudson/chip.h index 511b586..ded7b0d 100644 --- a/src/southbridge/amd/pi/hudson/chip.h +++ b/src/southbridge/amd/pi/hudson/chip.h @@ -16,6 +16,8 @@ #ifndef HUDSON_CHIP_H #define HUDSON_CHIP_H +#include <stdint.h> + struct southbridge_amd_pi_hudson_config { u32 ide0_enable : 1; diff --git a/src/southbridge/amd/rs780/chip.h b/src/southbridge/amd/rs780/chip.h index ca86a67..93f2763 100644 --- a/src/southbridge/amd/rs780/chip.h +++ b/src/southbridge/amd/rs780/chip.h @@ -16,6 +16,8 @@ #ifndef RS780_CHIP_H #define RS780_CHIP_H +#include <stdint.h> + /* Member variables are defined in devicetree.cb. */ struct southbridge_amd_rs780_config { diff --git a/src/southbridge/amd/sb700/pmio.h b/src/southbridge/amd/sb700/pmio.h index ed38eed..c5a80f8 100644 --- a/src/southbridge/amd/sb700/pmio.h +++ b/src/southbridge/amd/sb700/pmio.h @@ -17,6 +17,8 @@ #ifndef _PMIO_H_ #define _PMIO_H_ +#include <stdint.h> + #define PM_INDEX 0xCD6 #define PM_DATA 0xCD7 #define PM2_INDEX 0xCD0 diff --git a/src/southbridge/amd/sb800/chip.h b/src/southbridge/amd/sb800/chip.h index f773977..9a63fa9 100644 --- a/src/southbridge/amd/sb800/chip.h +++ b/src/southbridge/amd/sb800/chip.h @@ -16,6 +16,8 @@ #ifndef SB800_CHIP_H #define SB800_CHIP_H +#include <stdint.h> + struct southbridge_amd_sb800_config { u32 ide0_enable : 1; diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index ce8a804..29f6881 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_BD82X6X_CHIP_H +#include <stdint.h> + struct southbridge_intel_bd82x6x_config { /** * GPI Routing configuration diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 2708864..7f7526a 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -17,6 +17,8 @@ #ifndef _INTEL_ME_H #define _INTEL_ME_H +#include <stdint.h> + #define ME_RETRY 100000 /* 1 second */ #define ME_DELAY 10 /* 10 us */ diff --git a/src/southbridge/intel/common/smbus.h b/src/southbridge/intel/common/smbus.h index be1aa76..0312c93 100644 --- a/src/southbridge/intel/common/smbus.h +++ b/src/southbridge/intel/common/smbus.h @@ -18,6 +18,8 @@ #ifndef INTEL_COMMON_SMBUS_H #define INTEL_COMMON_SMBUS_H +#include <stdint.h> + /* SMBus register offsets. */ #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 diff --git a/src/southbridge/intel/fsp_bd82x6x/chip.h b/src/southbridge/intel/fsp_bd82x6x/chip.h index 9d6a9e4..8da3936 100644 --- a/src/southbridge/intel/fsp_bd82x6x/chip.h +++ b/src/southbridge/intel/fsp_bd82x6x/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H #define SOUTHBRIDGE_INTEL_FSP_BD82X6X_CHIP_H +#include <stdint.h> + struct southbridge_intel_fsp_bd82x6x_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/fsp_i89xx/chip.h b/src/southbridge/intel/fsp_i89xx/chip.h index 69e1dc7..bea3e07 100644 --- a/src/southbridge/intel/fsp_i89xx/chip.h +++ b/src/southbridge/intel/fsp_i89xx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I89XX_CHIP_H #define SOUTHBRIDGE_INTEL_I89XX_CHIP_H +#include <stdint.h> + struct southbridge_intel_fsp_i89xx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801dx/chip.h b/src/southbridge/intel/i82801dx/chip.h index f77413d..a0961ee 100644 --- a/src/southbridge/intel/i82801dx/chip.h +++ b/src/southbridge/intel/i82801dx/chip.h @@ -17,6 +17,8 @@ #ifndef I82801DX_CHIP_H #define I82801DX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801dx_config { int enable_usb; int enable_native_ide; diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index e89fcc4..3a20ab1 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801GX_CHIP_H +#include <stdint.h> + struct southbridge_intel_i82801gx_config { /** * Interrupt Routing configuration diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index 307b751..0b3e0b5 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H +#include <stdint.h> + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 533254a..1712b81 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -17,6 +17,8 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H +#include <stdint.h> + enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7 diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index d11ce5f..09f1c90 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -16,6 +16,8 @@ #ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H #define SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H +#include <stdint.h> + struct southbridge_intel_lynxpoint_config { /** * Interrupt Routing configuration diff --git a/src/superio/nuvoton/npcd378/npcd378.h b/src/superio/nuvoton/npcd378/npcd378.h index 53541a9..cf0b804 100644 --- a/src/superio/nuvoton/npcd378/npcd378.h +++ b/src/superio/nuvoton/npcd378/npcd378.h @@ -17,6 +17,8 @@ #ifndef SUPERIO_NUVOTON_NPCD378_H #define SUPERIO_NUVOTON_NPCD378_H +#include <stdint.h> + /* HWM at LDN8 */ #define NPCD837_HWM_WRITE_LOCK_CTRL 0x4 #define NPCD837_HWM_WRITE_LOCK_BIT 0x1 diff --git a/src/superio/nuvoton/wpcm450/wpcm450.h b/src/superio/nuvoton/wpcm450/wpcm450.h index 6efdb2a..8172037 100644 --- a/src/superio/nuvoton/wpcm450/wpcm450.h +++ b/src/superio/nuvoton/wpcm450/wpcm450.h @@ -17,6 +17,8 @@ #ifndef SUPERIO_NUVOTON_WPCM450_WPCM450_H #define SUPERIO_NUVOTON_WPCM450_WPCM450_H +#include <stdint.h> + #define WPCM450_SP2 0x02 /* Com2 */ #define WPCM450_SP1 0x03 /* Com1 */ #define WPCM450_KBCK 0x06 /* Keyboard */ diff --git a/src/superio/smsc/sio1007/chip.h b/src/superio/smsc/sio1007/chip.h index 78ac18a..ad61ead 100644 --- a/src/superio/smsc/sio1007/chip.h +++ b/src/superio/smsc/sio1007/chip.h @@ -16,6 +16,8 @@ #ifndef SUPERIO_SMSC_1007_CHIP_H #define SUPERIO_SMSC_1007_CHIP_H +#include <stdint.h> + /* FIXME: wrong place for this! */ void sio1007_setreg(u16 lpc_port, u8 reg, u8 value, u8 mask); int sio1007_enable_uart_at(u16 port); -- To view, visit https://review.coreboot.org/29405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf0fa38daf858bcd668962f14ffcbaf359113413 Gerrit-Change-Number: 29405 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29403 to look at the new patch set (#5). Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> This is part #2 follows Change-Id: I6a9d71e69 Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common.h M src/cpu/intel/haswell/chip.h M src/device/oprom/yabel/compat/time.h M src/drivers/pc80/tpm/chip.h M src/ec/smsc/mec1308/chip.h M src/include/device/path.h M src/include/device/pcix.h M src/mainboard/google/parrot/ec.h M src/mainboard/roda/rk886ex/m3885.h M src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h M src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h M src/mainboard/siemens/mc_tcu3/lcd_panel.h M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/agesa/family15tn/chip.h M src/northbridge/amd/agesa/family16kb/chip.h M src/northbridge/amd/amdfam10/northbridge.h M src/northbridge/amd/amdht/AsPsNb.h M src/northbridge/amd/pi/00630F01/chip.h M src/northbridge/amd/pi/00660F01/chip.h M src/northbridge/amd/pi/00730F01/chip.h M src/northbridge/intel/pineview/raminit.h M src/northbridge/intel/x4x/iomap.h M src/soc/cavium/common/pci/chip.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/nvidia/tegra210/include/soc/display.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/rockchip/common/include/soc/pwm.h M src/soc/rockchip/rk3288/include/soc/display.h M src/soc/rockchip/rk3399/include/soc/saradc.h M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h M src/southbridge/amd/agesa/hudson/chip.h M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb900/sb_cimx.h M src/southbridge/amd/sb700/chip.h M src/superio/fintek/f81216h/f81216h.h M src/superio/nuvoton/nct5104d/chip.h M src/superio/serverengines/pilot/pilot.h M src/superio/smsc/lpc47n227/lpc47n227.h 39 files changed, 79 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/5 -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Bora Guvendik (Code Review) 31 Oct '18

31 Oct '18

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/29274 ) Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 18:40:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29403 to look at the new patch set (#4). Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> This is part #2 follows Change-Id: I6a9d71e69 Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/intel/common/common.h M src/cpu/intel/haswell/chip.h M src/device/oprom/yabel/compat/time.h M src/drivers/pc80/tpm/chip.h M src/ec/smsc/mec1308/chip.h M src/include/device/path.h M src/include/device/pcix.h M src/mainboard/google/parrot/ec.h M src/mainboard/roda/rk886ex/m3885.h M src/mainboard/roda/rv11/variants/rv11/include/variant/hda_verb.h M src/mainboard/roda/rv11/variants/rw11/include/variant/hda_verb.h M src/mainboard/siemens/mc_tcu3/lcd_panel.h M src/northbridge/amd/agesa/family14/chip.h M src/northbridge/amd/agesa/family15tn/chip.h M src/northbridge/amd/agesa/family16kb/chip.h M src/northbridge/amd/amdfam10/northbridge.h M src/northbridge/amd/amdht/AsPsNb.h M src/northbridge/amd/pi/00630F01/chip.h M src/northbridge/amd/pi/00660F01/chip.h M src/northbridge/amd/pi/00730F01/chip.h M src/northbridge/intel/pineview/raminit.h M src/northbridge/intel/x4x/iomap.h M src/soc/cavium/common/pci/chip.h M src/soc/intel/broadwell/include/soc/xhci.h M src/soc/nvidia/tegra210/include/soc/display.h M src/soc/nvidia/tegra210/include/soc/tegra_dsi.h M src/soc/rockchip/common/include/soc/pwm.h M src/soc/rockchip/rk3288/include/soc/display.h M src/soc/rockchip/rk3399/include/soc/saradc.h M src/soc/samsung/exynos5250/include/soc/alternate_cbfs.h M src/soc/samsung/exynos5420/include/soc/alternate_cbfs.h M src/southbridge/amd/agesa/hudson/chip.h M src/southbridge/amd/cimx/sb800/sb_cimx.h M src/southbridge/amd/cimx/sb900/sb_cimx.h M src/southbridge/amd/sb700/chip.h M src/superio/fintek/f81216h/f81216h.h M src/superio/nuvoton/nct5104d/chip.h M src/superio/serverengines/pilot/pilot.h M src/superio/smsc/lpc47n227/lpc47n227.h 39 files changed, 79 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/29403/4 -- To view, visit https://review.coreboot.org/29403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543 Gerrit-Change-Number: 29403 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Pratikkumar V Prajapati (Code Review) 31 Oct '18

31 Oct '18

Pratikkumar V Prajapati has posted comments on this change. ( https://review.coreboot.org/29274 ) Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 18:33:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Lijian Zhao (Code Review) 31 Oct '18

31 Oct '18

Hello Pratikkumar V Prajapati, Subrata Banik, Kyoung Il Kim, Li1 Feng, Bora Guvendik, build bot (Jenkins), Hannah Williams, Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29274 to look at the new patch set (#4). Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... soc/intel/cannonlake: Enable ISH from device PCH ISH enabled/disabled in FSP memory init UPD, it will be match the setting in ISH device on/off in devicetree.cb. BUG=N/A TEST=Build and pass on whiskey lake rvp platform. Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29274/4 -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 4 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Lijian Zhao (Code Review) 31 Oct '18

31 Oct '18

Hello Pratikkumar V Prajapati, Subrata Banik, Kyoung Il Kim, Li1 Feng, Bora Guvendik, Hannah Williams, build bot (Jenkins), Krzysztof M Sywula, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29274 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... soc/intel/cannonlake: Enable ISH from device PCH ISH enabled/disabled in FSP memory init UPD, it will be match the setting in ISH device on/off in devicetree.cb. BUG=N/A TEST=Build and pass on whiskey lake rvp platform. Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Signed-off-by: Lijian Zhao <lijian.zhao(a)intel.com> --- M src/soc/intel/cannonlake/romstage/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29274/3 -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 3 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018