October 2018 - coreboot-gerrit

Change in coreboot[master]: sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29389 Change subject: sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors ...................................................................... sb/intel/lynxpoint: Include <stdint.h> to fix compilation errors If the file `southbridge/intel/lynxpoint/nvs.h` is included in a file that does not already include <stdint.h>, compilation errors result. Adding the necessary <stdint.h> inclusions fixes compilation for an ASRock H81M-HDS. Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/nvs.h M src/vendorcode/google/chromeos/gnvs.h 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/29389/1 diff --git a/src/southbridge/intel/lynxpoint/nvs.h b/src/southbridge/intel/lynxpoint/nvs.h index 397cdf2..a8f0dea 100644 --- a/src/southbridge/intel/lynxpoint/nvs.h +++ b/src/southbridge/intel/lynxpoint/nvs.h @@ -15,6 +15,7 @@ */ #include <commonlib/helpers.h> +#include <stdint.h> #include "vendorcode/google/chromeos/gnvs.h" typedef struct global_nvs_t { diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 7e97bfa..76ca20c 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -16,6 +16,8 @@ #ifndef __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H #define __VENDORCODE_GOOGLE_CHROMEOS_GNVS_H +#include <stdint.h> + #define BOOT_REASON_OTHER 0 #define BOOT_REASON_S3DIAG 9 -- To view, visit https://review.coreboot.org/29389 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id0d14705282cc959146e00dd47754ee8a2e8e825 Gerrit-Change-Number: 29389 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Generate the ACPI FADT with a common function
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29387 Change subject: sb/intel/lynxpoint: Generate the ACPI FADT with a common function ...................................................................... sb/intel/lynxpoint: Generate the ACPI FADT with a common function The function `acpi_fill_fadt()` is based on that of sb/intel/bd82x6x. Tested on an ASRock H81M-HDS and a Google Peppy board, both using Linux 4.9 with `acpi=strict`. No ACPI errors or warnings appear in the kernel log. System reset, poweroff, and S3 suspend/resume continue to work. General improvements -------------------- - `fadt->preferred_pm_profile` is set based on the value of `CONFIG_SYSTEM_TYPE_LAPTOP` instead of being hardcoded. - Constants are used instead of magic values in more locations. - `fadt->gpe0_blk`, `fadt->gpe0_blk_len`, and `fadt->x_gpe0_blk` are set appropriately depending on whether the system uses Lynx Point LP or not. - The C2 and C3 latencies can be set in the devicetree. If unset, the FADT will indicate that the C-state is unsupported. - Boards can indicate docking support in the FADT via the devicetree. Changes to existing Lynx Point boards ------------------------------------- - `header->asl_compiler_revision` changes from 1 to 0. - `fadt->model` is left at 0 instead of being set to 1. This field is only needed for ACPI 1.0 compatibility. - `fadt->flush_size` and `fadt->flush_stride` are set to 0. This is because their values are ignored, since `ACPI_FADT_WBINVD` is set in `fadt->flags`. - `fadt->duty_offset` is set to 0 instead of 1. None of the existing boards indicate support for changing the processor duty cycle (as `fadt->duty_width` is set to 0), so `fadt->duty_offset` does not currently need to be set. - Access sizes of registers are set. - On mb/intel/baskingridge, the pmbase is now read using the common function `get_pmbase()` instead of `pci_read_config16(...)`. - On mb/intel/baskingridge, the value of `fadt->x_gpe0_blk.bit_width` changes from 64 to 128. The correct value should be 128 (bits), to match `fadt->gpe0_blk_len`, which is set to 16 (bytes). - On Lynx Point LP systems, the unused extended address `fadt->x_gpe0_blk` sets its address space ID to be consistent with other unused extended addresses. Such a change should not alter the interpretation of the registers as being unused. Why not set them all to zero? Simply because the existing practice, in both coreboot and some other vendors' firmware, has them set in such a case. A diff of the FADT from a Google Peppy board is below: --- pre/facp.dsl 2018-10-30 20:14:52.676570798 +1300 +++ post/facp.dsl 2018-10-30 20:15:06.904381436 +1300 @@ -1,179 +1,179 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180810 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * - * Disassembly of facp.dat, Tue Oct 30 20:14:52 2018 + * Disassembly of facp.dat, Tue Oct 30 20:15:06 2018 * * ACPI Data Table [FACP] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] [004h 0004 4] Table Length : 000000F4 [008h 0008 1] Revision : 04 -[009h 0009 1] Checksum : 61 +[009h 0009 1] Checksum : 6E [00Ah 0010 6] Oem ID : "CORE " [010h 0016 8] Oem Table ID : "COREBOOT" [018h 0024 4] Oem Revision : 00000000 [01Ch 0028 4] Asl Compiler ID : "CORE" -[020h 0032 4] Asl Compiler Revision : 00000001 +[020h 0032 4] Asl Compiler Revision : 00000000 [024h 0036 4] FACS Address : 7BF46240 [028h 0040 4] DSDT Address : 7BF46280 -[02Ch 0044 1] Model : 01 +[02Ch 0044 1] Model : 00 [02Dh 0045 1] PM Profile : 02 [Mobile] [02Eh 0046 2] SCI Interrupt : 0009 [030h 0048 4] SMI Command Port : 000000B2 [034h 0052 1] ACPI Enable Value : E1 [035h 0053 1] ACPI Disable Value : 1E [036h 0054 1] S4BIOS Command : 00 [037h 0055 1] P-State Control : 00 [038h 0056 4] PM1A Event Block Address : 00001000 [03Ch 0060 4] PM1B Event Block Address : 00000000 [040h 0064 4] PM1A Control Block Address : 00001004 [044h 0068 4] PM1B Control Block Address : 00000000 [048h 0072 4] PM2 Control Block Address : 00001050 [04Ch 0076 4] PM Timer Block Address : 00001008 [050h 0080 4] GPE0 Block Address : 00001080 [054h 0084 4] GPE1 Block Address : 00000000 [058h 0088 1] PM1 Event Block Length : 04 [059h 0089 1] PM1 Control Block Length : 02 [05Ah 0090 1] PM2 Control Block Length : 01 [05Bh 0091 1] PM Timer Block Length : 04 [05Ch 0092 1] GPE0 Block Length : 20 [05Dh 0093 1] GPE1 Block Length : 00 [05Eh 0094 1] GPE1 Base Offset : 00 [05Fh 0095 1] _CST Support : 00 [060h 0096 2] C2 Latency : 0001 [062h 0098 2] C3 Latency : 0057 -[064h 0100 2] CPU Cache Size : 0400 -[066h 0102 2] Cache Flush Stride : 0010 -[068h 0104 1] Duty Cycle Offset : 01 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 [069h 0105 1] Duty Cycle Width : 00 [06Ah 0106 1] RTC Day Alarm Index : 0D [06Bh 0107 1] RTC Month Alarm Index : 00 [06Ch 0108 1] RTC Century Index : 00 [06Dh 0109 2] Boot Flags (decoded below) : 0003 Legacy Devices Supported (V2) : 1 8042 Present on ports 60/64 (V2) : 1 VGA Not Present (V4) : 0 MSI Not Supported (V4) : 0 PCIe ASPM Not Supported (V4) : 0 CMOS RTC Not Present (V5) : 0 [06Fh 0111 1] Reserved : 00 [070h 0112 4] Flags (decoded below) : 00008CAD WBINVD instruction is operational (V1) : 1 WBINVD flushes all caches (V1) : 0 All CPUs support C1 (V1) : 1 C2 works on MP system (V1) : 1 Control Method Power Button (V1) : 0 Control Method Sleep Button (V1) : 1 RTC wake not in fixed reg space (V1) : 0 RTC can wake system from S4 (V1) : 1 32-bit PM Timer (V1) : 0 Docking Supported (V1) : 0 Reset Register Supported (V2) : 1 Sealed Case (V3) : 1 Headless - No Video (V3) : 0 Use native instr after SLP_TYPx (V3) : 0 PCIEXP_WAK Bits Supported (V4) : 0 Use Platform Timer (V4) : 1 RTC_STS valid on S4 wake (V4) : 0 Remote Power-on capable (V4) : 0 Use APIC Cluster Model (V4) : 0 Use APIC Physical Destination Mode (V4) : 0 Hardware Reduced (V5) : 0 Low Power S0 Idle (V5) : 0 [074h 0116 12] Reset Register : [Generic Address Structure] [074h 0116 1] Space ID : 01 [SystemIO] [075h 0117 1] Bit Width : 08 [076h 0118 1] Bit Offset : 00 -[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[077h 0119 1] Encoded Access Width : 01 [Byte Access:8] [078h 0120 8] Address : 0000000000000CF9 [080h 0128 1] Value to cause reset : 06 [081h 0129 2] ARM Flags (decoded below) : 0000 PSCI Compliant : 0 Must use HVC for PSCI : 0 [083h 0131 1] FADT Minor Revision : 00 [084h 0132 8] FACS Address : 000000007BF46240 [08Ch 0140 8] DSDT Address : 000000007BF46280 [094h 0148 12] PM1A Event Block : [Generic Address Structure] [094h 0148 1] Space ID : 01 [SystemIO] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 -[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[097h 0151 1] Encoded Access Width : 02 [Word Access:16] [098h 0152 8] Address : 0000000000001000 [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] [0A0h 0160 1] Space ID : 01 [SystemIO] [0A1h 0161 1] Bit Width : 00 [0A2h 0162 1] Bit Offset : 00 [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] [0A4h 0164 8] Address : 0000000000000000 [0ACh 0172 12] PM1A Control Block : [Generic Address Structure] [0ACh 0172 1] Space ID : 01 [SystemIO] [0ADh 0173 1] Bit Width : 10 [0AEh 0174 1] Bit Offset : 00 -[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0AFh 0175 1] Encoded Access Width : 02 [Word Access:16] [0B0h 0176 8] Address : 0000000000001004 [0B8h 0184 12] PM1B Control Block : [Generic Address Structure] [0B8h 0184 1] Space ID : 01 [SystemIO] [0B9h 0185 1] Bit Width : 00 [0BAh 0186 1] Bit Offset : 00 [0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] [0BCh 0188 8] Address : 0000000000000000 [0C4h 0196 12] PM2 Control Block : [Generic Address Structure] [0C4h 0196 1] Space ID : 01 [SystemIO] [0C5h 0197 1] Bit Width : 08 [0C6h 0198 1] Bit Offset : 00 -[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C7h 0199 1] Encoded Access Width : 01 [Byte Access:8] [0C8h 0200 8] Address : 0000000000001050 [0D0h 0208 12] PM Timer Block : [Generic Address Structure] [0D0h 0208 1] Space ID : 01 [SystemIO] [0D1h 0209 1] Bit Width : 20 [0D2h 0210 1] Bit Offset : 00 -[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D3h 0211 1] Encoded Access Width : 03 [DWord Access:32] [0D4h 0212 8] Address : 0000000000001008 [0DCh 0220 12] GPE0 Block : [Generic Address Structure] -[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DCh 0220 1] Space ID : 01 [SystemIO] [0DDh 0221 1] Bit Width : 00 [0DEh 0222 1] Bit Offset : 00 [0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] [0E0h 0224 8] Address : 0000000000000000 [0E8h 0232 12] GPE1 Block : [Generic Address Structure] [0E8h 0232 1] Space ID : 01 [SystemIO] [0E9h 0233 1] Bit Width : 00 [0EAh 0234 1] Bit Offset : 00 [0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] [0ECh 0236 8] Address : 0000000000000000 Raw Table Data: Length 244 (0xF4) - 0000: 46 41 43 50 F4 00 00 00 04 61 43 4F 52 45 20 20 // FACP.....aCORE + 0000: 46 41 43 50 F4 00 00 00 04 6E 43 4F 52 45 20 20 // FACP.....nCORE 0010: 43 4F 52 45 42 4F 4F 54 00 00 00 00 43 4F 52 45 // COREBOOT....CORE - 0020: 01 00 00 00 40 62 F4 7B 80 62 F4 7B 01 02 09 00 // ....(a)b.{.b.{.... + 0020: 00 00 00 00 40 62 F4 7B 80 62 F4 7B 00 02 09 00 // ....(a)b.{.b.{.... 0030: B2 00 00 00 E1 1E 00 00 00 10 00 00 00 00 00 00 // ................ 0040: 04 10 00 00 00 00 00 00 50 10 00 00 08 10 00 00 // ........P....... 0050: 80 10 00 00 00 00 00 00 04 02 01 04 20 00 00 00 // ............ ... - 0060: 01 00 57 00 00 04 10 00 01 00 0D 00 00 03 00 00 // ..W............. - 0070: AD 8C 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0060: 01 00 57 00 00 00 00 00 00 00 0D 00 00 03 00 00 // ..W............. + 0070: AD 8C 00 00 01 08 00 01 F9 0C 00 00 00 00 00 00 // ................ 0080: 06 00 00 00 40 62 F4 7B 00 00 00 00 80 62 F4 7B // ....@b.{.....b.{ - 0090: 00 00 00 00 01 20 00 00 00 10 00 00 00 00 00 00 // ..... .......... - 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 0090: 00 00 00 00 01 20 00 02 00 10 00 00 00 00 00 00 // ..... .......... + 00A0: 01 00 00 00 00 00 00 00 00 00 00 00 01 10 00 02 // ................ 00B0: 04 10 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ - 00C0: 00 00 00 00 01 08 00 00 50 10 00 00 00 00 00 00 // ........P....... - 00D0: 01 20 00 00 08 10 00 00 00 00 00 00 00 00 00 00 // . .............. + 00C0: 00 00 00 00 01 08 00 01 50 10 00 00 00 00 00 00 // ........P....... + 00D0: 01 20 00 03 08 10 00 00 00 00 00 00 01 00 00 00 // . .............. 00E0: 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ 00F0: 00 00 00 00 // .... Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/devicetree.cb D src/mainboard/google/beltino/fadt.c D src/mainboard/google/slippy/fadt.c M src/mainboard/google/slippy/variants/falco/devicetree.cb M src/mainboard/google/slippy/variants/leon/devicetree.cb M src/mainboard/google/slippy/variants/peppy/devicetree.cb M src/mainboard/google/slippy/variants/wolf/devicetree.cb M src/mainboard/intel/baskingridge/devicetree.cb D src/mainboard/intel/baskingridge/fadt.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/chip.h M src/southbridge/intel/lynxpoint/lpc.c 12 files changed, 172 insertions(+), 453 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/29387/1 diff --git a/src/mainboard/google/beltino/devicetree.cb b/src/mainboard/google/beltino/devicetree.cb index 89758dd..1c8c356 100644 --- a/src/mainboard/google/beltino/devicetree.cb +++ b/src/mainboard/google/beltino/devicetree.cb @@ -71,6 +71,9 @@ # Route all USB ports to XHCI per default register "xhci_default" = "1" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 off end # Serial I/O DMA diff --git a/src/mainboard/google/beltino/fadt.c b/src/mainboard/google/beltino/fadt.c deleted file mode 100644 index 5c2cafd..0000000 --- a/src/mainboard/google/beltino/fadt.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <device/pci.h> -#include <southbridge/intel/lynxpoint/pch.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/slippy/fadt.c b/src/mainboard/google/slippy/fadt.c deleted file mode 100644 index 52a099f..0000000 --- a/src/mainboard/google/slippy/fadt.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> -#include <southbridge/intel/lynxpoint/pch.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = get_pmbase(); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = get_acpi_table_revision(FADT); - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x80; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 32; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 0; - fadt->x_gpe0_blk.bit_width = 0; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = 0; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/google/slippy/variants/falco/devicetree.cb b/src/mainboard/google/slippy/variants/falco/devicetree.cb index f2a9520..3cfe4be 100644 --- a/src/mainboard/google/slippy/variants/falco/devicetree.cb +++ b/src/mainboard/google/slippy/variants/falco/devicetree.cb @@ -84,6 +84,9 @@ # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013e0000" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/leon/devicetree.cb b/src/mainboard/google/slippy/variants/leon/devicetree.cb index 8951e99..0aa92b7 100644 --- a/src/mainboard/google/slippy/variants/leon/devicetree.cb +++ b/src/mainboard/google/slippy/variants/leon/devicetree.cb @@ -89,6 +89,9 @@ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/peppy/devicetree.cb b/src/mainboard/google/slippy/variants/peppy/devicetree.cb index 6451d95..a6c4b95 100644 --- a/src/mainboard/google/slippy/variants/peppy/devicetree.cb +++ b/src/mainboard/google/slippy/variants/peppy/devicetree.cb @@ -88,6 +88,9 @@ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/google/slippy/variants/wolf/devicetree.cb b/src/mainboard/google/slippy/variants/wolf/devicetree.cb index 2cad23b..9cdb59a 100644 --- a/src/mainboard/google/slippy/variants/wolf/devicetree.cb +++ b/src/mainboard/google/slippy/variants/wolf/devicetree.cb @@ -89,6 +89,9 @@ # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP register "icc_clock_disable" = "0x013c0000" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 13.0 off end # Smart Sound Audio DSP device pci 14.0 on end # USB3 XHCI device pci 15.0 on end # Serial I/O DMA diff --git a/src/mainboard/intel/baskingridge/devicetree.cb b/src/mainboard/intel/baskingridge/devicetree.cb index a9cfb49..8d5e799 100644 --- a/src/mainboard/intel/baskingridge/devicetree.cb +++ b/src/mainboard/intel/baskingridge/devicetree.cb @@ -58,6 +58,9 @@ # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" + register "c2_latency" = "1" + register "c3_latency" = "87" + device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/intel/baskingridge/fadt.c b/src/mainboard/intel/baskingridge/fadt.c deleted file mode 100644 index 54e95f8..0000000 --- a/src/mainboard/intel/baskingridge/fadt.c +++ /dev/null @@ -1,151 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <device/pci.h> -#include <arch/acpi.h> -#include <cpu/x86/smm.h> - -void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), - 0x40) & 0xfffe; - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 3; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_DESKTOP; - - fadt->sci_int = 0x9; - fadt->smi_cmd = APM_CNT; - fadt->acpi_enable = APM_CNT_ACPI_ENABLE; - fadt->acpi_disable = APM_CNT_ACPI_DISABLE; - fadt->s4bios_req = 0x0; - fadt->pstate_cnt = 0; - - fadt->pm1a_evt_blk = pmbase; - fadt->pm1b_evt_blk = 0x0; - fadt->pm1a_cnt_blk = pmbase + 0x4; - fadt->pm1b_cnt_blk = 0x0; - fadt->pm2_cnt_blk = pmbase + 0x50; - fadt->pm_tmr_blk = pmbase + 0x8; - fadt->gpe0_blk = pmbase + 0x20; - fadt->gpe1_blk = 0; - - fadt->pm1_evt_len = 4; - fadt->pm1_cnt_len = 2; - fadt->pm2_cnt_len = 1; - fadt->pm_tmr_len = 4; - fadt->gpe0_blk_len = 16; - fadt->gpe1_blk_len = 0; - fadt->gpe1_base = 0; - fadt->cst_cnt = 0; - fadt->p_lvl2_lat = 1; - fadt->p_lvl3_lat = 87; - fadt->flush_size = 1024; - fadt->flush_stride = 16; - fadt->duty_offset = 1; - fadt->duty_width = 0; - fadt->day_alrm = 0xd; - fadt->mon_alrm = 0x00; - fadt->century = 0x00; - fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; - - fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | - ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | - ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | - ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; - - fadt->reset_reg.space_id = 1; - fadt->reset_reg.bit_width = 8; - fadt->reset_reg.bit_offset = 0; - fadt->reset_reg.resv = 0; - fadt->reset_reg.addrl = 0xcf9; - fadt->reset_reg.addrh = 0; - - fadt->reset_value = 6; - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - fadt->x_pm1a_evt_blk.space_id = 1; - fadt->x_pm1a_evt_blk.bit_width = 32; - fadt->x_pm1a_evt_blk.bit_offset = 0; - fadt->x_pm1a_evt_blk.resv = 0; - fadt->x_pm1a_evt_blk.addrl = pmbase; - fadt->x_pm1a_evt_blk.addrh = 0x0; - - fadt->x_pm1b_evt_blk.space_id = 1; - fadt->x_pm1b_evt_blk.bit_width = 0; - fadt->x_pm1b_evt_blk.bit_offset = 0; - fadt->x_pm1b_evt_blk.resv = 0; - fadt->x_pm1b_evt_blk.addrl = 0x0; - fadt->x_pm1b_evt_blk.addrh = 0x0; - - fadt->x_pm1a_cnt_blk.space_id = 1; - fadt->x_pm1a_cnt_blk.bit_width = 16; - fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.resv = 0; - fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; - fadt->x_pm1a_cnt_blk.addrh = 0x0; - - fadt->x_pm1b_cnt_blk.space_id = 1; - fadt->x_pm1b_cnt_blk.bit_width = 0; - fadt->x_pm1b_cnt_blk.bit_offset = 0; - fadt->x_pm1b_cnt_blk.resv = 0; - fadt->x_pm1b_cnt_blk.addrl = 0x0; - fadt->x_pm1b_cnt_blk.addrh = 0x0; - - fadt->x_pm2_cnt_blk.space_id = 1; - fadt->x_pm2_cnt_blk.bit_width = 8; - fadt->x_pm2_cnt_blk.bit_offset = 0; - fadt->x_pm2_cnt_blk.resv = 0; - fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; - fadt->x_pm2_cnt_blk.addrh = 0x0; - - fadt->x_pm_tmr_blk.space_id = 1; - fadt->x_pm_tmr_blk.bit_width = 32; - fadt->x_pm_tmr_blk.bit_offset = 0; - fadt->x_pm_tmr_blk.resv = 0; - fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; - fadt->x_pm_tmr_blk.addrh = 0x0; - - fadt->x_gpe0_blk.space_id = 1; - fadt->x_gpe0_blk.bit_width = 64; - fadt->x_gpe0_blk.bit_offset = 0; - fadt->x_gpe0_blk.resv = 0; - fadt->x_gpe0_blk.addrl = pmbase + 0x20; - fadt->x_gpe0_blk.addrh = 0x0; - - fadt->x_gpe1_blk.space_id = 1; - fadt->x_gpe1_blk.bit_width = 0; - fadt->x_gpe1_blk.bit_offset = 0; - fadt->x_gpe1_blk.resv = 0; - fadt->x_gpe1_blk.addrl = 0x0; - fadt->x_gpe1_blk.addrh = 0x0; - - header->checksum = acpi_checksum((void *) fadt, header->length); -} diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 1e088c1..5837d6d 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -35,6 +35,7 @@ select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN + select COMMON_FADT config INTEL_LYNXPOINT_LP bool diff --git a/src/southbridge/intel/lynxpoint/chip.h b/src/southbridge/intel/lynxpoint/chip.h index d11ce5f..f0f0383 100644 --- a/src/southbridge/intel/lynxpoint/chip.h +++ b/src/southbridge/intel/lynxpoint/chip.h @@ -110,6 +110,11 @@ /* Route USB ports to XHCI per default */ uint8_t xhci_default; + + /* Information for the ACPI FADT. */ + uint16_t c2_latency; + uint16_t c3_latency; + bool docking_supported; }; extern struct chip_operations southbridge_intel_lynxpoint_ops; diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index cf5959e..6d29480 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -790,6 +790,154 @@ } } +void acpi_fill_fadt(acpi_fadt_t *fadt) +{ + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct southbridge_intel_lynxpoint_config *cfg = dev->chip_info; + u16 c2_latency = cfg->c2_latency; + u16 c3_latency = cfg->c3_latency; + u16 pmbase = get_pmbase(); + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + PM2_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + if (pch_is_lp()) + fadt->gpe0_blk = pmbase + LP_GPE0_STS_1; + else + fadt->gpe0_blk = pmbase + GPE0_STS; + fadt->gpe1_blk = 0; + + /* + * Some of the lengths here are doubled. This is because they describe + * blocks containing two registers, where the size of each register + * is found by halving the block length. See Table 5-34 and section + * 4.8.3 of the ACPI specification for details. + */ + fadt->pm1_evt_len = 2 * 2; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + if (pch_is_lp()) + fadt->gpe0_blk_len = 2 * 16; + else + fadt->gpe0_blk_len = 2 * 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = c2_latency ? c2_latency : ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = c3_latency ? c3_latency : ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 0; + fadt->duty_width = 0; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + + if (cfg->docking_supported) + fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; + + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 2 * 16; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = pmbase + PM2_CNT; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* + * We don't set `fadt->x_gpe0_blk` for Lynx Point LP since the correct + * bit width is 128 * 2, which is too large for an 8 bit unsigned int. + * The OSPM can instead use the values in `fadt->gpe0_blk{,_len}`. + */ + if (!pch_is_lp()) { + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 2 * 64; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_gpe0_blk.addrl = pmbase + GPE0_STS; + fadt->x_gpe0_blk.addrh = 0x0; + } else { + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 0; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = 0; + fadt->x_gpe0_blk.addrl = 0x0; + fadt->x_gpe0_blk.addrh = 0x0; + } + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; +} + static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; -- To view, visit https://review.coreboot.org/29387 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9638bb5ff998518eb750e3e7e85b51cdaf1f070e Gerrit-Change-Number: 29387 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Deduplicate `acpi_fill_madt()`
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29388 Change subject: sb/intel/lynxpoint: Deduplicate `acpi_fill_madt()` ...................................................................... sb/intel/lynxpoint: Deduplicate `acpi_fill_madt()` The function `acpi_fill_madt()` is identical among all the Lynx Point boards, so share a common function between them. The file madt.c that implements the common function was copied from sb/intel/bd82x6x. Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No issues arose from this patch. Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/acpi_tables.c M src/mainboard/google/slippy/acpi_tables.c M src/mainboard/intel/baskingridge/acpi_tables.c M src/southbridge/intel/lynxpoint/Makefile.inc A src/southbridge/intel/lynxpoint/madt.c 5 files changed, 42 insertions(+), 54 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/29388/1 diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index 3e9f2ad..b6ca0f8 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -78,21 +78,3 @@ acpi_update_thermal_table(gnvs); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index 4036f1b..7de0bfb 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -62,21 +62,3 @@ acpi_update_thermal_table(gnvs); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index b9dd015..730fbad 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -80,21 +80,3 @@ acpi_update_thermal_table(gnvs); } - -unsigned long acpi_fill_madt(unsigned long current) -{ - /* Local APICs */ - current = acpi_create_madt_lapics(current); - - /* IOAPIC */ - current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, - 2, IO_APIC_ADDR, 0); - - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); - - return current; -} diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index db34546..4530df0 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += me_status.c ramstage-y += watchdog.c ramstage-y += acpi.c +ramstage-y += madt.c ramstage-$(CONFIG_ELOG) += elog.c diff --git a/src/southbridge/intel/lynxpoint/madt.c b/src/southbridge/intel/lynxpoint/madt.c new file mode 100644 index 0000000..afa15ae --- /dev/null +++ b/src/southbridge/intel/lynxpoint/madt.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} -- To view, visit https://review.coreboot.org/29388 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556 Gerrit-Change-Number: 29388 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

1 0

Change in coreboot[master]: sb/intel/lynxpoint: Add a common platform.asl file
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29386 Change subject: sb/intel/lynxpoint: Add a common platform.asl file ...................................................................... sb/intel/lynxpoint: Add a common platform.asl file The platform.asl file is copied from sb/intel/bd82x6x, and also matches the contents deleted from each mainboard's platform.asl. Tested on an ASRock H81M-HDS and a Google Peppy board (variant of Slippy). No issues arose from this patch. Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/mainboard/google/beltino/acpi/platform.asl M src/mainboard/google/slippy/acpi/platform.asl M src/mainboard/intel/baskingridge/acpi/platform.asl A src/southbridge/intel/lynxpoint/acpi/platform.asl 4 files changed, 56 insertions(+), 111 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/29386/1 diff --git a/src/mainboard/google/beltino/acpi/platform.asl b/src/mainboard/google/beltino/acpi/platform.asl index bc2fba2..cbe0c6f 100644 --- a/src/mainboard/google/beltino/acpi/platform.asl +++ b/src/mainboard/google/beltino/acpi/platform.asl @@ -14,43 +14,7 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} +#include <southbridge/intel/lynxpoint/acpi/platform.asl> /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/google/slippy/acpi/platform.asl b/src/mainboard/google/slippy/acpi/platform.asl index 7074336..10b0efb 100644 --- a/src/mainboard/google/slippy/acpi/platform.asl +++ b/src/mainboard/google/slippy/acpi/platform.asl @@ -14,43 +14,7 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} +#include <southbridge/intel/lynxpoint/acpi/platform.asl> /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/mainboard/intel/baskingridge/acpi/platform.asl b/src/mainboard/intel/baskingridge/acpi/platform.asl index 22a13b2..4d610d5 100644 --- a/src/mainboard/intel/baskingridge/acpi/platform.asl +++ b/src/mainboard/intel/baskingridge/acpi/platform.asl @@ -14,43 +14,7 @@ * GNU General Public License for more details. */ -/* The APM port can be used for generating software SMIs */ - -OperationRegion (APMP, SystemIO, 0xb2, 2) -Field (APMP, ByteAcc, NoLock, Preserve) -{ - APMC, 8, // APM command - APMS, 8 // APM status -} - -/* Port 80 POST */ - -OperationRegion (POST, SystemIO, 0x80, 1) -Field (POST, ByteAcc, Lock, Preserve) -{ - DBG0, 8 -} - -/* SMI I/O Trap */ -Method(TRAP, 1, Serialized) -{ - Store (Arg0, SMIF) // SMI Function - Store (0, TRP0) // Generate trap - Return (SMIF) // Return value of SMI handler -} - -/* The _PIC method is called by the OS to choose between interrupt - * routing via the i8259 interrupt controller or the APIC. - * - * _PIC is called with a parameter of 0 for i8259 configuration and - * with a parameter of 1 for Local Apic/IOAPIC configuration. - */ - -Method(_PIC, 1) -{ - // Remember the OS' IRQ routing choice. - Store(Arg0, PICM) -} +#include <southbridge/intel/lynxpoint/acpi/platform.asl> /* The _PTS method (Prepare To Sleep) is called before the OS is * entering a sleep state. The sleep state number is passed in Arg0 diff --git a/src/southbridge/intel/lynxpoint/acpi/platform.asl b/src/southbridge/intel/lynxpoint/acpi/platform.asl new file mode 100644 index 0000000..e370668 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/acpi/platform.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} -- To view, visit https://review.coreboot.org/29386 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c Gerrit-Change-Number: 29386 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: nb/intel/haswell/gma: Support boards that have DDI E connected
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29385 Change subject: nb/intel/haswell/gma: Support boards that have DDI E connected ...................................................................... nb/intel/haswell/gma: Support boards that have DDI E connected On an ASRock H81M-HDS neither libgfxinit, nor Linux, is able to initialise the display when lanes are not configured to be shared between DDI A and DDI E. Intel's reference manual [1] states that the decision to share lanes between DDI A and DDI E is "based on board configuration". Hence, add a new field to the devicetree that boards can set. All existing Haswell boards have this unset, thus taking a value of 0, so there is no change to existing behaviour. [1]: Intel Open Source Graphics Programmer's Reference Manual (PRM) Volume 2c: Command Reference: Registers (Haswell) https://01.org/linuxgraphics/documentation/hardware-specification-prms/2013… Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/northbridge/intel/haswell/chip.h M src/northbridge/intel/haswell/gma.c 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/29385/1 diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 098bc33..fdabc3f 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -40,6 +40,8 @@ u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */ + bool gpu_ddi_e_connected; + struct i915_gpu_controller_info gfx; }; diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c index efc9fa3..f4cec68 100644 --- a/src/northbridge/intel/haswell/gma.c +++ b/src/northbridge/intel/haswell/gma.c @@ -368,7 +368,10 @@ bit 4: DDI A supports 4 lanes and DDI E is not used bit 7: DDI buffer is idle */ - gtt_write(DDI_BUF_CTL_A, DDI_BUF_IS_IDLE | DDI_A_4_LANES | DDI_INIT_DISPLAY_DETECTED); + reg32 = DDI_BUF_IS_IDLE | DDI_INIT_DISPLAY_DETECTED; + if (!conf->gpu_ddi_e_connected) + reg32 |= DDI_A_4_LANES; + gtt_write(DDI_BUF_CTL_A, reg32); /* Set FDI registers - is this required? */ gtt_write(_FDI_RXA_MISC, 0x00200090); -- To view, visit https://review.coreboot.org/29385 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6f7832293215d2b53e31b0a5c985e6098eb72f1b Gerrit-Change-Number: 29385 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: cpu/intel/haswell: Don't change the voltage regulator slow ramp rate
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29384 Change subject: cpu/intel/haswell: Don't change the voltage regulator slow ramp rate ...................................................................... cpu/intel/haswell: Don't change the voltage regulator slow ramp rate On my system (Pentium G3258, ASRock H81M-HDS), changing the the slow ramp rate during `initialize_vr_config()` results in the following exception, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 The exception occurs when `MSR_VR_MISC_CONFIG`, located at 0x603, is written to. This MSR doesn't seem to be documented publicly (except by this code). The slow ramp rate is changed by clearing bit 54 and setting bit 53 of the MSR. However, in 16cbf8983c ("haswell: VR controller configuration"), the MSR on the test system has bit 54 cleared and bit 53 set by default, meaning that explicitly changing is it not necessary. This is also the default MSR value on an Acer C720 (Google Peppy). On my Pentium G3258 system, both bit 53 and bit 54 are not set by default, and keeping it that way prevents the system from hanging. No noticeable issues arise by having these bits unset. So, leaving the slow ramp rate at its default should result in the optimal outcome. Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/29384/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index c67ef14..fac9e54 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -333,9 +333,6 @@ msr.hi &= ~(1 << (51 - 32)); /* Enable decay mode on C-state entry. */ msr.hi |= (1 << (52 - 32)); - /* Set the slow ramp rate to be fast ramp rate / 4 */ - msr.hi &= ~(0x3 << (53 - 32)); - msr.hi |= (0x01 << (53 - 32)); /* Set MIN_VID (31:24) to allow CPU to have full control. */ msr.lo &= ~0xff000000; wrmsr(MSR_VR_MISC_CONFIG, msr); -- To view, visit https://review.coreboot.org/29384 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I79b10139295741d298ac6c77c4f7272ac151ad90 Gerrit-Change-Number: 29384 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: cpu/intel/haswell: Allow use of TSC for the monotonic timer
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29383 Change subject: cpu/intel/haswell: Allow use of TSC for the monotonic timer ...................................................................... cpu/intel/haswell: Allow use of TSC for the monotonic timer When the Haswell-specific monotonic timer is used on an ASRock H81M-HDS with a Pentium G3258, the following exception is generated, causing the system to hang. CPU Index 0 - APIC 0 Unexpected Exception:13 @ 10:7f7a3736 - Halting Code: 0 eflags: 00010006 cr2: 00000000 eax: 00262626 ebx: 00140000 ecx: 00000603 edx: 00360000 edi: 00000007 esi: 00262626 ebp: 7f7c0fd8 esp: 7f7c0e90 The exception occurs when trying to read `MSR_COUNTER_24_MHz`, located at 0x637. This MSR doesn't seem to be publicly documented, and also doesn't seem to exist on the Pentium G3258. It possibly only exists on Haswell-ULT CPUs. So, allow boards to use the TSC monotonic timer instead. They can do this by placing `select TSC_MONOTONIC_TIMER` in the mainboard Kconfig. Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/cpu/intel/haswell/Makefile.inc 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/29383/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index bbd98da..c317c09 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -7,14 +7,17 @@ ramstage-y += acpi.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c -ramstage-y += monotonic_timer.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c + +ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y) +ramstage-y += monotonic_timer.c smm-y += monotonic_timer.c +endif cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S postcar-y += ../car/non-evict/exit_car.S -- To view, visit https://review.coreboot.org/29383 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I31d0e801b8cc85330dcb70c3fc03670f2e677e8f Gerrit-Change-Number: 29383 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Provide a function for mainboard super I/O config
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29382 Change subject: sb/intel/lynxpoint: Provide a function for mainboard super I/O config ...................................................................... sb/intel/lynxpoint: Provide a function for mainboard super I/O config The super I/O setup needs to be done after the LPC is enabled. For Lynx Point, configuring the super I/O in `mainboard_romstage_entry()` is too early to get a serial console output. To remedy this, add a function `mainboard_config_superio()` that will be called at the appropriate time, and can be overridden by mainboard code. Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/29382/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 8e11f10..27a3b29 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -124,6 +124,10 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec); } +void __weak mainboard_config_superio(void) +{ +} + int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config) { @@ -139,6 +143,8 @@ setup_pch_gpios(gpio_map); #endif + mainboard_config_superio(); + console_init(); pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 489b565..1e59479 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -206,6 +206,7 @@ int early_pch_init(const void *gpio_map, const struct rcba_config_instruction *rcba_config); void pch_enable_lpc(void); +void mainboard_config_superio(void); #endif /* !__PRE_RAM__ && !__SMM__ */ #endif /* __ASSEMBLER__ */ -- To view, visit https://review.coreboot.org/29382 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iaf4188a17533c636e7b0c7efa220bc6a25876dda Gerrit-Change-Number: 29382 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29380 Change subject: cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs ...................................................................... cpu/intel/haswell: Add the CPUID for Haswell C0 CPUs Tested on a Pentium G3258. Change-Id: Ibf020c034c00b3bf3a7b0cda8bd3a7d40c4c13bd Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/cpu/intel/haswell/haswell_init.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/29380/1 diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 1f8d7c3..c67ef14 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -791,6 +791,7 @@ static const struct cpu_device_id cpu_table[] = { { X86_VENDOR_INTEL, 0x306c1 }, /* Intel Haswell 4+2 A0 */ { X86_VENDOR_INTEL, 0x306c2 }, /* Intel Haswell 4+2 B0 */ + { X86_VENDOR_INTEL, 0x306c3 }, /* Intel Haswell C0 */ { X86_VENDOR_INTEL, 0x40650 }, /* Intel Haswell ULT B0 */ { X86_VENDOR_INTEL, 0x40651 }, /* Intel Haswell ULT B1 */ { 0, 0 }, -- To view, visit https://review.coreboot.org/29380 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibf020c034c00b3bf3a7b0cda8bd3a7d40c4c13bd Gerrit-Change-Number: 29380 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29381 Change subject: sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table ...................................................................... sb/intel/lynxpoint: Automatically generate the ACPI PCI routing table This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables") Tested on an ASRock H81M-HDS. The generated _PRT object looks correct, and the system doesn't show any issue when running. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1 ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2 Also tested on a Google Peppy board. The following assignments occur: ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0 ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3 ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6 ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2 ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1 A diff of the _PRT object for the Google Peppy board is below. The code used in the diff has been modified for clarity, but the semantics remain the same. To summarise the diff: * The disabled PCIe root ports are no longer included. * The LPC controller is no longer included, as it has no interrupt pin. The pins for the remaining LPC devices are each one less. Perhaps the original _PRT object was incorrect? * The SDIO device is no longer included, as it is disabled. * The Serial IO devices are no longer included, but that is due to a separate issue I am having with this system (the devices don't show up under Linux regardless of this patch). In short: their omission is not a fault of this patch. --- pre/_PRT +++ post/_PRT @@ -1,301 +1,157 @@ Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0003FFFF, Zero, Zero, 0x10 }, Package (0x04) { 0x0014FFFF, Zero, Zero, 0x12 }, Package (0x04) { 0x001BFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001CFFFF, Zero, Zero, 0x10 }, - Package (0x04) - { - 0x001CFFFF, - One, - Zero, - 0x11 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - Zero, - 0x12 - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - Zero, - 0x13 - }, - Package (0x04) { 0x001DFFFF, Zero, Zero, 0x13 }, Package (0x04) { 0x001FFFFF, Zero, Zero, 0x16 }, Package (0x04) { 0x001FFFFF, One, Zero, 0x12 }, Package (0x04) { 0x001FFFFF, 0x02, Zero, 0x11 - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - Zero, - 0x10 - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - Zero, - 0x14 - }, - - Package (0x04) - { - 0x0015FFFF, - One, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - Zero, - 0x15 - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - Zero, - 0x17 } }) } Else { - Return (Package (0x12) + Return (Package (0x09) { Package (0x04) { 0x0002FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0003FFFF, Zero, ^LPCB.LNKA, Zero }, Package (0x04) { 0x0014FFFF, Zero, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001BFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001CFFFF, Zero, ^LPCB.LNKA, Zero }, - Package (0x04) - { - 0x001CFFFF, - One, - ^LPCB.LNKB, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x02, - ^LPCB.LNKC, - Zero - }, - - Package (0x04) - { - 0x001CFFFF, - 0x03, - ^LPCB.LNKD, - Zero - }, - Package (0x04) { 0x001DFFFF, Zero, ^LPCB.LNKD, Zero }, Package (0x04) { 0x001FFFFF, Zero, ^LPCB.LNKG, Zero }, Package (0x04) { 0x001FFFFF, One, ^LPCB.LNKC, Zero }, Package (0x04) { 0x001FFFFF, 0x02, ^LPCB.LNKB, Zero - }, - - Package (0x04) - { - 0x001FFFFF, - 0x03, - ^LPCB.LNKA, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - Zero, - ^LPCB.LNKE, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - One, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x02, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0015FFFF, - 0x03, - ^LPCB.LNKF, - Zero - }, - - Package (0x04) - { - 0x0017FFFF, - Zero, - ^LPCB.LNKH, - Zero } }) } } Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- D src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl D src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl D src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl M src/northbridge/intel/haswell/acpi/hostbridge.asl M src/northbridge/intel/haswell/northbridge.c M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/lpc.c 7 files changed, 31 insertions(+), 231 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29381/1 diff --git a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl b/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 0900a3d..0000000 --- a/src/mainboard/google/beltino/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Haswell */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl b/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 0900a3d..0000000 --- a/src/mainboard/google/slippy/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,82 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Haswell */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 18 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 22 }, - Package() { 0x001fffff, 1, 0, 18 }, - Package() { 0x001fffff, 2, 0, 17 }, - Package() { 0x001fffff, 3, 0, 16 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, 0, 20 }, - Package() { 0x0015ffff, 1, 0, 21 }, - Package() { 0x0015ffff, 2, 0, 21 }, - Package() { 0x0015ffff, 3, 0, 21 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, 0, 23 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Mini-HD Audio 0:3.0 - Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - // Serial IO 0:15.0 - Package() { 0x0015ffff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x0015ffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 2, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x0015ffff, 3, \_SB.PCI0.LPCB.LNKF, 0 }, - // SDIO 0:17.0 - Package() { 0x0017ffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - }) - } -} diff --git a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl b/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl deleted file mode 100644 index 3e841e0..0000000 --- a/src/mainboard/intel/baskingridge/acpi/haswell_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for IvyBridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 20 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl index 2565851..1ebdf28 100644 --- a/src/northbridge/intel/haswell/acpi/hostbridge.asl +++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl @@ -455,6 +455,3 @@ Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/haswell_pci_irqs.asl" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index ccfb234..4501afa 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -74,6 +74,22 @@ assign_resources(dev->link_list); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + /* TODO We could determine how many PCIe busses we need in * the bar. For now that number is hardcoded to a max of 64. * See e7525/northbridge.c for an example. @@ -84,6 +100,7 @@ .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus, + .acpi_name = northbridge_acpi_name, .write_acpi_tables = northbridge_write_acpi_tables, }; diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 32485c5..1e088c1 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -33,6 +33,7 @@ select HAVE_SPI_CONSOLE_SUPPORT select RTC select SOUTHBRIDGE_INTEL_COMMON_GPIO if !INTEL_LYNXPOINT_LP + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select HAVE_INTEL_CHIPSET_LOCKDOWN config INTEL_LYNXPOINT_LP diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 6483e6d..cf5959e 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -36,6 +36,7 @@ #include <arch/acpigen.h> #include <cbmem.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #define NMI_OFF 0 @@ -789,6 +790,16 @@ } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + +static void southbridge_fill_ssdt(struct device *dev) +{ + intel_acpi_gen_def_acpi_pirq(dev); +} + static unsigned long southbridge_write_acpi_tables(struct device *device, unsigned long start, struct acpi_rsdp *rsdp) @@ -835,7 +846,9 @@ .read_resources = pch_lpc_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, + .acpi_name = lpc_acpi_name, .write_acpi_tables = southbridge_write_acpi_tables, .init = lpc_init, .enable = pch_lpc_enable, -- To view, visit https://review.coreboot.org/29381 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4 Gerrit-Change-Number: 29381 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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