October 2018 - coreboot-gerrit

Change in coreboot[master]: amd/mtrr: Fix IORR MTRR
by Elyes HAOUAS (Code Review) Oct. 30, 2018

Oct. 30, 2018

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#5). Change subject: amd/mtrr: Fix IORR MTRR ...................................................................... amd/mtrr: Fix IORR MTRR IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c 4 files changed, 7 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/5 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Fix get_cpu_count()
by Richard Spiegel (Code Review) Oct. 30, 2018

Oct. 30, 2018

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29367 ) Change subject: soc/amd/stoneyridge: Fix get_cpu_count() ...................................................................... Patch Set 1: Code-Review+2 I like Daniel's idea... but either way works for me. -- To view, visit https://review.coreboot.org/29367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Gerrit-Change-Number: 29367 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 05:02:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Fix get_cpu_count()
by Daniel Kurtz (Code Review) Oct. 30, 2018

Oct. 30, 2018

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/29367 ) Change subject: soc/amd/stoneyridge: Fix get_cpu_count() ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29367/1/src/soc/amd/stoneyridge/cpu.c File src/soc/amd/stoneyridge/cpu.c: https://review.coreboot.org/#/c/29367/1/src/soc/amd/stoneyridge/cpu.c@58 PS1, Line 58: return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) This is pretty ugly. Perhaps: int cpu_count = pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT); return (cpu_count & CPU_CNT_MASK) + 1; -- To view, visit https://review.coreboot.org/29367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Gerrit-Change-Number: 29367 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 31 Oct 2018 04:52:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Fix get_cpu_count()
by Martin Roth (Code Review) Oct. 30, 2018

Oct. 30, 2018

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/29367 Change subject: soc/amd/stoneyridge: Fix get_cpu_count() ...................................................................... soc/amd/stoneyridge: Fix get_cpu_count() In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where possible), the register being read was changed accidentally from HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5) This doesn't return the correct value, and causes Grunt to reboot. BUG=b:118721473 TEST=Boot grunt Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/cpu.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/29367/1 diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6cb59a9..1d9804d 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -55,7 +55,7 @@ static int get_cpu_count(void) { - return (pci_read_config16(SOC_NB_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + return (pci_read_config16(SOC_HT_DEV, D18F0_CPU_CNT) & CPU_CNT_MASK) + 1; } -- To view, visit https://review.coreboot.org/29367 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f Gerrit-Change-Number: 29367 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1'
by Loop Wu (Code Review) Oct. 30, 2018

Oct. 30, 2018

Loop Wu has uploaded this change for review. ( https://review.coreboot.org/29366 Change subject: Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1' ...................................................................... Veyron: add Hynix H9CCNNNBKTMLBR-NTD ddr with RAMID '00Z1' Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config. sdram-lpddr3-hynix-4GB.inc BUG=b:117967129 BRANCH=master TEST=None Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Signed-off-by: Loop_Wu <Loop_Wu(a)asus.com> --- M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/29366/1 diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index 88c0a69..ee8d4c1 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index 88c0a69..ee8d4c1 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -40,7 +40,7 @@ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 000Z */ #include "sdram_inf/sdram-lpddr3-micron-2GB-D2.inc" /* ram_code = 001Z */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-BK.inc" /* ram_code = 00Z0 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 00Z1 */ +#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 00Z1 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 00ZZ */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 010Z */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 011Z */ -- To view, visit https://review.coreboot.org/29366 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af Gerrit-Change-Number: 29366 Gerrit-PatchSet: 1 Gerrit-Owner: Loop Wu <Loop_Wu(a)asus.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Ren Kuo (Code Review) Oct. 30, 2018

Oct. 30, 2018

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/29365 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Gerrit-Change-Number: 29365 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Comment-Date: Wed, 31 Oct 2018 02:26:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Ren Kuo (Code Review) Oct. 30, 2018

Oct. 30, 2018

Ren Kuo has abandoned this change. ( https://review.coreboot.org/29239 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I51a0068ed68063435b5bf20eebce4ee5114bf42f Gerrit-Change-Number: 29239 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Ren Kuo (Code Review) Oct. 30, 2018

Oct. 30, 2018

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/29365 Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... mb/google/poppy/variants/nami: Enable radium touchscreen support Enable the radium touchscreen support BUG=b:117960394 BRANCH=master TEST= 1. emerge-nami coreboot chromeos-bootimage 2. boot up on ekko DUT to check touchscreen device by evtest /dev/input/event3: Raydium Touchscreen Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/29365/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index d505099..bd8e4bd 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -317,6 +317,23 @@ register "stop_off_delay_ms" = "2" device i2c 10 on end end + chip drivers/i2c/generic + register "hid" = ""RAYD0001"" + register "desc" = ""Raydium Touchscreen"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B3)" + register "reset_delay_ms" = "1" + register "reset_off_delay_ms" = "2" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B4)" + register "enable_delay_ms" = "10" + register "enable_off_delay_ms" = "100" + register "has_power_resource" = "1" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C3)" + register "stop_delay_ms" = "20" + register "stop_off_delay_ms" = "2" + device i2c 39 on end + end chip drivers/i2c/hid register "generic.hid" = ""SYTS7817"" register "generic.desc" = ""Synaptics Touchscreen"" -- To view, visit https://review.coreboot.org/29365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90 Gerrit-Change-Number: 29365 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: chromeec: Remove battery remaining capacity workaround
by Daisuke Nojiri (Code Review) Oct. 30, 2018

Oct. 30, 2018

Daisuke Nojiri has uploaded this change for review. ( https://review.coreboot.org/29364 Change subject: chromeec: Remove battery remaining capacity workaround ...................................................................... chromeec: Remove battery remaining capacity workaround Power manager (powerd) reads the remaining capacity and full capacity from EC through ACPI. Gas gauges typically perform charge-discharge cycle when the charge is nearly full to avoid stressing battery packs at high charge. ACPI converts remaining capacity readings to the full capacity to mask this fluctuation from the user but this can be also done by power manager. This patch removes this compensation from ACPI so that power manager can solely handle it. BUG=b:109954565,chromium:899120 BRANCH=none TEST=Verify LED changes from amber (charging) to white (full) at the same time as the display shows battery is full. Change-Id: I15d585229948a0be4b59a9c653d8524d05c3a90d Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- M src/ec/google/chromeec/acpi/battery.asl 1 file changed, 1 insertion(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/29364/1 diff --git a/src/ec/google/chromeec/acpi/battery.asl b/src/ec/google/chromeec/acpi/battery.asl index 0a0caec..3b7ef97 100644 --- a/src/ec/google/chromeec/acpi/battery.asl +++ b/src/ec/google/chromeec/acpi/battery.asl @@ -214,23 +214,7 @@ // // 2: BATTERY REMAINING CAPACITY // - Store (BTRA, Local1) - If (LAnd (Arg3, LAnd (ACEX, LNot (LAnd (BFDC, BFCG))))) { - // On AC power and battery is neither charging - // nor discharging. Linux expects a full battery - // to report same capacity as last full charge. - // https://bugzilla.kernel.org/show_bug.cgi?id=12632 - Store (BTDF, Local2) - - // See if within ~6% of full - ShiftRight (Local2, 4, Local3) - If (LAnd (LGreater (Local1, Subtract (Local2, Local3)), - LLess (Local1, Add (Local2, Local3)))) - { - Store (Local2, Local1) - } - } - Store (Local1, Index (Arg1, 2)) + Store (BTRA, Index (Arg1, 2)) // // 3: BATTERY PRESENT VOLTAGE -- To view, visit https://review.coreboot.org/29364 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I15d585229948a0be4b59a9c653d8524d05c3a90d Gerrit-Change-Number: 29364 Gerrit-PatchSet: 1 Gerrit-Owner: Daisuke Nojiri <dnojiri(a)chromium.org>

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Change in coreboot[master]: soc/intel/apollolake: Improve cold boot and S3 resume
by build bot (Jenkins) (Code Review) Oct. 30, 2018

Oct. 30, 2018

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29363 ) Change subject: soc/intel/apollolake: Improve cold boot and S3 resume ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29363/1/src/soc/intel/apollolake/chip.c File src/soc/intel/apollolake/chip.c: https://review.coreboot.org/#/c/29363/1/src/soc/intel/apollolake/chip.c@572 PS1, Line 572: * FSP provides UPD interface to execute IPC command. In order to improve boot line over 80 characters https://review.coreboot.org/#/c/29363/1/src/soc/intel/apollolake/chip.c@573 PS1, Line 573: * performance, configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay line over 80 characters -- To view, visit https://review.coreboot.org/29363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Gerrit-Change-Number: 29363 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 22:39:32 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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