coreboot-gerrit October 2018

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Change in coreboot[master]: drivers/elog: Add support for early elog
by build bot (Jenkins) (Code Review) 30 Oct '18

30 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29358 ) Change subject: drivers/elog: Add support for early elog ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29358/1/src/drivers/elog/elog.c File src/drivers/elog/elog.c: https://review.coreboot.org/#/c/29358/1/src/drivers/elog/elog.c@75 PS1, Line 75: static uint8_t * get_elog_mirror_buffer(size_t elog_size) { "foo * bar" should be "foo *bar" https://review.coreboot.org/#/c/29358/1/src/drivers/elog/elog.c@75 PS1, Line 75: static uint8_t * get_elog_mirror_buffer(size_t elog_size) { open brace '{' following function definitions go on the next line https://review.coreboot.org/#/c/29358/1/src/drivers/elog/elog.c@90 PS1, Line 90: static uint8_t * get_elog_mirror_buffer(size_t elog_size) { "foo * bar" should be "foo *bar" https://review.coreboot.org/#/c/29358/1/src/drivers/elog/elog.c@90 PS1, Line 90: static uint8_t * get_elog_mirror_buffer(size_t elog_size) { open brace '{' following function definitions go on the next line -- To view, visit https://review.coreboot.org/29358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia69515961da3bc72740f9b048a53d91af79c5b0d Gerrit-Change-Number: 29358 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 16:04:25 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/elog: Add support for early elog
by Karthik Ramasubramanian (Code Review) 30 Oct '18

30 Oct '18

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/29358 Change subject: drivers/elog: Add support for early elog ...................................................................... drivers/elog: Add support for early elog Add support to log events during the romstage. BUG=b:117884485 Change-Id: Ia69515961da3bc72740f9b048a53d91af79c5b0d Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/drivers/elog/Makefile.inc M src/drivers/elog/elog.c 2 files changed, 37 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/29358/1 diff --git a/src/drivers/elog/Makefile.inc b/src/drivers/elog/Makefile.inc index 79a7cc0..e0c42e2 100644 --- a/src/drivers/elog/Makefile.inc +++ b/src/drivers/elog/Makefile.inc @@ -1,3 +1,4 @@ +romstage-$(CONFIG_ELOG) += elog.c ramstage-$(CONFIG_ELOG) += elog.c smm-$(CONFIG_ELOG_GSMI) += elog.c gsmi.c diff --git a/src/drivers/elog/elog.c b/src/drivers/elog/elog.c index d3c01c2..7d0e0a9 100644 --- a/src/drivers/elog/elog.c +++ b/src/drivers/elog/elog.c @@ -16,6 +16,7 @@ #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) #include <arch/acpi.h> #endif +#include <arch/early_variables.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -42,6 +43,15 @@ #endif #define NV_NEEDS_ERASE (~(size_t)0) +enum elog_state { + ELOG_UNINITIALIZED = 0, + ELOG_INITIALIZED, + ELOG_BROKEN, +}; + +#define MAX_ELOG_SIZE (4 * KiB) + +#if ENV_RAMSTAGE /* * Static variables for ELOG state */ @@ -60,11 +70,29 @@ /* Device that mirrors the eventlog in memory. */ static struct mem_region_device mirror_dev; -static enum { - ELOG_UNINITIALIZED = 0, - ELOG_INITIALIZED, - ELOG_BROKEN, -} elog_initialized = ELOG_UNINITIALIZED; +static enum elog_state elog_initialized; + +static uint8_t * get_elog_mirror_buffer(size_t elog_size) { + if (elog_size == MAX_ELOG_SIZE) + return (uint8_t *)malloc(elog_size); + return NULL; +} +#else +static u16 full_threshold CAR_GLOBAL; +static u16 shrink_size CAR_GLOBAL; +static size_t mirror_last_write CAR_GLOBAL; +static size_t nv_last_write CAR_GLOBAL; +static struct region_device nv_dev CAR_GLOBAL; +static struct mem_region_device mirror_dev CAR_GLOBAL; +static enum elog_state elog_initialized CAR_GLOBAL; +static uint8_t early_elog_buf[MAX_ELOG_SIZE] CAR_GLOBAL; + +static uint8_t * get_elog_mirror_buffer(size_t elog_size) { + if (elog_size == MAX_ELOG_SIZE) + return (uint8_t *)car_get_var_ptr(early_elog_buf); + return NULL; +} +#endif static inline struct region_device *mirror_dev_get(void) { @@ -776,7 +804,7 @@ return -1; elog_size = region_device_sz(&nv_dev); - mirror_buffer = malloc(elog_size); + mirror_buffer = get_elog_mirror_buffer(elog_size); if (!mirror_buffer) { printk(BIOS_ERR, "ELOG: Unable to allocate backing store\n"); return -1; @@ -800,6 +828,7 @@ full_threshold, shrink_size); if (elog_do_add_boot_count()) { +#if ENV_RAMSTAGE elog_add_event_dword(ELOG_TYPE_BOOT, boot_count_read()); #if IS_ENABLED(CONFIG_ARCH_X86) @@ -807,6 +836,7 @@ if (IS_ENABLED(CONFIG_CMOS_POST)) cmos_post_log(); #endif +#endif /* ENV_RAMSTAGE */ } return 0; } -- To view, visit https://review.coreboot.org/29358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia69515961da3bc72740f9b048a53d91af79c5b0d Gerrit-Change-Number: 29358 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Karthikeyan Ramasubramanian <kramasub(a)chromium.org>

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Marshall Dawson (Code Review) 30 Oct '18

30 Oct '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/29350 ) Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... Patch Set 1: Abandon? Looks like a duplicate of https://review.coreboot.org/#/c/coreboot/+/29295/ -- To view, visit https://review.coreboot.org/29350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee Gerrit-Change-Number: 29350 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Oct 2018 15:44:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Get rid of domain_read_resources
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has posted comments on this change. ( https://review.coreboot.org/29345 ) Change subject: soc/amd/stoneyridge: Get rid of domain_read_resources ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29345/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29345/1//COMMIT_MSG@24 PS1, Line 24: the empty resource > The particular empty resource was filled later: It's NOT filled in later. Look at a current boot log. You'll see these that you're talking about: Show resources in subtree (Root Device)...After assigning values. ... DOMAIN: 0000 resource base 1000 size 100 align 8 gran 0 limit ffff flags 40040100 index 10000000 DOMAIN: 0000 resource base f0000000 size 4d8a100 align 26 gran 0 limit f7ffffff flags 40040200 index 0 ... PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080 That last entry is what I'm talking about. Note that the index between these is different, so they're not the same resource node. >Have you check if it's still being created? Or if not being created, does it affects the boot process anyway (it might be created and never used)? No, it's not being created any more, that's the point of this patch. Since it wasn't being filled in, it wasn't being used, and it should be deleted. Yes, I've tested booting. That's how I verified that only the empty resource changed. -- To view, visit https://review.coreboot.org/29345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Gerrit-Change-Number: 29345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 15:29:31 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: amd: [test] Fix IORR MTRR
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29352 ) Change subject: amd: [test] Fix IORR MTRR ...................................................................... Patch Set 4: (3 comments) You are having problems with include order, where some places AGESA.h is included firs, some places mtrr.h is included first. Options: 1) Remove the old and new definitions of IORR from mtrr.h and include AGESA.h where the definition is needed. 2) Rename the definitions slightly to avoid collision with AGESA.h. 3) Add protection to all AGESA.h files under src/vendorcode/amd/pi. 4) make sure all includes are in AGESA.h first in every file where mtrr.h and AGESA.h are included. https://review.coreboot.org/#/c/29352/4//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29352/4//COMMIT_MSG@7 PS4, Line 7: Fi amd/mtrr: Fix IORR MTRR https://review.coreboot.org/#/c/29352/4//COMMIT_MSG@8 PS4, Line 8: Add explanation... why was it wrong, problems with include order. https://review.coreboot.org/#/c/29352/4/src/include/cpu/amd/mtrr.h File src/include/cpu/amd/mtrr.h: https://review.coreboot.org/#/c/29352/4/src/include/cpu/amd/mtrr.h@4 PS4, Line 4: #ifndef _AGESA_H_ I would love to have it removed from AGESA.h... however, because you're doing this for family 10 through family 16, non-stoney vendor code do use the definition. So for the time being this is an acceptable solution. -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 15:20:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Furquan Shaikh (Code Review) 30 Oct '18

30 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29239 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51a0068ed68063435b5bf20eebce4ee5114bf42f Gerrit-Change-Number: 29239 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 14:59:19 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: amd: [test] Fix IORR MTRR
by Elyes HAOUAS (Code Review) 30 Oct '18

30 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#4). Change subject: amd: [test] Fix IORR MTRR ...................................................................... amd: [test] Fix IORR MTRR Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c 3 files changed, 8 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/4 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd: [test] Fix IORR MTRR
by Elyes HAOUAS (Code Review) 30 Oct '18

30 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#3). Change subject: amd: [test] Fix IORR MTRR ...................................................................... amd: [test] Fix IORR MTRR Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/mtrr/amd_mtrr.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 16 files changed, 9 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/3 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: amd: [test] Fix IORR MTRR
by Elyes HAOUAS (Code Review) 30 Oct '18

30 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#2). Change subject: amd: [test] Fix IORR MTRR ...................................................................... amd: [test] Fix IORR MTRR Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/mtrr/amd_mtrr.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 16 files changed, 7 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/2 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by Frans Hendriks (Code Review) 30 Oct '18

30 Oct '18

Frans Hendriks has abandoned this change. ( https://review.coreboot.org/29355 ) Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... Abandoned Checkin with wrong Change-Id should be patchset of other commit -- To view, visit https://review.coreboot.org/29355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I0f442b188ae10ca3ef918ca53e49b0b4728d0c5e Gerrit-Change-Number: 29355 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018