coreboot-gerrit October 2018

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Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... Patch Set 34: Code-Review+2 -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 34 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 12:15:37 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: security/tpm: Fix references to tpm_setup function
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29349 ) Change subject: security/tpm: Fix references to tpm_setup function ...................................................................... security/tpm: Fix references to tpm_setup function Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/29349 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/security/tpm/tspi/tspi.c 1 file changed, 3 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d9cade9..0b6f9bc 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -103,10 +103,10 @@ /* * tpm_setup starts the TPM and establishes the root of trust for the - * anti-rollback mechanism. SetupTPM can fail for three reasons. 1 A bug. 2 a - * TPM hardware failure. 3 An unexpected TPM state due to some attack. In + * anti-rollback mechanism. tpm_setup can fail for three reasons. 1 A bug. + * 2 a TPM hardware failure. 3 An unexpected TPM state due to some attack. In * general we cannot easily distinguish the kind of failure, so our strategy is - * to reboot in recovery mode in all cases. The recovery mode calls SetupTPM + * to reboot in recovery mode in all cases. The recovery mode calls tpm_setup * again, which executes (almost) the same sequence of operations. There is a * good chance that, if recovery mode was entered because of a TPM failure, the * failure will repeat itself. (In general this is impossible to guarantee -- To view, visit https://review.coreboot.org/29349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1 Gerrit-Change-Number: 29349 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/tpm: Fix references to tpm_setup function
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29349 ) Change subject: security/tpm: Fix references to tpm_setup function ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1 Gerrit-Change-Number: 29349 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 12:12:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/sifive/fu540: Load PLL settings from a struct
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has uploaded a new patch set (#2). ( https://review.coreboot.org/29356 ) Change subject: soc/sifive/fu540: Load PLL settings from a struct ...................................................................... soc/sifive/fu540: Load PLL settings from a struct The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/sifive/fu540/clock.c 1 file changed, 72 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29356/2 -- To view, visit https://review.coreboot.org/29356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Gerrit-Change-Number: 29356 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/sifive/fu540: Refactor PLL programming
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29356 Change subject: soc/sifive/fu540: Refactor PLL programming ...................................................................... soc/sifive/fu540: Refactor PLL programming The different PLLs in the fu540 use the same register layout, so use one function (configure_pll) to program a PLL and wait for it to lock. This also makes it possible to dynamically calculate the PLL settings later. TEST=Boot until "Payload not loaded" on HiFive Unleashed Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/sifive/fu540/clock.c 1 file changed, 72 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/29356/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 20dce23..42fe716 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -20,6 +20,9 @@ #include <stdlib.h> #include <stdint.h> +// 33.33 Mhz after reset +#define FU540_BASE_FQY 33330 + struct prci_ctlr { u32 hfxosccfg; /* offset 0x00 */ u32 corepllcfg0; /* offset 0x04 */ @@ -40,33 +43,19 @@ #define PRCI_CORECLK_CORE_PLL 0 #define PRCI_CORECLK_HFCLK 1 -#define PRCI_COREPLLCFG0_LOCK (1u << 31) -#define PRCI_COREPLLCFG0_DIVR_SHIFT 0 -#define PRCI_COREPLLCFG0_DIVF_SHIFT 6 -#define PRCI_COREPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_COREPLLCFG0_RANGE_SHIFT 18 -#define PRCI_COREPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_COREPLLCFG0_FSE_SHIFT 25 -#define PRCI_COREPLLCFG0_DIVR_MASK (0x03f << PRCI_COREPLLCFG0_DIVR_SHIFT) -#define PRCI_COREPLLCFG0_DIVF_MASK (0x1ff << PRCI_COREPLLCFG0_DIVF_SHIFT) -#define PRCI_COREPLLCFG0_DIVQ_MASK (0x007 << PRCI_COREPLLCFG0_DIVQ_SHIFT) -#define PRCI_COREPLLCFG0_RANGE_MASK (0x07 << PRCI_COREPLLCFG0_RANGE_SHIFT) -#define PRCI_COREPLLCFG0_BYPASS_MASK (0x1 << PRCI_COREPLLCFG0_BYPASS_SHIFT) -#define PRCI_COREPLLCFG0_FSE_MASK (0x1 << PRCI_COREPLLCFG0_FSE_SHIFT) - -#define PRCI_DDRPLLCFG0_LOCK (1u << 31) -#define PRCI_DDRPLLCFG0_DIVR_SHIFT 0 -#define PRCI_DDRPLLCFG0_DIVF_SHIFT 6 -#define PRCI_DDRPLLCFG0_DIVQ_SHIFT 15 -#define PRCI_DDRPLLCFG0_RANGE_SHIFT 18 -#define PRCI_DDRPLLCFG0_BYPASS_SHIFT 24 -#define PRCI_DDRPLLCFG0_FSE_SHIFT 25 -#define PRCI_DDRPLLCFG0_DIVR_MASK (0x03f << PRCI_DDRPLLCFG0_DIVR_SHIFT) -#define PRCI_DDRPLLCFG0_DIVF_MASK (0x1ff << PRCI_DDRPLLCFG0_DIVF_SHIFT) -#define PRCI_DDRPLLCFG0_DIVQ_MASK (0x007 << PRCI_DDRPLLCFG0_DIVQ_SHIFT) -#define PRCI_DDRPLLCFG0_RANGE_MASK (0x07 << PRCI_DDRPLLCFG0_RANGE_SHIFT) -#define PRCI_DDRPLLCFG0_BYPASS_MASK (0x1 << PRCI_DDRPLLCFG0_BYPASS_SHIFT) -#define PRCI_DDRPLLCFG0_FSE_MASK (0x1 << PRCI_DDRPLLCFG0_FSE_SHIFT) +#define PRCI_PLLCFG_LOCK (1u << 31) +#define PRCI_PLLCFG_DIVR_SHIFT 0 +#define PRCI_PLLCFG_DIVF_SHIFT 6 +#define PRCI_PLLCFG_DIVQ_SHIFT 15 +#define PRCI_PLLCFG_RANGE_SHIFT 18 +#define PRCI_PLLCFG_BYPASS_SHIFT 24 +#define PRCI_PLLCFG_FSE_SHIFT 25 +#define PRCI_PLLCFG_DIVR_MASK (0x03f << PRCI_PLLCFG_DIVR_SHIFT) +#define PRCI_PLLCFG_DIVF_MASK (0x1ff << PRCI_PLLCFG_DIVF_SHIFT) +#define PRCI_PLLCFG_DIVQ_MASK (0x007 << PRCI_PLLCFG_DIVQ_SHIFT) +#define PRCI_PLLCFG_RANGE_MASK (0x07 << PRCI_PLLCFG_RANGE_SHIFT) +#define PRCI_PLLCFG_BYPASS_MASK (0x1 << PRCI_PLLCFG_BYPASS_SHIFT) +#define PRCI_PLLCFG_FSE_MASK (0x1 << PRCI_PLLCFG_FSE_SHIFT) #define PRCI_DDRPLLCFG1_MASK (1u << 31) @@ -78,6 +67,38 @@ #define PRCI_DEVICESRESET_DDR_PHY_RST_N(x) (((x) & 0x1) << 3) #define PRCI_DEVICESRESET_GEMGXL_RST_N(x) (((x) & 0x1) << 5) +/* Clock initialization should only be done in romstage. */ +#if ENV_ROMSTAGE +struct pll_settings { + unsigned int divr:6; + unsigned int divf:9; + unsigned int divq:3; + unsigned int range:3; + unsigned int bypass:1; + unsigned int fse:1; +}; + +static void configure_pll(u32 *reg, struct pll_settings *s) +{ + // Write the settings to the register + u32 c = read32(reg); + clrsetbits_le32(&c, PRCI_PLLCFG_DIVR_MASK + | PRCI_PLLCFG_DIVF_MASK | PRCI_PLLCFG_DIVQ_MASK + | PRCI_PLLCFG_RANGE_MASK | PRCI_PLLCFG_BYPASS_MASK + | PRCI_PLLCFG_FSE_MASK, + (s->divr << PRCI_PLLCFG_DIVR_SHIFT) + | (s->divf << PRCI_PLLCFG_DIVF_SHIFT) + | (s->divq << PRCI_PLLCFG_DIVQ_SHIFT) + | (s->range << PRCI_PLLCFG_RANGE_SHIFT) + | (s->bypass << PRCI_PLLCFG_BYPASS_SHIFT) + | (s->fse << PRCI_PLLCFG_FSE_SHIFT)); + write32(reg, c); + + // Wait for PLL lock + while (!(read32(reg) & PRCI_PLLCFG_LOCK)) + ; /* TODO: implement a timeout */ +} + /* * Set coreclk according to the SiFive FU540-C000 Manual * https://www.sifive.com/documentation/chips/freedom-u540-c000-manual/ @@ -88,13 +109,14 @@ * For example, to setup COREPLL for 1 GHz operation, program divr = 0 (x1), * divf = 59 (4000 MHz VCO), divq = 2 (/4 Output divider) */ - -#define PRCI_CORECLK_DIVR 0 -#define PRCI_CORECLK_DIVF 59 -#define PRCI_CORECLK_DIVQ 2 -#define PRCI_CORECLK_RANGE 4 -#define PRCI_CORECLK_BYPASS 0 -#define PRCI_CORECLK_FSE 1 +static struct pll_settings corepll_settings = { + .divr = 0, + .divf = 59, + .divq = 2, + .range = 4, + .bypass = 0, + .fse = 1, +}; /* * Section 7.4.3: DDR and Ethernet Subsystem Clocking and Reset @@ -110,41 +132,22 @@ * GEMGXLPLL is set up for 125 MHz output frequency. * divr = 0, divf = 59 (4000 MHz VCO), divq = 5 */ +static struct pll_settings ddrpll_settings = { + .divr = 0, + .divf = 55, + .divq = 2, + .range = 4, + .bypass = 0, + .fse = 1, +}; -#define PRCI_DDRCLK_DIVR 0 -#define PRCI_DDRCLK_DIVF 55 -#define PRCI_DDRCLK_DIVQ 2 -#define PRCI_DDRCLK_RANGE 4 -#define PRCI_DDRCLK_BYPASS 0 -#define PRCI_DDRCLK_FSE 1 - -// 33.33 Mhz after reset -#define FU540_BASE_FQY 33330 - -/* Clock initialization should only be done in romstage. */ -#if ENV_ROMSTAGE static void init_coreclk(void) { // switch coreclk to input reference frequency before modifying PLL clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, PRCI_CORECLK_HFCLK); - u32 c = read32(&prci->corepllcfg0); - clrsetbits_le32(&c, PRCI_COREPLLCFG0_DIVR_MASK - | PRCI_COREPLLCFG0_DIVF_MASK | PRCI_COREPLLCFG0_DIVQ_MASK - | PRCI_COREPLLCFG0_RANGE_MASK | PRCI_COREPLLCFG0_BYPASS_MASK - | PRCI_COREPLLCFG0_FSE_MASK, - (PRCI_CORECLK_DIVR << PRCI_COREPLLCFG0_DIVR_SHIFT) - | (PRCI_CORECLK_DIVF << PRCI_COREPLLCFG0_DIVF_SHIFT) - | (PRCI_CORECLK_DIVQ << PRCI_COREPLLCFG0_DIVQ_SHIFT) - | (PRCI_CORECLK_RANGE << PRCI_COREPLLCFG0_RANGE_SHIFT) - | (PRCI_CORECLK_BYPASS << PRCI_COREPLLCFG0_BYPASS_SHIFT) - | (PRCI_CORECLK_FSE << PRCI_COREPLLCFG0_FSE_SHIFT)); - write32(&prci->corepllcfg0, c); - - // wait for PLL lock - while (!(read32(&prci->corepllcfg0) & PRCI_COREPLLCFG0_LOCK)) - ; /* TODO: implement a timeout */ + configure_pll(&prci->corepllcfg0, &corepll_settings); // switch coreclk to use corepll clrsetbits_le32(&prci->coreclksel, PRCI_CORECLK_MASK, @@ -158,22 +161,7 @@ clrbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); write32(&prci->ddrpllcfg1, cfg1); - u32 c = read32(&prci->ddrpllcfg0); - clrsetbits_le32(&c, PRCI_DDRPLLCFG0_DIVR_MASK - | PRCI_DDRPLLCFG0_DIVF_MASK | PRCI_DDRPLLCFG0_DIVQ_MASK - | PRCI_DDRPLLCFG0_RANGE_MASK | PRCI_DDRPLLCFG0_BYPASS_MASK - | PRCI_DDRPLLCFG0_FSE_MASK, - (PRCI_DDRCLK_DIVR << PRCI_DDRPLLCFG0_DIVR_SHIFT) - | (PRCI_DDRCLK_DIVF << PRCI_DDRPLLCFG0_DIVF_SHIFT) - | (PRCI_DDRCLK_DIVQ << PRCI_DDRPLLCFG0_DIVQ_SHIFT) - | (PRCI_DDRCLK_RANGE << PRCI_DDRPLLCFG0_RANGE_SHIFT) - | (PRCI_DDRCLK_BYPASS << PRCI_DDRPLLCFG0_BYPASS_SHIFT) - | (PRCI_DDRCLK_FSE << PRCI_DDRPLLCFG0_FSE_SHIFT)); - write32(&prci->ddrpllcfg0, c); - - // wait for PLL lock - while (!(read32(&prci->ddrpllcfg0) & PRCI_DDRPLLCFG0_LOCK)) - ; /* TODO: implement a timeout */ + configure_pll(&prci->ddrpllcfg0, &ddrpll_settings); // enable ddr clock output setbits_le32(&cfg1, PRCI_DDRPLLCFG1_MASK); @@ -248,12 +236,12 @@ return FU540_BASE_FQY; u32 cfg = read32(&prci->corepllcfg0); - u32 divr = (cfg & PRCI_COREPLLCFG0_DIVR_MASK) - >> PRCI_COREPLLCFG0_DIVR_SHIFT; - u32 divf = (cfg & PRCI_COREPLLCFG0_DIVF_MASK) - >> PRCI_COREPLLCFG0_DIVF_SHIFT; - u32 divq = (cfg & PRCI_COREPLLCFG0_DIVQ_MASK) - >> PRCI_COREPLLCFG0_DIVQ_SHIFT; + u32 divr = (cfg & PRCI_PLLCFG_DIVR_MASK) + >> PRCI_PLLCFG_DIVR_SHIFT; + u32 divf = (cfg & PRCI_PLLCFG_DIVF_MASK) + >> PRCI_PLLCFG_DIVF_SHIFT; + u32 divq = (cfg & PRCI_PLLCFG_DIVQ_MASK) + >> PRCI_PLLCFG_DIVQ_SHIFT; printk(BIOS_SPEW, "clk: r=%d f=%d q=%d\n", divr, divf, divq); return FU540_BASE_FQY -- To view, visit https://review.coreboot.org/29356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5c0cee886bad5758c70f967d2bb998c1e1a736ab Gerrit-Change-Number: 29356 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29346 to look at the new patch set (#2). Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... nb/intel/x4x/raminit: Add missing space TEST=Make the printk reachable, check with `strings build/cbfs/fallback/romstage.elf | grep lowest` that this patch changes "MHzas" to "MHz as". Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29346/2 -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 2 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by build bot (Jenkins) (Code Review) 30 Oct '18

30 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29333 ) Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... Patch Set 3: (4 comments) https://review.coreboot.org/#/c/29333/3/src/soc/intel/braswell/northcluster… File src/soc/intel/braswell/northcluster.c: https://review.coreboot.org/#/c/29333/3/src/soc/intel/braswell/northcluster… PS3, Line 110: if (fsp_reserved_memory_area){ space required before the open brace '{' https://review.coreboot.org/#/c/29333/3/src/soc/intel/braswell/northcluster… PS3, Line 111: fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area)); line over 80 characters https://review.coreboot.org/#/c/29333/3/src/soc/intel/braswell/northcluster… PS3, Line 113: else that open brace { should be on the previous line https://review.coreboot.org/#/c/29333/3/src/soc/intel/braswell/northcluster… PS3, Line 113: else else should follow close brace '}' -- To view, visit https://review.coreboot.org/29333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Gerrit-Change-Number: 29333 Gerrit-PatchSet: 3 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 10:28:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by Frans Hendriks (Code Review) 30 Oct '18

30 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29355 Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: I0f442b188ae10ca3ef918ca53e49b0b4728d0c5e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/29355/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 0554cd3..e341f66 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -107,11 +107,10 @@ /* Determine the base of the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); - if (fsp_reserved_memory_area){ - fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area)); - } - else - { + if (fsp_reserved_memory_area) { + fsp_res_base_k = + RES_IN_KIB((unsigned int)fsp_reserved_memory_area); + } else { /* If no FSP reserverd area */ fsp_res_base_k = tseg_base_k; } -- To view, visit https://review.coreboot.org/29355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0f442b188ae10ca3ef918ca53e49b0b4728d0c5e Gerrit-Change-Number: 29355 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Angel Pons (Code Review) 30 Oct '18

30 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29346 ) Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... Patch Set 1: Is this tested? printf() does need the space to display properly, but I am not sure about printk(). -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:53:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: util/board_status: Add missing space
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has abandoned this change. ( https://review.coreboot.org/29348 ) Change subject: util/board_status: Add missing space ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ie3542069a7ae21f5463e97d37f599b1bf0f6ca78 Gerrit-Change-Number: 29348 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018