coreboot-gerrit October 2018

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Change in coreboot[master]: /soc/intel:Update tcc offset for fleex
by John Su (Code Review) 30 Oct '18

30 Oct '18

John Su has uploaded this change for review. ( https://review.coreboot.org/29351 Change subject: /soc/intel:Update tcc offset for fleex ...................................................................... /soc/intel:Update tcc offset for fleex Change tcc offset from 0 to 10. Refer to b:117789732#comment20. BUG=b:117789732 TEST=Match the result from TAT UI Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/soc/intel/apollolake/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/29351/1 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d2ec6c1..eeb0c12 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -198,6 +198,12 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + /* Set TCC offset */ + msr_t msr; + msr.lo = 0xa690000; + msr.hi = 0x0; + wrmsr(0x1a2, msr); + if (punit_init()) set_max_freq(); else -- To view, visit https://review.coreboot.org/29351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc Gerrit-Change-Number: 29351 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29350 Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... soc/amd/stoneyridge: Create MMIO ACPI access functions Now that the relationship between IO access and MMIO access has been established, create read/write functions to access ACPI standard registers through MMIO. BUG=b:118049037 TEST=Build grunt Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/29350/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 681f149..6b96c81 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -444,6 +444,12 @@ void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u8 acpi_mmio_read8(u8 reg); +u16 acpi_mmio_read16(u8 reg); +u32 acpi_mmio_read32(u8 reg); +void acpi_mmio_write8(u8 reg, u8 value); +void acpi_mmio_write16(u8 reg, u16 value); +void acpi_mmio_write32(u8 reg, u32 value); u32 misc_read32(u8 reg); void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 9daf0bb..f6bfcc9 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -56,6 +56,36 @@ return read32((void *)(PM_MMIO_BASE + reg)); } +u8 acpi_mmio_read8(u8 reg) +{ + return read8((u8 *)(ACPI_REG_MMIO_BASE + reg)); +} + +u16 acpi_mmio_read16(u8 reg) +{ + return read16((u16 *)(ACPI_REG_MMIO_BASE + reg)); +} + +u32 acpi_mmio_read32(u8 reg) +{ + return read32((u32 *)(ACPI_REG_MMIO_BASE + reg)); +} + +void acpi_mmio_write8(u8 reg, u8 value) +{ + write8((u8 *)(ACPI_REG_MMIO_BASE + reg), value); +} + +void acpi_mmio_write16(u8 reg, u16 value) +{ + write16((u16 *)(ACPI_REG_MMIO_BASE + reg), value); +} + +void acpi_mmio_write32(u8 reg, u32 value) +{ + write32((u32 *)(ACPI_REG_MMIO_BASE + reg), value); +} + void smi_write32(uint8_t offset, uint32_t value) { write32((void *)(APU_SMI_BASE + offset), value); -- To view, visit https://review.coreboot.org/29350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee Gerrit-Change-Number: 29350 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: riscv: simplify timer interrupt handling
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29340 ) Change subject: riscv: simplify timer interrupt handling ...................................................................... Patch Set 4: Code-Review+1 I think it looks good -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 23:46:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Marshall Dawson (Code Review) 30 Oct '18

30 Oct '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… PS1, Line 328: if (!dev->enabled > if (dev->enabled) ? nit: if(dev && dev->enabled) https://review.coreboot.org/#/c/29343/1/src/soc/amd/stoneyridge/northbridge… File src/soc/amd/stoneyridge/northbridge.c: https://review.coreboot.org/#/c/29343/1/src/soc/amd/stoneyridge/northbridge… PS1, Line 513: dev->enabled similar nit for dev=0. -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 23:29:55 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Get rid of domain_read_resources
by Richard Spiegel (Code Review) 29 Oct '18

29 Oct '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29345 ) Change subject: soc/amd/stoneyridge: Get rid of domain_read_resources ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29345/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/29345/1//COMMIT_MSG@24 PS1, Line 24: the empty resource The particular empty resource was filled later: DOMAIN: 0000 10000000 <- [0x0000001000 - 0x00000010ff] size 0x00000100 gran 0x00 io DOMAIN: 0000 10000100 <- [0x00f0000000 - 0x00f4d8a0ff] size 0x04d8a100 gran 0x00 mem Have you check if it's still being created? Or if not being created, does it affects the boot process anyway (it might be created and never used)? -- To view, visit https://review.coreboot.org/29345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Gerrit-Change-Number: 29345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 22:53:58 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Get rid of domain_read_resources
by Marshall Dawson (Code Review) 29 Oct '18

29 Oct '18

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/29345 ) Change subject: soc/amd/stoneyridge: Get rid of domain_read_resources ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Gerrit-Change-Number: 29345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 22:35:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/asus/p5qc: Fix spelling of Marvell
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29347 Change subject: mb/asus/p5qc: Fix spelling of Marvell ...................................................................... mb/asus/p5qc: Fix spelling of Marvell Marvell is the chip company, Marvel makes comic books. Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/asus/p5qc/Kconfig M src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb M src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/29347/1 diff --git a/src/mainboard/asus/p5qc/Kconfig b/src/mainboard/asus/p5qc/Kconfig index 2bcee16..301dcf6 100644 --- a/src/mainboard/asus/p5qc/Kconfig +++ b/src/mainboard/asus/p5qc/Kconfig @@ -53,7 +53,7 @@ int default 4 -# The MARVEL IDE controller delays SeaBIOS a lot and results in an unbootable +# The MARVELL IDE controller delays SeaBIOS a lot and results in an unbootable # bogus disk. Compiling SeaBIOS without ATA support is a workaround. config PAYLOAD_CONFIGFILE diff --git a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb index f7088fc..3229779 100644 --- a/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5q_pro/devicetree.cb @@ -55,7 +55,7 @@ device pci 1c.1 off end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.4 on end # PCIe 5 MARVELL IDE device pci 1c.5 on end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB diff --git a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb index 52bbb40..5ca1978 100644 --- a/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5qc/devicetree.cb @@ -55,7 +55,7 @@ device pci 1c.1 off end # PCIe 2 device pci 1c.2 off end # PCIe 3 device pci 1c.3 off end # PCIe 4 - device pci 1c.4 on end # PCIe 5 MARVEL IDE + device pci 1c.4 on end # PCIe 5 MARVELL IDE device pci 1c.5 on end # PCIe 6 device pci 1d.0 on end # USB device pci 1d.1 on end # USB -- To view, visit https://review.coreboot.org/29347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Gerrit-Change-Number: 29347 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: util/board_status: Add missing space
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29348 Change subject: util/board_status: Add missing space ...................................................................... util/board_status: Add missing space Change-Id: Ie3542069a7ae21f5463e97d37f599b1bf0f6ca78 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/board_status/board_status.sh 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/29348/1 diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index 4acbb6c..a51142c 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -387,7 +387,7 @@ if [ $(id -u) -ne 0 ]; then command -v "$cbmem_cmd" >/dev/null if [ $? -ne 0 ]; then - echo "Failed to run $cbmem_cmd. Check \$PATH or" \ + echo "Failed to run $cbmem_cmd. Check \$PATH or " \ "use -c to specify path to cbmem binary." exit $EXIT_FAILURE else -- To view, visit https://review.coreboot.org/29348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie3542069a7ae21f5463e97d37f599b1bf0f6ca78 Gerrit-Change-Number: 29348 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: security/tpm: Fix references to tpm_setup function
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29349 Change subject: security/tpm: Fix references to tpm_setup function ...................................................................... security/tpm: Fix references to tpm_setup function Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/security/tpm/tspi/tspi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/29349/1 diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index d9cade9..0b6f9bc 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -103,10 +103,10 @@ /* * tpm_setup starts the TPM and establishes the root of trust for the - * anti-rollback mechanism. SetupTPM can fail for three reasons. 1 A bug. 2 a - * TPM hardware failure. 3 An unexpected TPM state due to some attack. In + * anti-rollback mechanism. tpm_setup can fail for three reasons. 1 A bug. + * 2 a TPM hardware failure. 3 An unexpected TPM state due to some attack. In * general we cannot easily distinguish the kind of failure, so our strategy is - * to reboot in recovery mode in all cases. The recovery mode calls SetupTPM + * to reboot in recovery mode in all cases. The recovery mode calls tpm_setup * again, which executes (almost) the same sequence of operations. There is a * good chance that, if recovery mode was entered because of a TPM failure, the * failure will repeat itself. (In general this is impossible to guarantee -- To view, visit https://review.coreboot.org/29349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia97ddcd5471f8e5db50f57b67a766f08a08180b1 Gerrit-Change-Number: 29349 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29346 Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... nb/intel/x4x/raminit: Add missing space Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/29346/1 diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 80bde6c..ff1f970 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -304,7 +304,7 @@ min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); if (min_tCLK == 0) { printk(BIOS_ERR, "DRAM frequency is under lowest supported " - "frequency (400 MHz). Increasing to 400 MHz" + "frequency (400 MHz). Increasing to 400 MHz " "as last resort"); min_tCLK = TCK_400MHZ; } -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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coreboot-gerrit October 2018