coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

1 participants
1285 discussions

Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by build bot (Jenkins) (Code Review) 30 Oct '18

30 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… PS1, Line 329: LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; line over 80 characters -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 20:24:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/29343 Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... soc/amd/stoneyridge: Set IOMMU support to follow device setting Instead of forcing the IOMMU to be enabled, change it to only be enabled if the device is enabled in devicetree. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/29343/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 87e0b69..3e7f6f9 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -29,6 +29,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/image.h> #include <amdblocks/BiosCallOuts.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/northbridge.h> #include <soc/cpu.h> @@ -323,8 +324,11 @@ */ AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); - LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + const struct device *dev = dev_find_slot(0, IOMMU_DEVFN); + if (!dev->enabled) { + LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; + LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + } timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = AmdInitLate(LateParams); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2ae52c..e981f83 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -509,7 +509,8 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) { - params->IommuSupport = TRUE; + const struct device *dev = SOC_IOMMU_DEV; + params->IommuSupport = dev->enabled; set_board_env_params(params); } -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mb/google/kahlee: Disable IOMMU
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/29342 Change subject: mb/google/kahlee: Disable IOMMU ...................................................................... mb/google/kahlee: Disable IOMMU Unfortunately Stoney has an issue where enabling the IOMMU causes a 10%-50% decrease in the integrated graphics performance. It is also disabled by default on other stoney platforms. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/delan/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/liara/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/29342/1 diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 5438e6d..27a8e28 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -58,7 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index b541c03..23253b2 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -61,7 +61,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/delan/devicetree.cb b/src/mainboard/google/kahlee/variants/delan/devicetree.cb index 0dfe204..fd30d5d 100644 --- a/src/mainboard/google/kahlee/variants/delan/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/delan/devicetree.cb @@ -55,7 +55,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 5a8906b..b37e1bf 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -61,7 +61,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index cea3425..343fbeb 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -58,7 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge -- To view, visit https://review.coreboot.org/29342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Gerrit-Change-Number: 29342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

1 0

Change in coreboot[master]: mb/google/poppy/variant/nocturne: add Nanya memory option
by Nick Vaccaro (Code Review) 30 Oct '18

30 Oct '18

Hello Caveh Jalali, Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29341 to look at the new patch set (#2). Change subject: mb/google/poppy/variant/nocturne: add Nanya memory option ...................................................................... mb/google/poppy/variant/nocturne: add Nanya memory option Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/Makefile.inc 1 file changed, 12 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29341/2 -- To view, visit https://review.coreboot.org/29341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Gerrit-Change-Number: 29341 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com>

1 0

Change in coreboot[master]: mb/google/poppy/variant/nocturne: add Nanya memory option
by Nick Vaccaro (Code Review) 30 Oct '18

30 Oct '18

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/29341 Change subject: mb/google/poppy/variant/nocturne: add Nanya memory option ...................................................................... mb/google/poppy/variant/nocturne: add Nanya memory option Add option for Nanya NT6CL256T32CM-H1 part. Add comments to indicate total memory size for convenience. BUG=b:118624505 BRANCH=master TEST=none Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/mainboard/google/poppy/variants/nocturne/Makefile.inc 1 file changed, 15 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/29341/1 diff --git a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc index c17a49c..e558cfc 100644 --- a/src/mainboard/google/poppy/variants/nocturne/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nocturne/Makefile.inc @@ -1,17 +1,17 @@ SPD_SOURCES = empty # 0b0000 -SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 -SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010 -SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 -SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100 -#SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCF # 0b0101 -SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101 -SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110 -SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111 -SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000 -SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 -SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 -SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 +SPD_SOURCES += samsung_dimm_K4E8E324EB-EGCF # 0b0001 4GB +SPD_SOURCES += hynix_dimm_H9CCNNN8GTALAR-NUD # 0b0010 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EB-EGCF # 0b0011 8GB +SPD_SOURCES += hynix_dimm_H9CCNNNBJTALAR-NUD # 0b0100 8GB +SPD_SOURCES += samsung_dimm_K4EBE304EB-EGCG # 0b0101 16GB +SPD_SOURCES += hynix_dimm_H9CCNNNCLGALAR-NUD # 0b0110 16GB +SPD_SOURCES += micron_dimm_MT52L512M32D2PF-107 # 0b0111 8GB +SPD_SOURCES += micron_dimm_MT52L1G32D4PG-107 # 0b1000 16GB +SPD_SOURCES += micron_dimm_MT52L256M32D1PF-107 # 0b1001 4GB +SPD_SOURCES += samsung_dimm_K4E6E304EC-EGCF # 0b1010 8GB +SPD_SOURCES += samsung_dimm_K4EBE304EC-EGCF # 0b1011 16GB +SPD_SOURCES += nayna_dimm_NT6CL256T32CM-H1 # 0b1100 4GB bootblock-y += gpio.c @@ -20,3 +20,6 @@ ramstage-y += gpio.c ramstage-y += nhlt.c ramstage-y += mainboard.c + +smm-y += ec.c +ramstage-y += ec.c -- To view, visit https://review.coreboot.org/29341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Gerrit-Change-Number: 29341 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com>

1 0

Change in coreboot[master]: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the...
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29339 ) Change subject: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode ...................................................................... Patch Set 1: Code-Review+2 Thanks -- To view, visit https://review.coreboot.org/29339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Gerrit-Change-Number: 29339 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 19:28:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: riscv: simplify timer interrupt handling
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29340 ) Change subject: riscv: simplify timer interrupt handling ...................................................................... Patch Set 2: I think this patch would be clearer without the formatting changes. Would you mind to split them out? -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Mon, 29 Oct 2018 18:35:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: riscv: simplify timer interrupt handling
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Philipp Hug has uploaded a new patch set (#2). ( https://review.coreboot.org/29340 ) Change subject: riscv: simplify timer interrupt handling ...................................................................... riscv: simplify timer interrupt handling Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/trap_handler.c 1 file changed, 45 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/2 -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: riscv: simplify timer interrupt handling
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/29340 Change subject: riscv: simplify timer interrupt handling ...................................................................... riscv: simplify timer interrupt handling Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/trap_handler.c 1 file changed, 45 insertions(+), 84 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/1 diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 772be64..c56dc0c 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -20,9 +20,6 @@ #include <string.h> #include <vm.h> -static uint64_t *time; -static uint64_t *timecmp; - static const char *const exception_names[] = { "Instruction address misaligned", "Instruction access fault", @@ -45,10 +42,14 @@ static const char *mstatus_to_previous_mode(uintptr_t ms) { switch (ms & MSTATUS_MPP) { - case 0x00000000: return "user"; - case 0x00000800: return "supervisor"; - case 0x00001000: return "hypervisor"; - case 0x00001800: return "machine"; + case 0x00000000: + return "user"; + case 0x00000800: + return "supervisor"; + case 0x00001000: + return "hypervisor"; + case 0x00001800: + return "machine"; } return "unknown"; @@ -64,76 +65,36 @@ if (tf->cause < ARRAY_SIZE(exception_names)) printk(BIOS_DEBUG, "Exception: %s\n", - exception_names[tf->cause]); + exception_names[tf->cause]); else printk(BIOS_DEBUG, "Trap: Unknown cause %p\n", - (void *)tf->cause); + (void *)tf->cause); previous_mode = mstatus_to_previous_mode(read_csr(mstatus)); printk(BIOS_DEBUG, "Previous mode: %s%s\n", - previous_mode, mprv? " (MPRV)":""); + previous_mode, mprv ? " (MPRV)" : ""); printk(BIOS_DEBUG, "Bad instruction pc: %p\n", (void *)tf->epc); printk(BIOS_DEBUG, "Bad address: %p\n", (void *)tf->badvaddr); - printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]); - printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]); -} - -static void gettimer(void) -{ - /* - * FIXME: This hard-coded value (currently) works on spike, but we - * should really read it from the device tree. - */ - uintptr_t clint = 0x02000000; - - time = (void *)(clint + 0xbff8); - timecmp = (void *)(clint + 0x4000); - - if (!time) - die("Got timer interrupt but found no timer."); - if (!timecmp) - die("Got timer interrupt but found no timecmp."); + printk(BIOS_DEBUG, "Stored ra: %p\n", (void *)tf->gpr[1]); + printk(BIOS_DEBUG, "Stored sp: %p\n", (void *)tf->gpr[2]); } static void interrupt_handler(trapframe *tf) { uint64_t cause = tf->cause & ~0x8000000000000000ULL; - uint32_t msip, ssie; switch (cause) { case IRQ_M_TIMER: - // The only way to reset the timer interrupt is to - // write mtimecmp. But we also have to ensure the - // comparison fails, for a long time, to let - // supervisor interrupt handler compute a new value - // and set it. Finally, it fires if mtimecmp is <= - // mtime, not =, so setting mtimecmp to 0 won't work - // to clear the interrupt and disable a new one. We - // have to set the mtimecmp far into the future. - // Akward! - // - // Further, maybe the platform doesn't have the - // hardware or the payload never uses it. We hold off - // querying some things until we are sure we need - // them. What to do if we can not find them? There are - // no good options. + /* + * Set interrupt pending for supervisor mode and disable timer + * interrupt in machine mode. + * To receive another timer interrupt just set timecmp and + * enable machine mode timer interrupt again. + */ - // This hart may have disabled timer interrupts. If - // so, just return. Kernels should only enable timer - // interrupts on one hart, and that should be hart 0 - // at present, as we only search for - // "core{0{0{timecmp" above. - ssie = read_csr(sie); - if (!(ssie & SIP_STIP)) - break; + clear_csr(mie, MIP_MTIP); + set_csr(mip, MIP_STIP); - if (!timecmp) - gettimer(); - //printk(BIOS_SPEW, "timer interrupt\n"); - *timecmp = (uint64_t) -1; - msip = read_csr(mip); - msip |= SIP_STIP; - write_csr(mip, msip); break; default: printk(BIOS_EMERG, "======================================\n"); @@ -152,30 +113,30 @@ return; } - switch(tf->cause) { - case CAUSE_MISALIGNED_FETCH: - case CAUSE_FETCH_ACCESS: - case CAUSE_ILLEGAL_INSTRUCTION: - case CAUSE_BREAKPOINT: - case CAUSE_LOAD_ACCESS: - case CAUSE_STORE_ACCESS: - case CAUSE_USER_ECALL: - case CAUSE_SUPERVISOR_ECALL: - case CAUSE_HYPERVISOR_ECALL: - case CAUSE_MACHINE_ECALL: - print_trap_information(tf); - break; - case CAUSE_MISALIGNED_LOAD: - case CAUSE_MISALIGNED_STORE: - print_trap_information(tf); - handle_misaligned(tf); - return; - default: - printk(BIOS_EMERG, "================================\n"); - printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); - printk(BIOS_EMERG, "================================\n"); - print_trap_information(tf); - break; + switch (tf->cause) { + case CAUSE_MISALIGNED_FETCH: + case CAUSE_FETCH_ACCESS: + case CAUSE_ILLEGAL_INSTRUCTION: + case CAUSE_BREAKPOINT: + case CAUSE_LOAD_ACCESS: + case CAUSE_STORE_ACCESS: + case CAUSE_USER_ECALL: + case CAUSE_SUPERVISOR_ECALL: + case CAUSE_HYPERVISOR_ECALL: + case CAUSE_MACHINE_ECALL: + print_trap_information(tf); + break; + case CAUSE_MISALIGNED_LOAD: + case CAUSE_MISALIGNED_STORE: + print_trap_information(tf); + handle_misaligned(tf); + return; + default: + printk(BIOS_EMERG, "================================\n"); + printk(BIOS_EMERG, "coreboot: can not handle a trap:\n"); + printk(BIOS_EMERG, "================================\n"); + print_trap_information(tf); + break; } die("Can't recover from trap. Halting.\n"); -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

1 0

Change in coreboot[master]: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the...
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29339 ) Change subject: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode ...................................................................... Patch Set 1: Found this when I re-used this code for instruction emulation. Not tested yet. -- To view, visit https://review.coreboot.org/29339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Gerrit-Change-Number: 29339 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Comment-Date: Mon, 29 Oct 2018 17:11:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2018