coreboot-gerrit October 2018

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservation
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29332 Change subject: src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservation ...................................................................... src/soc/intel/braswell/northcluster.c: Correct Chromeos RAM reservation RAM is reserved for Chromeos even when Chrome is not used. Use CONFIG_CHROMEOS to determine is RAM must be reserved. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/29332/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 3245a28..88f7d0c 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -149,7 +149,9 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_reserve_ram_oops(dev, index++); +#endif } static struct device_operations nc_ops = { -- To view, visit https://review.coreboot.org/29332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682 Gerrit-Change-Number: 29332 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29333 Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area Calculation of memory reserved by FSP is incorrect. Use CBMEM_ID_FSP_RESERVED_MEMORY to determine the memory area BUG=N/A TEST=Intel CherryHill CRB Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 13 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/29333/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 88f7d0c..0554cd3 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -3,6 +3,7 @@ * * Copyright (C) 2013 Google Inc. * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -93,6 +94,7 @@ unsigned long fsp_res_base_k; unsigned long base_k, size_k; const unsigned long four_gig_kib = (4 << (30 - 10)); + void *fsp_reserved_memory_area; int index = 0; /* Read standard PCI resources. */ @@ -104,7 +106,15 @@ tseg_top_k = tseg_base_k + RES_IN_KIB(smm_size); /* Determine the base of the FSP reserved memory */ - fsp_res_base_k = RES_IN_KIB((unsigned long) cbmem_top()); + fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_reserved_memory_area){ + fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area)); + } + else + { + /* If no FSP reserverd area */ + fsp_res_base_k = tseg_base_k; + } /* PCIe memory-mapped config space access - 256 MiB. */ mmconf = iosf_bunit_read(BUNIT_MMCONF_REG) & ~((1 << 28) - 1); @@ -115,8 +125,8 @@ size_k = RES_IN_KIB(0xa0000) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xc0000 -> fsp_res_base - cacheable and usable */ - base_k = RES_IN_KIB(0xc0000); + /* High memory -> fsp_res_base - cacheable and usable */ + base_k = RES_IN_KIB(0x100000); size_k = fsp_res_base_k - base_k; ram_resource(dev, index++, base_k, size_k); -- To view, visit https://review.coreboot.org/29333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Gerrit-Change-Number: 29333 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29331 Change subject: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid. ...................................................................... src/drivers/pc80/tpm/tis.c: Dont use port value when invalid. port is allocated in ACPI, without checking for value. Don't use port value when zero. BUG=N/A TEST=Portwell PQ-M107 Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/29331/1 diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 6b84614..f7d9d6f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -911,7 +912,8 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_write_mem32fixed(1, CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000); - acpigen_write_io16(port, port, 1, 2, 1); + if (port) + acpigen_write_io16(port, port, 1, 2, 1); if (CONFIG_TPM_PIRQ) { /* -- To view, visit https://review.coreboot.org/29331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Gerrit-Change-Number: 29331 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29330 Change subject: src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines ...................................................................... src/soc/intel/baytrail/southcluster.c: Replace fixed values by defines The GPIO and ACPI base sizes have defines, but they are not used. Use GPIO_BASE_SIZE and ACPI_BASE_SIZE. BUG=N/A TEST=Intel BayTrail CRB Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/baytrail/southcluster.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29330/1 diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 0ef70d0..f44f502 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -3,6 +3,7 @@ * * Copyright (C) 2008-2009 coresystems GmbH * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -107,10 +108,10 @@ res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; /* GPIO */ - sc_add_io_resource(dev, GPIO_BASE_ADDRESS, 256, GBASE); + sc_add_io_resource(dev, GPIO_BASE_ADDRESS, GPIO_BASE_SIZE, GBASE); /* ACPI */ - sc_add_io_resource(dev, ACPI_BASE_ADDRESS, 128, ABASE); + sc_add_io_resource(dev, ACPI_BASE_ADDRESS, ACPI_BASE_SIZE, ABASE); } static void sc_read_resources(struct device *dev) -- To view, visit https://review.coreboot.org/29330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90 Gerrit-Change-Number: 29330 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29329 Change subject: src/drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure ...................................................................... src/drivers/pc80/rtc/mc146818rtc.c: Reset RTC time on RTC power failure RTC time contains invalid values on system without RTC battery Add config to enable reset of RTC time when RTC power failure has been detected. BUG=N/A TEST=Portwell PQ-M107 Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/pc80/rtc/Kconfig M src/drivers/pc80/rtc/mc146818rtc.c 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/29329/1 diff --git a/src/drivers/pc80/rtc/Kconfig b/src/drivers/pc80/rtc/Kconfig index 350863e..fd4675a4 100644 --- a/src/drivers/pc80/rtc/Kconfig +++ b/src/drivers/pc80/rtc/Kconfig @@ -2,3 +2,8 @@ bool default y if ARCH_X86 depends on PC80_SYSTEM + +config RESET_TIME_ON_RTC_POWERFAIL + bool + default n + depends on PC80_SYSTEM diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 3b22a46..81d10cd 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -3,6 +3,7 @@ * * Copyright 2014 The Chromium OS Authors. All rights reserved. * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -122,6 +123,13 @@ x = cmos_read(RTC_VALID); cmos_invalid = !(x & RTC_VRT); +#if IS_ENABLED(CONFIG_RESET_TIME_ON_RTC_POWERFAIL) + if (invalid == true) { + cmos_invalid = true; + printk(BIOS_DEBUG, "Force cmos_invalid to true\n"); + } +#endif + if (IS_ENABLED(CONFIG_USE_OPTION_TABLE)) { /* See if there is a CMOS checksum error */ checksum_invalid = !cmos_checksum_valid(PC_CKS_RANGE_START, -- To view, visit https://review.coreboot.org/29329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I5eae57d00f328400a8b03c28b7ecdbbc71522206 Gerrit-Change-Number: 29329 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/drivers/intel/fsp1_1/Kconfig: Remove unused FSP_USES_UPD
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29328 Change subject: src/drivers/intel/fsp1_1/Kconfig: Remove unused FSP_USES_UPD ...................................................................... src/drivers/intel/fsp1_1/Kconfig: Remove unused FSP_USES_UPD CONFIG_FSP_USES_UPD is not used by FSP 1.1. Remove this config from this file. BUG=N/A TEST=Intel CherryHill CRB Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/Kconfig 1 file changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/29328/1 diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index a70f00d..86f47a6 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2014 Sage Electronic Engineering, LLC. +## Copyright (C) 2018 Eltan B.V. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -82,13 +83,6 @@ Display the user specified product data prior to memory initialization. -config FSP_USES_UPD - bool - default n - help - If this FSP uses UPD/VPD data regions, select this in the chipset - Kconfig. - config USE_GENERIC_FSP_CAR_INC bool default n -- To view, visit https://review.coreboot.org/29328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If922b6cb2d39b10f6657b4d80e54b226d1386c76 Gerrit-Change-Number: 29328 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: soc/intel/icelake: Open ports 0x60, 0x64 for keyboard controller
by Aamir Bohra (Code Review) 29 Oct '18

29 Oct '18

Hello Shelley Chen, I'd like you to do a code review. Please visit https://review.coreboot.org/29327 to review the following change. Change subject: soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller ...................................................................... soc/intel/icelake: Open ports 0x60,0x64 for keyboard controller Change-Id: I6525c2a46eef835dc64682466364a5b8fbb35226 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/soc/intel/icelake/bootblock/pch.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/29327/1 diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index 269e2a3..2fc94f4 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -181,7 +181,8 @@ } /* IO Decode Enable */ - dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN; + dec_en |= SE_LPC_EN | KBC_LPC_EN | MC1_LPC_EN | GAMEL_LPC_EN | + LPC_IOE_KBC_60_64; pci_write_config16(PCH_DEV_LPC, LPC_EN, dec_en); pcr_write16(PID_DMI, PCR_DMI_LPCIOE, dec_en); -- To view, visit https://review.coreboot.org/29327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I6525c2a46eef835dc64682466364a5b8fbb35226 Gerrit-Change-Number: 29327 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: security/tpm: Move TPM2 NVRAM specific settings
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29326 Change subject: security/tpm: Move TPM2 NVRAM specific settings ...................................................................... security/tpm: Move TPM2 NVRAM specific settings * Move TPM2 NVRAM default parameters from vboot to a tpm2 specific header Change-Id: Iec9d1c272ed8d0872c9bbc406e98a19ac7a376bd Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/security/tpm/tss/tcg-2.0/tss_structures.h M src/security/vboot/secdata_tpm.c 2 files changed, 30 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/29326/1 diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index e902f3c..89f7219 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -151,6 +151,36 @@ #define PT_VAR (PT_GROUP * 2) #define TPM_PT_PERMANENT ((TPM_PT)(PT_VAR + 0)) +/* + * Different sets of NVRAM space attributes apply to the "ro" spaces, + * i.e. those which should not be possible to delete or modify once + * the RO exits, and the rest of the NVRAM spaces. + */ +const static TPMA_NV ro_space_attributes = { + .TPMA_NV_PPWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PLATFORMCREATE = 1, + .TPMA_NV_WRITE_STCLEAR = 1, + .TPMA_NV_POLICY_DELETE = 1, +}; + +const static TPMA_NV rw_space_attributes = { + .TPMA_NV_PPWRITE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_PPREAD = 1, + .TPMA_NV_PLATFORMCREATE = 1, +}; + +/* + * This policy digest was obtained using TPM2_PolicyPCR + * selecting only PCR_0 with a value of all zeros. + */ +const static uint8_t pcr0_unchanged_policy[] = { + 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, + 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, + 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; + /* Structures of payloads of various TPM2 commands. */ struct tpm2_get_capability { TPM_CAP capability; diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index c62f18b..286b2be 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -168,35 +168,6 @@ static const uint8_t rec_hash_data[REC_HASH_NV_SIZE] = { }; #if IS_ENABLED(CONFIG_TPM2) -/* - * Different sets of NVRAM space attributes apply to the "ro" spaces, - * i.e. those which should not be possible to delete or modify once - * the RO exits, and the rest of the NVRAM spaces. - */ -const static TPMA_NV ro_space_attributes = { - .TPMA_NV_PPWRITE = 1, - .TPMA_NV_AUTHREAD = 1, - .TPMA_NV_PPREAD = 1, - .TPMA_NV_PLATFORMCREATE = 1, - .TPMA_NV_WRITE_STCLEAR = 1, - .TPMA_NV_POLICY_DELETE = 1, -}; - -const static TPMA_NV rw_space_attributes = { - .TPMA_NV_PPWRITE = 1, - .TPMA_NV_AUTHREAD = 1, - .TPMA_NV_PPREAD = 1, - .TPMA_NV_PLATFORMCREATE = 1, -}; - -/* - * This policy digest was obtained using TPM2_PolicyPCR - * selecting only PCR_0 with a value of all zeros. - */ -const static uint8_t pcr0_unchanged_policy[] = { - 0x09, 0x93, 0x3C, 0xCE, 0xEB, 0xB4, 0x41, 0x11, 0x18, 0x81, 0x1D, - 0xD4, 0x47, 0x78, 0x80, 0x08, 0x88, 0x86, 0x62, 0x2D, 0xD7, 0x79, - 0x94, 0x46, 0x62, 0x26, 0x68, 0x8E, 0xEE, 0xE6, 0x6A, 0xA1}; /* Nothing special in the TPM2 path yet. */ static uint32_t safe_write(uint32_t index, const void *data, uint32_t length) -- To view, visit https://review.coreboot.org/29326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iec9d1c272ed8d0872c9bbc406e98a19ac7a376bd Gerrit-Change-Number: 29326 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Hello Patrick Rudolph, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29324 to look at the new patch set (#3). Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... soc/intel/cannonlake: Add additional UPD * Add CleanMemory option Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/romstage/fsp_params.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29324/3 -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Nico Huber (Code Review) 29 Oct '18

29 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29312 ) Change subject: src: Add missing include <stdint.h> ...................................................................... Patch Set 11: (1 comment) https://review.coreboot.org/#/c/29312/11/src/soc/intel/baytrail/include/soc… File src/soc/intel/baytrail/include/soc/iomap.h: https://review.coreboot.org/#/c/29312/11/src/soc/intel/baytrail/include/soc… PS11, Line 81: /* Read Top of Low Memory (BMBOUND) */ Comment should be kept above the function it comments. -- To view, visit https://review.coreboot.org/29312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Gerrit-Change-Number: 29312 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 13:01:44 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit October 2018