coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: src/drivers/intel/fsp1_1/raminit.c: Missing NON_VOLATILE_STORAGE_HOB ...
by Patrick Rudolph (Code Review) 29 Oct '18

29 Oct '18

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/29320 ) Change subject: src/drivers/intel/fsp1_1/raminit.c: Missing NON_VOLATILE_STORAGE_HOB is not an error ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29320/1/src/drivers/intel/fsp1_1/raminit.c File src/drivers/intel/fsp1_1/raminit.c: https://review.coreboot.org/#/c/29320/1/src/drivers/intel/fsp1_1/raminit.c@… PS1, Line 204: please update the comment here as well -- To view, visit https://review.coreboot.org/29320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0 Gerrit-Change-Number: 29320 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 09:54:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Typo fix
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29321 Change subject: src/soc/intel/braswell/northcluster.c: Typo fix ...................................................................... src/soc/intel/braswell/northcluster.c: Typo fix Correct typo in comment and debug string. BUG=N/A TEST=build Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/security/tpm/tss.h M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/soc/intel/braswell/include/soc/irq.h M src/soc/intel/braswell/northcluster.c M util/cbfstool/cbfstool.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/29321/1 diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index c053df9..2259e79 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -137,7 +137,7 @@ uint32_t tlcl_physical_presence_cmd_enable(void); /** - * Finalize the physical presence settings: sofware PP is enabled, hardware PP + * Finalize the physical presence settings: software PP is enabled, hardware PP * is disabled, and the lifetime lock is set. The TPM error code is returned. */ uint32_t tlcl_finalize_physical_presence(void); diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index ad23d9b..168eac9 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -439,12 +439,12 @@ } /* - * Let's ignore the authorisation section. It should be 5 bytes total, + * Let's ignore the authorization section. It should be 5 bytes total, * just confirm that this is the case and report any discrepancy. */ if (ibuf_remaining(ib) != 5) printk(BIOS_ERR, - "%s:%d - unexpected authorisation seciton size %zd\n", + "%s:%d - unexpected authorization section size %zd\n", __func__, __LINE__, ibuf_remaining(ib)); ibuf_oob_drain(ib, ibuf_remaining(ib)); diff --git a/src/soc/intel/braswell/include/soc/irq.h b/src/soc/intel/braswell/include/soc/irq.h index 4375c20..98b9e56 100644 --- a/src/soc/intel/braswell/include/soc/irq.h +++ b/src/soc/intel/braswell/include/soc/irq.h @@ -177,7 +177,7 @@ # define SCIS_IRQ23 0x07 /* - * In each mainbaord directory there should exist a header file irqroute.h that + * In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 3245a28..ee43c89 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -53,7 +53,7 @@ * +--------------------------+ 0 * * Note that there are really only a few regions that need to enumerated w.r.t. - * coreboot's resrouce model: + * coreboot's resource model: * * +--------------------------+ BMBOUND_HI * | Cacheable/Usable | diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 28e0e5d..ceda785 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -134,7 +134,7 @@ * "top-aligned" offsets from the top of the image region. Works in either * direction: pass in one type of offset and receive the other type. * N.B. A top-aligned offset is always a positive number, and should not be - * confused with a top-aliged *address*, which is its arithmetic inverse. */ + * confused with a top-aligned *address*, which is its arithmetic inverse. */ static unsigned convert_to_from_top_aligned(const struct buffer *region, unsigned offset) { -- To view, visit https://review.coreboot.org/29321 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0362bb8d7c883e7fcbc6a2fc2f9918251f0d8d6e Gerrit-Change-Number: 29321 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: Documentation: Improve payload fit
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29319 ) Change subject: Documentation: Improve payload fit ...................................................................... Patch Set 1: Code-Review+2 Looks good -- To view, visit https://review.coreboot.org/29319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Gerrit-Change-Number: 29319 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 09:34:58 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: src/drivers/intel/fsp1_1/raminit.c: Missing NON_VOLATILE_STORAGE_HOB ...
by Frans Hendriks (Code Review) 29 Oct '18

29 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29320 Change subject: src/drivers/intel/fsp1_1/raminit.c: Missing NON_VOLATILE_STORAGE_HOB is not an error ...................................................................... src/drivers/intel/fsp1_1/raminit.c: Missing NON_VOLATILE_STORAGE_HOB is not an error The missing 7.3 NON_VOLATILE_STORAGE_HOB is reported as error. Change the argument used in printk() to BIOS_DEBUG for this hob. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/raminit.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/29320/1 diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index c7d8722..34bcf0b 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014-2016 Intel Corporation + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -217,7 +218,7 @@ } hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr); if (hob_ptr.Raw == NULL) { - printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); + printk(BIOS_DEBUG, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n"); fsp_verification_failure = (params->pei_data->saved_data == NULL) ? 1 : 0; } else { -- To view, visit https://review.coreboot.org/29320 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice8220149c2e44bb2da010d5a7d8bc4dbeca11e0 Gerrit-Change-Number: 29320 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: Documentation: Improve payload fit
by Patrick Rudolph (Code Review) 29 Oct '18

29 Oct '18

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/29319 Change subject: Documentation: Improve payload fit ...................................................................... Documentation: Improve payload fit * Convert '' to ` * Add example how to use mkimage Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M Documentation/lib/payloads/fit.md 1 file changed, 16 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/29319/1 diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index ac7b3e6..53be92e 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -25,7 +25,7 @@ The FIT parser needs architecure support. ### aarch64 -The source code can be found in ''src/arch/arm64/fit.c''. +The source code can be found in `src/arch/arm64/fit.c`. On aarch64 the kernel (a section named 'kernel') must be in **Image** format and it needs a devicetree (a section named 'fdt') to boot. @@ -83,7 +83,7 @@ ## Building FIT image -The FIT image has to be built by calling ''mkimage''. You can use +The FIT image has to be built by calling `mkimage`. You can use the following example configuration: ``` @@ -148,9 +148,20 @@ }; ``` -It includes a compressed initrd **initramfs.cpio.xz**, which will be -decompressed by the Linux kernel, a compressed kernel **Image.lzma**, which will -be decompressed by the FIT loader and an uncompressed devicetree blob. +Save it as ITS file `config.its` along with the other files defined here: +* target.dtb +* initramfs.cpio.xz +* Image.lzma + +Generate the `uImage` that will be included into the CBFS by calling + +```bash +mkimage -f config.its uImage +``` + +The generated file includes a compressed initrd **initramfs.cpio.xz**, which +will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**, +which will be decompressed by the FIT loader and an uncompressed devicetree blob. [uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto… [U-Boot]: https://www.denx.de/wiki/U-Boot -- To view, visit https://review.coreboot.org/29319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Gerrit-Change-Number: 29319 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: siemens/mc_apl2: Adjust GPIO settings for mc_apl2
by Mario Scheithauer (Code Review) 29 Oct '18

29 Oct '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29318 Change subject: siemens/mc_apl2: Adjust GPIO settings for mc_apl2 ...................................................................... siemens/mc_apl2: Adjust GPIO settings for mc_apl2 This mainboard variant requires GPIO adaptations to match the hardware. Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c 2 files changed, 669 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/29318/1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc index f3c87b2..a6b80e0 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/Makefile.inc @@ -1 +1,4 @@ +romstage-y += gpio.c + +ramstage-y += gpio.c ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c new file mode 100644 index 0000000..f086341 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/gpio.c @@ -0,0 +1,666 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * Copyright (C) 2017-2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#include <commonlib/helpers.h> +#include <baseboard/variants.h> + +/* + * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing' + * table found in EDS vol 1, but some pins aren't grouped functionally in + * the table so those were moved for more logical grouping. + */ +static const struct pad_config gpio_table[] = { + + /* Southwest Community */ + + /* EXT_WAKE0_1V8# */ + PAD_CFG_NF_IOSSTATE(GPIO_205, UP_20K, DEEP, NF1, MASK), + /* EXT_WAKE1_1V8# */ + PAD_CFG_NF_IOSSTATE(GPIO_206, UP_20K, DEEP, NF1, MASK), + /* LAN_WAKE_1V8# */ + PAD_CFG_NF_IOSSTATE(GPIO_207, UP_20K, DEEP, NF1, MASK), + /* PCIE_WAKE3_1V8# */ + PAD_CFG_NF_IOSSTATE(GPIO_208, UP_20K, DEEP, NF1, MASK), + + /* EMMC_CLK */ + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), + /* EMMC_D0 */ + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D1 */ + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D2 */ + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D3 */ + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D4 */ + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D5 */ + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D6 */ + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_D7 */ + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_CMD */ + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), + /* EMMC_RCLK */ + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), + + /* SDIO -- not connected */ + PAD_CFG_NF_IOSSTATE(GPIO_166, DN_20K, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_167, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_168, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_169, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_170, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_171, UP_20K, DEEP, NF1, HIZCRx1), + + /* SDCARD_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* SDCARD_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* SDCARD_D1 */ + PAD_CFG_NF_IOSSTATE(GPIO_174, UP_20K, DEEP, NF1, HIZCRx1), + /* SDCARD_D2 */ + PAD_CFG_NF_IOSSTATE(GPIO_175, UP_20K, DEEP, NF1, HIZCRx1), + /* SDCARD_D3 */ + PAD_CFG_NF_IOSSTATE(GPIO_176, UP_20K, DEEP, NF1, HIZCRx1), + /* SDCARD_CD_1V8# */ + PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), + /* SDCARD_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* Not connected */ + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + /* SDCARD_WP_1V8 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_186, DN_20K, DEEP), + /* SD_PWR_EN_1V8 - Always enabled SDCard. */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_183, 0, DEEP, UP_20K), + + /* West Community */ + + /* I2C_PM_DATA_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_124, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_PM_CLK_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_125, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_CAM0_DATA_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_126, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_CAM0_CLK_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_127, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_CAM1_DATA_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_128, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_CAM1_CLK_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_129, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_GP_DATA_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_130, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_GP_CLK_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_131, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_LCD_DATA_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_132, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* I2C_LCD_CLK_1V8 */ + PAD_CFG_NF_IOSSTATE(GPIO_133, UP_1K, DEEP, NF1, Tx1RxDCRx1), + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_134, NONE, DEEP, Tx0RxDCRx0, SAME), + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_135, NONE, DEEP, Tx0RxDCRx0, SAME), + /* GPIO_PWRBTN# */ + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, + TxDRxE, SAME), + + /* HDA_BCLK_1V8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, DN_20K, DEEP, NF3, MASK, SAME), + /* HDA_WS_SYNC_1V8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_147, DN_20K, DEEP, NF3, MASK, SAME), + /* HDA_SDI_1V8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, DN_20K, DEEP, NF3, MASK, SAME), + /* HDA_SDO_1V8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_149, DN_20K, DEEP, NF3, MASK, SAME), + + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_150, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_151, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_152, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_153, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_154, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_155, DN_20K, DEEP), + + /* PCIE_CLKREQ[0:3]_N */ + PAD_CFG_NF(GPIO_209, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_210, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_211, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_212, UP_20K, DEEP, NF1), + + /* OSC_CLK_OUT_[0:4] -- not connected */ + PAD_CFG_GPI_GPIO_DRIVER(OSC_CLK_OUT_0, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(OSC_CLK_OUT_1, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(OSC_CLK_OUT_2, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(OSC_CLK_OUT_3, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(OSC_CLK_OUT_4, DN_20K, DEEP), + + /* PM_CHARGER_PRSNT */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_AC_PRESENT, DN_20K, DEEP, NF1, MASK, + SAME), + /* PM_BATLOW# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_BATLOW_B, UP_20K, DEEP, NF1, MASK, + SAME), + /* PMU_PLTRST# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PLTRST_B, NONE, DEEP, NF1, MASK, SAME), + /* PMU_PWRBTN# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_PWRBTN_B, UP_20K, DEEP, NF1, MASK, + SAME), + /* SYS_RESET# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_RESETBUTTON_B, NONE, DEEP, NF1, MASK, + SAME), + /* PMU_SLP_S0# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S0_B, NONE, DEEP, NF1, MASK, SAME), + /* PMU_SLP_S3# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S3_B, NONE, DEEP, NF1, MASK, SAME), + /* PMU_SLP_S4# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SLP_S4_B, NONE, DEEP, NF1, MASK, SAME), + /* CLK_32K_SUS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_SUSCLK, NONE, DEEP, NF1, MASK, SAME), + /* EMMC_PWR_EN# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMU_WAKE_B, DN_20K, DEEP, NF1, MASK, SAME), + /* SUS_STAT# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SUS_STAT_B, NONE, DEEP, NF1, MASK, SAME), + /* SUSPWRDNACK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SUSPWRDNACK, NONE, DEEP, NF1, MASK, SAME), + + /* Northwest Community */ + + /* DDI0_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to + * choose between DDI0_AUXP (Port 0: Display Port Auxiliary Channel for + * DP/HDMI) controlled by resistor stuffing options. + */ + PAD_CFG_NF(GPIO_187, UP_20K, DEEP, NF1), + /* DDI0_DDC_CLK_1V8 - I2C Clock for HDMI - Connected to a MUX SEL IC + * to choose between DDI0_AUXN controlled by resistor stuffing options. + */ + PAD_CFG_NF(GPIO_188, UP_20K, DEEP, NF1), + /* DDI1_DDC_DATA_1V8 - I2C Data for HDMI - Connected to a MUX SEL IC to + * choose between DDI1_AUXN. + */ + PAD_CFG_NF(GPIO_189, UP_20K, DEEP, NF1), + /* DDI1_DDC_CLK_1V8 - I2C Clock for HDMI - Connected to a MUX SEL IC + * to choose between DDI1_AUXP. + */ + PAD_CFG_NF(GPIO_190, UP_20K, DEEP, NF1), + + /* Not connected */ + PAD_CFG_NF(GPIO_191, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_192, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_193, DN_20K, DEEP, NF1, Tx0RxDCRx0, + SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_194, DN_20K, DEEP, NF1, Tx0RxDCRx0, + SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_195, DN_20K, DEEP, NF1, Tx0RxDCRx0, + SAME), + + /* EDP_VDD_EN_1V8 (DNI) - Alternative stuffing option for + * PTN3460 LVDS_VDD_EN. + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_196, 1, DEEP, UP_20K), + /* EDP_BKLT_EN_1V8 (DNI) - Alternative stuffing option for + * PTN3460 LVDS_BKLT_EN + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_197, 1, DEEP, UP_20K), + /* EDP_BKLT_CTRL_1V8 - Alternative stuffing option for + * PTN3460 LVDS_BKLT_CTRL + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_198, 1, DEEP, UP_20K), + + /* DDI1_HPD# - Connect to DP1_HPD Hot plug detection signal of SMARC + * Connector. + */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), + /* DDI0_HPD# - Connect to DP0_HPD Hot plug detection signal of SMARC + * Connector. + */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), + + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, DN_20K, DEEP, NF1, Tx0RxDCRx0, + SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, DN_20K, DEEP, NF1, Tx0RxDCRx0, + SAME), + + /* USB2_OC0_1V8# - Connected to (USB0_OC#:MUX_SEL[USB2_OTG_0/USB2_6]), + * (USB1_OC#:USB1), (USB2_OC#:USB2) + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, MASK, SAME), + /* USB2_OC1_1V8# - Connected to (USB3_OC#:USB3), (USB4_OC#:USB4), + * (USB5_OC#:USB5). NOTE: USB2_7_WIBU do not have OC. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, MASK, SAME), + + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS0, UP_20K, DEEP, NF1, TxLASTRxE, + SAME), + /* EDP_HPD# - from HPDRX pin of PTN3460 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS1, UP_20K, DEEP, NF2, TxLASTRxE, + SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_FS2, UP_20K, DEEP, NF1, TxLASTRxE, + SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_RXD, DN_20K, DEEP, NF1, TxLASTRxE, + SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_TXD, DN_20K, DEEP, NF1, TxLASTRxE, + SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMC_SPI_CLK, DN_20K, DEEP, NF1, TxLASTRxE, + SAME), + + /* Not connected */ + PAD_CFG_GPO_GPIO_DRIVER(PMIC_PWRGOOD, 1, DEEP, UP_1K), + PAD_CFG_GPO_GPIO_DRIVER(GPIO_214, 1, DEEP, DN_20K), + PAD_CFG_GPO_GPIO_DRIVER(GPIO_215, 1, DEEP, DN_20K), + /* THERMTRIP_1V8# - Connected to CPLD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1, + TxLASTRxE, SAME), + /* PROCHOT_CPU# - Connected to CPLD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(PROCHOT_B, UP_20K, DEEP, NF1, HIZCRx1, + SAME), + + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(PMIC_I2C_SCL, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(PMIC_I2C_SDA, DN_20K, DEEP), + + /* I2S_MCLK - Connected to SMARC Connector I2S0_CLK - Digital audio + * clock + */ + PAD_CFG_NF(GPIO_74, DN_20K, DEEP, NF1), + /* I2S_BCLK - Connected to SMARC Connector I2S0_LRCK - Left & Right + * audio synchronization clock + */ + PAD_CFG_NF(GPIO_75, DN_20K, DEEP, NF1), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_76, DN_20K, DEEP), + /* I2S_SDI - Connected to SMARC Connector I2S0_SDI - Digital audio + * Input + */ + PAD_CFG_NF(GPIO_77, DN_20K, DEEP, NF1), + /* I2S_SD0 & STRAP_GPIO_78 (int. PU) - Connected to SMARC Connector + * I2S0_SDO - Digital audio Output + */ + PAD_CFG_NF(GPIO_78, DN_20K, DEEP, NF1), + + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_79, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_80, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_81, DN_20K, DEEP), + /* STRAP_GPIO_82 (int. PD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_82, DN_20K, DEEP), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_83, DN_20K, DEEP), + + /* HDA_RST_1V8# - MUX SEL with CPLD pin and then goto GPIO4/HDA_RST# + * pin of SMARC connector + */ + PAD_CFG_NF(GPIO_84, UP_20K, DEEP, NF2), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_85, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_86, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_87, DN_20K, DEEP), + /* STRAP_GPIO_88 (int. PU) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_88, DN_20K, DEEP), + + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_89, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_90, DN_20K, DEEP), + PAD_CFG_GPI_GPIO_DRIVER(GPIO_91, DN_20K, DEEP), + /* STRAP_GPIO_92 (int. PD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_92, DN_20K, DEEP), + + /* CS0 for BIOS SPI. Connected to CPLD. CPLD then MUX SEL to either SPI + * FLASH CHIP on module (SPI_CS_MODULE_1V8#) or to the carrier board + * SPI FLASH Chip (SPI_CS_EXT_1V8#). + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_97, NATIVE, DEEP, NF1, MASK, SAME), + /* CS1 for BIOS SPI. Connected to CPLD. Not used, because we use 1x16MB + * Flash and not 2x8MB Flash. + */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_98, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_MISO_1V8 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_MOSI_1V8. Support dual mode. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_100, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_IO2. Not support quad mode, external pulled-up. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_101, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_IO3. Not support quad mode, external pulled-up. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_102, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_CLK_1V8. Goes to both module SPI chip and carrier board. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_103, NATIVE, DEEP, NF1, MASK, SAME), + /* FST_SPI_CLK_FB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(FST_SPI_CLK_FB, NONE, DEEP, NF1, MASK, + SAME), + + /* SIO_SPI_CLK_1V8 - Connected to ESPI_CK of SMARC connector. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* SIO_SPI_FS0_1V8 - Connected to ESPI_CS0# of SMARC connector. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_105, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* SIO_SPI_FS1_1V8 - Connected to ESPI_CS1# of SMARC connector. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, HIZCRx0, ENPD), + /* SIO_SPI_MISO_1V8 - Connected to ESPI_IO_0 of SMARC connector. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_109, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* SIO_SPI_MOSI_1V8 - Connected to ESPI_IO_1 of SMARC connector. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + + /* STRAP_GPIO_111 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_111, DN_20K, DEEP), + /* STRAP_GPIO_112 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_112, DN_20K, DEEP), + /* STRAP_GPIO_113 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_113, DN_20K, DEEP), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_116, DN_20K, DEEP), + /* STRAP_GPIO_117 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_117, DN_20K, DEEP), + /* STRAP_GPIO_118 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_118, DN_20K, DEEP), + /* STRAP_GPIO_119 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_119, DN_20K, DEEP), + /* STRAP_GPIO_120 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_120, DN_20K, DEEP), + /* STRAP_GPIO_121 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_121, DN_20K, DEEP), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_122, DN_20K, DEEP), + /* STRAP_GPIO_123 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_123, UP_20K, DEEP), + + /* North Community */ + + /* Debug tracing. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, DN_20K, DEEP, NF1, HIZCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, DN_20K, DEEP, NF1, HIZCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, DN_20K, DEEP, NF1, HIZCRx0, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, DEEP, NF1, HIZCRx0, SAME), + + /* OTG_SEL_1V8 - Connected to a USB MUX to select between USB2_DP0 (OTG) + * and USB2_DP6. 1:OTG, 0:USB + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_9, 1, DEEP, UP_20K), + /* EN_I2CPM_EXT_1V8 - Connected to OE pin of I2C Re-driver. + * Allow/Disallow I2C signal to pass through to SMARC Connector. + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_10, 1, DEEP, UP_20K), + /* EN_SMB_EXT_1V8 - Connected to OE pin of I2C Re-driver. + * Allow/Disallow SMBUS signal to pass through to SMARC Connector. + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_11, 0, DEEP, UP_20K), + /* BOOT_SEL2_1V8# - Three Module pins allow the Carrier board user to + * select from eight possible boot devices. + */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_12, UP_20K, DEEP), + /* BOOT_SEL1_1V8# - BOOT_SEL pins shall be weakly pulled up on the + * Module and the pin states decoded by Module logic. + */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_13, UP_20K, DEEP), + /* BOOT_SEL0_1V8# - For details refer to + * SMARC_Hardware_Specification_V200.pdf page 38 chapter 4.17 Boot + * Select + */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_14, UP_20K, DEEP), + /* GPIO_CPLD_TCK_1V8 */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_15, 0, DEEP, DN_20K), + /* GPIO_CPLD_TMS_1V8 */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_16, 0, DEEP, DN_20K), + /* GPIO_CPLD_TDI_1V8 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_17, DN_20K, DEEP), + /* GPIO_CPLD_TDO_1V8 */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_18, 0, DEEP, DN_20K), + /* PM_TEST_1V8# connect to the SMARC Connector TEST# pin. + * Held low by Carrier to invoke Module vendor specific test function. + * Pulled up on Module. Driven by OD part on Carrier. + */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_19, UP_20K, DEEP), + /* MCERR_1V8 - ICT Test Point */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_20, DN_20K, DEEP), + /* IERR_1V8 - ICT Test Point */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_21, DN_20K, DEEP), + /* SLEEP_CPU_1V8# - Connect to the SMARC Connector SLEEP# pin. + * Sleep indicator from Carrier board. May be sourced from user Sleep + * button or Carrier logic. Carrier to float the line in in-active + * state. Active low, level sensitive. Should be de-bounced on the + * Module. Pulled up on Module. Driven by Open Drain (OD) part on + * Carrier. + */ + PAD_CFG_GPI_SCI_IOS(GPIO_22, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, + SAME), + /* LID_CPU_1V8# - Connect to the SMARC Connector LID# pin. + * Lid open/close indication to Module. Low indicates lid closure + * (which system may use to initiate a sleep state). Carrier to float + * the line in in-active state. Active low, level sensitive. Should be + * de-bounced on the Module Pulled up on Module. Driven by OD part on + * Carrier. + */ + PAD_CFG_GPI_SCI_IOS(GPIO_23, UP_20K, DEEP, EDGE_BOTH, INVERT, TxDRxE, + SAME), + /* WDT_IRQ1_1V8# (NMI) - Trigger by CPLD Watchdog module when enabled + * and timeout. + */ + PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + /* WDT_IRQ0_1V8# (SCI) - Refer to Kontron_CPLD.pdf Chapter 6 Watchdog + * Module Description, for how to use it. + */ + PAD_CFG_GPI_SCI(GPIO_25, UP_20K, DEEP, LEVEL, INVERT), + /* SATA_LED# - Connect to the SMARC Connector SATA_ACT# pin. + * Active low SATA activity indicator. If implemented, shall be able to + * sink 24mA or more Carrier LED current. + */ + PAD_CFG_NF(GPIO_26, DN_20K, DEEP, NF5), + + /* SMB_ALERT_GPIO# */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_27, UP_20K, DEEP), + /* GPIO_28_DEBUG - Connect to HOOK5 (ClkOut#) pin of XDP connector */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_28, 1, DEEP, UP_20K), + /* GPIO_29_DEBUG - Connect to HOOK4 (ClkOut) pin of XDP connector */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_29, 0, DEEP, DN_20K), + + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_30, DN_20K, DEEP), + /* CPU_GPIO_1_1V8 (DNI) - Connect to CPLD PIN_K6 (Unused in CPLD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_31, DN_20K, DEEP), + /* CPU_GPIO_2_1V8 (DNI) - Connect to CPLD PIN_J6 (Unused in CPLD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_32, DN_20K, DEEP), + /* Not connected */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_33, DN_20K, DEEP), + + /* STRAP_GPIO_34 (int. PD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_34, DN_20K, DEEP), + /* STRAP_GPIO_35 (int. PD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_35, DN_20K, DEEP), + /* STRAP_GPIO_36 (int. PD) */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_36, DN_20K, DEEP), + /* Not connected */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_37, 0, DEEP, DN_20K), + + /* GPIO_VALID (CPLD=gpio_valid/pi_gpio_en)- This pin Enable the CPLD + * GPIO to the SMARC Connector. + */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_62, 1, DEEP, UP_20K), + /* LVDS_ENABLE_1V8# connect to PTN3460 DP to LVDS converter chip. */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_63, 0, DEEP, DN_20K), + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_64, DN_20K, DEEP, HIZCRx0, SAME), + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_65, DN_20K, DEEP, HIZCRx0, SAME), + /* CAM_CS0_CS1_SEL - Serial Cameras interfaces Select - to select + * between the two MIPI CSI camera interfaces on the SMARC connector. */ + PAD_CFG_GPO_GPIO_DRIVER(GPIO_66, 0, DEEP, DN_20K), + /* MCSI0_RST_1V8# - Reset the MIPI CSI camera interfaces 0 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, DN_20K, HIZCRx0, SAME), + /* MCSI1_RST_1V8# - Reset the MIPI CSI camera interfaces 1 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_68, 0, DEEP, DN_20K, HIZCRx0, SAME), + /* MCSI0_PWR_1V8# - Power for the MIPI CSI camera interfaces 0 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_69, 0, DEEP, DN_20K, Tx1RxDCRx1, + SAME), + /* MCSI1_PWR_1V8# - Power for the MIPI CSI camera interfaces 1 */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_70, 0, DEEP, DN_20K, Tx1RxDCRx1, + SAME), + /* Not connected */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_71, 0, DEEP, DN_20K, HIZCRx0, SAME), + /* Not connected */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_72, 0, DEEP, DN_20K, HIZCRx0, SAME), + /* Not connected */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_73, 0, DEEP, DN_20K, HIZCRx0, SAME), + + /* JTAG_TCK to XDP Header TCK0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(TCK, DN_20K, DEEP, NF1, MASK, SAME), + /* JTAG_TRST# to XDP Header TRST# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(TRST_B, DN_20K, DEEP, NF1, MASK, SAME), + /* JTAG_TMS to XDP Header TMS */ + PAD_CFG_NF_IOSSTATE_IOSTERM(TMS, UP_20K, DEEP, NF1, MASK, SAME), + /* JTAG_TDI to XDP Header TDI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(TDI, UP_20K, DEEP, NF1, MASK, SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(CX_PMODE, NONE, DEEP, NF1, MASK, SAME), + /* TAG_PREQ# to XDP Header OBSFN_A0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(CX_PREQ_B, UP_20K, DEEP, NF1, MASK, SAME), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(JTAGX, UP_20K, DEEP, NF1, MASK, SAME), + /* JTAG_PRDY# to XDP Header OBSFN_A1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(CX_PRDY_B, UP_20K, DEEP, NF1, MASK, SAME), + /* JTAG_TDO to XDP Header TDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(TDO, UP_20K, DEEP, NF1, MASK, SAME), + + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(CNV_BRI_DT, DN_20K, DEEP, MASK, SAME), + /* PM_FORCE_RECOV_1V8# from SMARC Connector FORCE_RECOV#. + * A low on the Module FORCE_RECOV# pin may invoke the SOC native Force + * Recovery mode. + * For x86 systems this signal may be used to load BIOS defaults. + */ + PAD_CFG_GPIO_DRIVER_HI_Z(CNV_BRI_RSP, UP_20K, DEEP, MASK, SAME), + /* Not connected */ + PAD_CFG_GPIO_DRIVER_HI_Z(CNV_RGI_DT, DN_20K, DEEP, MASK, SAME), + /* EMMC_RST# to EMMC IC's RST# pin */ + PAD_CFG_NF_IOSSTATE_IOSTERM(CNV_RGI_RSP, UP_20K, DEEP, NF1, MASK, SAME), + + /* SVID0_ALERT# - Connect to the SVID VR chip. */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SVID0_ALERT_B, NONE, DEEP, NF1, MASK, SAME), + /* SVID0_DATA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SVID0_DATA, UP_20K, DEEP, NF1, MASK, SAME), + /* SVID0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SVID0_CLK, UP_20K, DEEP, NF1, MASK, SAME), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +/* GPIOs needed prior to ramstage. */ +static const struct pad_config early_gpio_table[] = { + + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_0, DN_20K, DEEP, NF1, HIZCRx0, SAME), + /* OBSDATA_A0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_1, DN_20K, DEEP, NF1, HIZCRx0, SAME), + /* OBSDATA_A1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_2, DN_20K, DEEP, NF1, HIZCRx0, SAME), + /* OBSDATA_A2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_3, DN_20K, DEEP, NF1, HIZCRx0, SAME), + /* OBSDATA_A3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_4, DN_20K, DEEP, NF1, HIZCRx0, SAME), + + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* STRAP_GPIO_39 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* STRAP_GPIO_40 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_40, DN_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* Not connected */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* CPU_UART1_RX to SMARC Connector SER0_RX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* CPU_UART1_TX to SMARC Connector SER0_TX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_43, DN_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* CPU_UART1_RTS_1V8# to SMARC Connector SER0_RTS# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* CPU_UART1_CTS_1V8# to SMARC Connector SER0_CTS# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, HIZCRx0, + DISPUPD), + /* CPU_UART2_RX_1V8 to SMARC Connector SER2_RX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, + DISPUPD), + /* CPU_UART2_TX_1V8 to SMARC Connector SER2_TX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, DN_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* CPU_UART2_RTS_1V8# to SMARC Connector SER2_RTS# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, DN_20K, DEEP, NF1, TxLASTRxE, + DISPUPD), + /* CPU_UART2_CTS_1V8# to SMARC Connector SER2_CTS# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_20K, DEEP, NF1, HIZCRx0, + DISPUPD), + + /* Board ID - GPIO_223 */ + PAD_CFG_GPI_GPIO_DRIVER(PMIC_RESET_B, DN_20K, DEEP), + /* Board ID - GPIO_213 */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_213, DN_20K, DEEP), + /* Board ID - GPIO_224 */ + PAD_CFG_GPI_GPIO_DRIVER(PMIC_STDBY, DN_20K, DEEP), + + /* CPU_GPIO_137 - Kontron config : 0:ECC, 1:no ECC (default) */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_137, UP_20K, DEEP, Tx0RxDCRx0, ENPU), + /* CPU_GPIO_138 - Kontron config - RAM Type BIT0 */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_138, UP_20K, DEEP, Tx0RxDCRx0, ENPU), + /* CPU_GPIO_139 - Kontron config - RAM Type BIT1 */ + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_139, UP_20K, DEEP, Tx0RxDCRx0, ENPU), + + /* SMB_ALERT_CPU# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_ALERTB, UP_20K, DEEP, NF1, MASK, SAME), + /* SMB_CLK_S5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_CLK, UP_20K, DEEP, NF1, MASK, SAME), + /* SMB_DATA_S5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(SMB_DATA, UP_20K, DEEP, NF1, MASK, SAME), + + /* LPC_SERIRQ_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1, MASK, + SAME), + /* CLK_25M_LPC_TPM_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, MASK, SAME), + /* CLK_25M_LPC_CPLD_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, MASK, SAME), + /* LPC_AD0_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, MASK, SAME), + /* LPC_AD1_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, MASK, SAME), + /* LPC_AD2_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, MASK, SAME), + /* LPC_AD3_CPU */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, MASK, SAME), + /* LPC_CLKRUN# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, MASK, SAME), + /* LPC_FRAME_CPU# */ + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, MASK, SAME), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} -- To view, visit https://review.coreboot.org/29318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d Gerrit-Change-Number: 29318 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

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Change in coreboot[master]: src: Remove unneeded include <arch/io.h>
by Elyes HAOUAS (Code Review) 29 Oct '18

29 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29307 to look at the new patch set (#19). Change subject: src: Remove unneeded include <arch/io.h> ...................................................................... src: Remove unneeded include <arch/io.h> Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/x86/cpu.c M src/console/die.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/geode_lx/cpubug.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/haswell/romstage.c M src/cpu/x86/lapic/apic_timer.c M src/device/device.c M src/device/pci_device.c M src/device/pci_early.c M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie_early.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/drivers/xgi/z9s/z9s.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/lenovo/h8/h8.c M src/include/device/azalia_device.h M src/include/device/pci_ehci.h M src/lib/edid.c M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/mainboard.c M src/mainboard/amd/mahogany_fam10/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/tilapia_fam10/mptable.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/mptable.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/mptable.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-q35/mainboard.c M src/mainboard/emulation/qemu-q35/romstage.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/gigabyte/ma785gm/mainboard.c M src/mainboard/gigabyte/ma785gm/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gigabyte/ma785gmt/mptable.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/mainboard.c M src/mainboard/gigabyte/ma78gm/mptable.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/auron/variant.h M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/reset.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/iei/kino-780am2-fam10/mainboard.c M src/mainboard/iei/kino-780am2-fam10/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/galileo/gpio.c M src/mainboard/intel/galileo/reg_access.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/stargo2/mainboard_smi.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/mainboard.c M src/mainboard/jetway/pa78vm5/mptable.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/irq_tables.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/roda/rk9/smihandler.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/samsung/stumpy/smihandler.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/mainboard.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdk8/reset_test.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/fsp_sandybridge/finalize.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/fsp_sandybridge/ram_calc.c M src/northbridge/intel/fsp_sandybridge/raminit.c M src/northbridge/intel/fsp_sandybridge/report_platform.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/pcie.c M src/soc/amd/common/block/acpi/halt.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/tsc_freq.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/imgtec/pistachio/include/soc/spi.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/baytrail/sd.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/hda.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/lpss.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/gpio.c M src/soc/samsung/exynos5420/dp.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/bd82x6x/watchdog.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_bd82x6x/early_spi.c M src/southbridge/intel/fsp_bd82x6x/early_usb.c M src/southbridge/intel/fsp_i89xx/early_spi.c M src/southbridge/intel/fsp_i89xx/early_usb.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82870/pci_parity.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/nvidia/ck804/ck804.c M src/southbridge/nvidia/ck804/enable_usbdebug.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/enable_usbdebug.c M src/southbridge/nvidia/mcp55/fadt.c M src/southbridge/nvidia/mcp55/mcp55.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c M src/southbridge/via/common/early_smbus_delay.c M src/southbridge/via/common/early_smbus_is_busy.c M src/southbridge/via/common/early_smbus_reset.c M src/southbridge/via/common/early_smbus_wait_until_ready.c M src/southbridge/via/common/via_early_smbus.h M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c M src/superio/fintek/f71808a/fintek_internal.h M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f71869ad/f71869ad_multifunc.c M src/superio/fintek/f71869ad/fintek_internal.h M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/fintek/f81866d/fintek_internal.h M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/early_serial.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8783ef/it8783ef.h M src/superio/nsc/pc87309/early_serial.c M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/early_serial.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/early_serial.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/early_serial.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/early_serial.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/serverengines/pilot/early_init.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/lpc47n207.h M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 466 files changed, 7 insertions(+), 459 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29307/19 -- To view, visit https://review.coreboot.org/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 19 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi>

1 0

Change in coreboot[master]: mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6
by Aamir Bohra (Code Review) 29 Oct '18

29 Oct '18

Hello Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29316 to look at the new patch set (#2). Change subject: mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6 ...................................................................... mb/intel/icelake_rvp: Update ICL flash layout to support IFWI 1.6 Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- M src/mainboard/intel/icelake_rvp/chromeos.fmd 1 file changed, 16 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/29316/2 -- To view, visit https://review.coreboot.org/29316 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81 Gerrit-Change-Number: 29316 Gerrit-PatchSet: 2 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src: Remove unneeded include <arch/io.h>
by Elyes HAOUAS (Code Review) 29 Oct '18

29 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29307 to look at the new patch set (#18). Change subject: src: Remove unneeded include <arch/io.h> ...................................................................... src: Remove unneeded include <arch/io.h> Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/arm/armv7/mmu.c M src/arch/x86/cpu.c M src/console/die.c M src/cpu/amd/family_10h-family_15h/ram_calc.c M src/cpu/amd/geode_lx/cpubug.c M src/cpu/amd/smm/smm_init.c M src/cpu/intel/haswell/romstage.c M src/cpu/x86/lapic/apic_timer.c M src/device/device.c M src/device/pci_device.c M src/device/pci_early.c M src/drivers/elog/gsmi.c M src/drivers/emulation/qemu/cirrus.c M src/drivers/i2c/at24rf08c/at24rf08c.c M src/drivers/i2c/at24rf08c/lenovo_serials.c M src/drivers/intel/fsp1_1/romstage.c M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/temp_ram_exit.c M src/drivers/intel/gma/intel_ddi.c M src/drivers/intel/gma/vbt.c M src/drivers/ricoh/rce822/rce822.c M src/drivers/sil/3114/sil_sata.c M src/drivers/uart/oxpcie_early.c M src/drivers/xgi/common/xgi_coreboot.c M src/drivers/xgi/common/xgi_coreboot.h M src/drivers/xgi/z9s/z9s.c M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/lenovo/h8/h8.c M src/include/device/azalia_device.h M src/include/device/pci_ehci.h M src/lib/edid.c M src/mainboard/advansus/a785e-i/mainboard.c M src/mainboard/advansus/a785e-i/romstage.c M src/mainboard/amd/bettong/mptable.c M src/mainboard/amd/bimini_fam10/mainboard.c M src/mainboard/amd/db-ft3b-lc/mainboard.c M src/mainboard/amd/db-ft3b-lc/mptable.c M src/mainboard/amd/gardenia/mptable.c M src/mainboard/amd/lamar/mainboard.c M src/mainboard/amd/lamar/mptable.c M src/mainboard/amd/mahogany_fam10/mainboard.c M src/mainboard/amd/mahogany_fam10/mptable.c M src/mainboard/amd/mahogany_fam10/romstage.c M src/mainboard/amd/olivehillplus/mainboard.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/persimmon/mptable.c M src/mainboard/amd/tilapia_fam10/mainboard.c M src/mainboard/amd/tilapia_fam10/mptable.c M src/mainboard/amd/tilapia_fam10/romstage.c M src/mainboard/amd/torpedo/acpi_tables.c M src/mainboard/aopen/dxplplusu/romstage.c M src/mainboard/apple/macbook21/smihandler.c M src/mainboard/apple/macbookair4_2/early_southbridge.c M src/mainboard/asus/am1i-a/mptable.c M src/mainboard/asus/kcma-d8/mptable.c M src/mainboard/asus/kfsn4-dre/acpi_tables.c M src/mainboard/asus/kfsn4-dre/romstage.c M src/mainboard/asus/kgpe-d16/mptable.c M src/mainboard/asus/m4a78-em/mainboard.c M src/mainboard/asus/m4a78-em/mptable.c M src/mainboard/asus/m4a78-em/romstage.c M src/mainboard/asus/m4a785-m/mainboard.c M src/mainboard/asus/m4a785-m/mptable.c M src/mainboard/asus/m4a785-m/romstage.c M src/mainboard/asus/m5a88-v/mainboard.c M src/mainboard/asus/m5a88-v/romstage.c M src/mainboard/asus/maximus_iv_gene-z/romstage.c M src/mainboard/asus/p5qc/romstage.c M src/mainboard/asus/p8h61-m_lx/romstage.c M src/mainboard/avalue/eax-785e/mainboard.c M src/mainboard/avalue/eax-785e/romstage.c M src/mainboard/bap/ode_e20XX/mptable.c M src/mainboard/bap/ode_e21XX/mainboard.c M src/mainboard/biostar/am1ml/mptable.c M src/mainboard/elmex/pcm205400/mptable.c M src/mainboard/emulation/qemu-i440fx/mainboard.c M src/mainboard/emulation/qemu-power8/uart.c M src/mainboard/emulation/qemu-q35/mainboard.c M src/mainboard/emulation/qemu-q35/romstage.c M src/mainboard/emulation/qemu-riscv/uart.c M src/mainboard/emulation/spike-riscv/uart.c M src/mainboard/getac/p470/mainboard.c M src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/gigabyte/ma785gm/mainboard.c M src/mainboard/gigabyte/ma785gm/mptable.c M src/mainboard/gigabyte/ma785gm/romstage.c M src/mainboard/gigabyte/ma785gmt/mainboard.c M src/mainboard/gigabyte/ma785gmt/mptable.c M src/mainboard/gigabyte/ma785gmt/romstage.c M src/mainboard/gigabyte/ma78gm/mainboard.c M src/mainboard/gigabyte/ma78gm/mptable.c M src/mainboard/gigabyte/ma78gm/romstage.c M src/mainboard/gizmosphere/gizmo2/mptable.c M src/mainboard/google/auron/variant.h M src/mainboard/google/beltino/chromeos.c M src/mainboard/google/beltino/smihandler.c M src/mainboard/google/butterfly/chromeos.c M src/mainboard/google/butterfly/mainboard_smi.c M src/mainboard/google/butterfly/romstage.c M src/mainboard/google/eve/smihandler.c M src/mainboard/google/foster/mainboard.c M src/mainboard/google/foster/reset.c M src/mainboard/google/glados/smihandler.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/jecht/chromeos.c M src/mainboard/google/jecht/smihandler.c M src/mainboard/google/kahlee/mptable.c M src/mainboard/google/link/mainboard_smi.c M src/mainboard/google/link/romstage.c M src/mainboard/google/nyan/romstage.c M src/mainboard/google/nyan_big/romstage.c M src/mainboard/google/nyan_blaze/romstage.c M src/mainboard/google/oak/mainboard.c M src/mainboard/google/octopus/ec.c M src/mainboard/google/parrot/chromeos.c M src/mainboard/google/parrot/ec.c M src/mainboard/google/parrot/romstage.c M src/mainboard/google/parrot/smihandler.c M src/mainboard/google/rambi/mainboard.c M src/mainboard/google/smaug/reset.c M src/mainboard/google/stout/chromeos.c M src/mainboard/google/stout/ec.c M src/mainboard/google/stout/mainboard.c M src/mainboard/google/stout/mainboard_smi.c M src/mainboard/google/stout/romstage.c M src/mainboard/google/urara/mainboard.c M src/mainboard/google/veyron/sdram_configs.c M src/mainboard/google/veyron_mickey/sdram_configs.c M src/mainboard/google/veyron_rialto/sdram_configs.c M src/mainboard/hp/2570p/romstage.c M src/mainboard/hp/2760p/romstage.c M src/mainboard/hp/8460p/romstage.c M src/mainboard/hp/8470p/romstage.c M src/mainboard/hp/8770w/romstage.c M src/mainboard/hp/compaq_8200_elite_sff/romstage.c M src/mainboard/hp/folio_9470m/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/mainboard.c M src/mainboard/hp/revolve_810_g1/romstage.c M src/mainboard/iei/kino-780am2-fam10/mainboard.c M src/mainboard/iei/kino-780am2-fam10/mptable.c M src/mainboard/iei/kino-780am2-fam10/romstage.c M src/mainboard/intel/bayleybay_fsp/mainboard.c M src/mainboard/intel/bayleybay_fsp/romstage.c M src/mainboard/intel/camelbackmountain_fsp/mainboard.c M src/mainboard/intel/cannonlake_rvp/smihandler.c M src/mainboard/intel/d945gclf/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/mainboard/intel/emeraldlake2/mainboard.c M src/mainboard/intel/galileo/gpio.c M src/mainboard/intel/galileo/reg_access.c M src/mainboard/intel/kblrvp/chromeos.c M src/mainboard/intel/kblrvp/smihandler.c M src/mainboard/intel/kunimitsu/smihandler.c M src/mainboard/intel/stargo2/mainboard_smi.c M src/mainboard/intel/stargo2/romstage.c M src/mainboard/intel/wtm2/chromeos.c M src/mainboard/jetway/nf81-t56n-lf/mptable.c M src/mainboard/jetway/pa78vm5/mainboard.c M src/mainboard/jetway/pa78vm5/mptable.c M src/mainboard/jetway/pa78vm5/romstage.c M src/mainboard/kontron/986lcd-m/romstage.c M src/mainboard/kontron/ktqm77/mainboard.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/lenovo/s230u/smihandler.c M src/mainboard/lenovo/t400/acpi_tables.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x200/acpi_tables.c M src/mainboard/msi/ms9652_fam10/romstage.c M src/mainboard/pcengines/alix1c/romstage.c M src/mainboard/pcengines/alix2d/irq_tables.c M src/mainboard/pcengines/apu1/mptable.c M src/mainboard/roda/rk9/acpi_tables.c M src/mainboard/roda/rk9/smihandler.c M src/mainboard/samsung/lumpy/chromeos.c M src/mainboard/samsung/lumpy/smihandler.c M src/mainboard/samsung/stumpy/chromeos.c M src/mainboard/samsung/stumpy/romstage.c M src/mainboard/samsung/stumpy/smihandler.c M src/mainboard/siemens/mc_tcu3/mainboard.c M src/mainboard/siemens/mc_tcu3/romstage.c M src/mainboard/sifive/hifive-unleashed/mainboard.c M src/mainboard/supermicro/h8dmr_fam10/romstage.c M src/mainboard/supermicro/h8qme_fam10/romstage.c M src/mainboard/supermicro/h8scm_fam10/mainboard.c M src/mainboard/supermicro/h8scm_fam10/mptable.c M src/mainboard/supermicro/h8scm_fam10/romstage.c M src/mainboard/tyan/s2912_fam10/romstage.c M src/northbridge/amd/agesa/family12/northbridge.c M src/northbridge/amd/agesa/family14/northbridge.c M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdfam10/amdfam10_util.c M src/northbridge/amd/amdfam10/ht_config.c M src/northbridge/amd/amdfam10/northbridge.c M src/northbridge/amd/amdfam10/raminit_amdmct.c M src/northbridge/amd/amdk8/reset_test.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c M src/northbridge/intel/e7505/northbridge.c M src/northbridge/intel/fsp_rangeley/acpi.c M src/northbridge/intel/fsp_rangeley/northbridge.c M src/northbridge/intel/fsp_rangeley/raminit.c M src/northbridge/intel/fsp_sandybridge/finalize.c M src/northbridge/intel/fsp_sandybridge/northbridge.c M src/northbridge/intel/fsp_sandybridge/ram_calc.c M src/northbridge/intel/fsp_sandybridge/raminit.c M src/northbridge/intel/fsp_sandybridge/report_platform.c M src/northbridge/intel/gm45/igd.c M src/northbridge/intel/gm45/iommu.c M src/northbridge/intel/gm45/northbridge.c M src/northbridge/intel/gm45/pm.c M src/northbridge/intel/gm45/thermal.c M src/northbridge/intel/haswell/finalize.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/haswell/ram_calc.c M src/northbridge/intel/haswell/report_platform.c M src/northbridge/intel/i440bx/debug.c M src/northbridge/intel/i945/debug.c M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/i945/ram_calc.c M src/northbridge/intel/nehalem/finalize.c M src/northbridge/intel/nehalem/northbridge.c M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/pineview/ram_calc.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_ivy.c M src/northbridge/via/vx900/chrome9hd.c M src/northbridge/via/vx900/early_vx900.c M src/northbridge/via/vx900/lpc.c M src/northbridge/via/vx900/pcie.c M src/soc/amd/common/block/acpi/halt.c M src/soc/amd/stoneyridge/hda.c M src/soc/amd/stoneyridge/include/soc/northbridge.h M src/soc/amd/stoneyridge/include/soc/pci_devs.h M src/soc/amd/stoneyridge/include/soc/smi.h M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/romstage.c M src/soc/amd/stoneyridge/sata.c M src/soc/amd/stoneyridge/sm.c M src/soc/amd/stoneyridge/tsc_freq.c M src/soc/cavium/common/bdk-coreboot.c M src/soc/imgtec/pistachio/include/soc/spi.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/smihandler.c M src/soc/intel/baytrail/dptf.c M src/soc/intel/baytrail/elog.c M src/soc/intel/baytrail/emmc.c M src/soc/intel/baytrail/hda.c M src/soc/intel/baytrail/lpss.c M src/soc/intel/baytrail/memmap.c M src/soc/intel/baytrail/perf_power.c M src/soc/intel/baytrail/romstage/early_spi.c M src/soc/intel/baytrail/sd.c M src/soc/intel/braswell/elog.c M src/soc/intel/braswell/emmc.c M src/soc/intel/braswell/gfx.c M src/soc/intel/braswell/hda.c M src/soc/intel/braswell/lpss.c M src/soc/intel/braswell/memmap.c M src/soc/intel/braswell/romstage/early_spi.c M src/soc/intel/braswell/sata.c M src/soc/intel/braswell/sd.c M src/soc/intel/broadwell/acpi.c M src/soc/intel/broadwell/bootblock/pch.c M src/soc/intel/broadwell/bootblock/systemagent.c M src/soc/intel/broadwell/ehci.c M src/soc/intel/broadwell/include/soc/pci_devs.h M src/soc/intel/broadwell/iobp.c M src/soc/intel/broadwell/me_status.c M src/soc/intel/broadwell/memmap.c M src/soc/intel/broadwell/pch.c M src/soc/intel/broadwell/romstage/raminit.c M src/soc/intel/broadwell/romstage/report_platform.c M src/soc/intel/broadwell/romstage/romstage.c M src/soc/intel/broadwell/romstage/smbus.c M src/soc/intel/broadwell/romstage/spi.c M src/soc/intel/broadwell/romstage/uart.c M src/soc/intel/broadwell/systemagent.c M src/soc/intel/cannonlake/include/soc/pci_devs.h M src/soc/intel/cannonlake/memmap.c M src/soc/intel/cannonlake/romstage/romstage.c M src/soc/intel/common/block/cpu/cpulib.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/p2sb/p2sb.c M src/soc/intel/common/block/systemagent/systemagent.c M src/soc/intel/common/block/xdci/xdci.c M src/soc/intel/common/block/xhci/xhci.c M src/soc/intel/common/pch/lockdown/lockdown.c M src/soc/intel/denverton_ns/include/soc/pci_devs.h M src/soc/intel/denverton_ns/npk.c M src/soc/intel/denverton_ns/xhci.c M src/soc/intel/fsp_baytrail/gfx.c M src/soc/intel/fsp_baytrail/include/soc/i2c.h M src/soc/intel/fsp_baytrail/lpss.c M src/soc/intel/fsp_baytrail/memmap.c M src/soc/intel/fsp_broadwell_de/romstage/romstage.c M src/soc/intel/fsp_broadwell_de/smihandler.c M src/soc/intel/fsp_broadwell_de/smmrelocate.c M src/soc/intel/icelake/include/soc/pci_devs.h M src/soc/intel/icelake/memmap.c M src/soc/intel/icelake/romstage/romstage.c M src/soc/intel/quark/include/soc/reg_access.h M src/soc/intel/quark/sd.c M src/soc/intel/quark/spi_debug.c M src/soc/intel/quark/storage_test.c M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/elog.c M src/soc/intel/skylake/me.c M src/soc/intel/skylake/romstage/romstage.c M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/systemagent.c M src/soc/intel/skylake/vr_config.c M src/soc/mediatek/mt8173/memory.c M src/soc/mediatek/mt8173/mt6391.c M src/soc/nvidia/tegra124/dp.c M src/soc/nvidia/tegra124/soc.c M src/soc/nvidia/tegra124/sor.c M src/soc/nvidia/tegra210/dp.c M src/soc/nvidia/tegra210/funitcfg.c M src/soc/nvidia/tegra210/jdi_25x18_display/panel-jdi-lpm102a188a.c M src/soc/nvidia/tegra210/mipi-phy.c M src/soc/nvidia/tegra210/mipi_dsi.c M src/soc/nvidia/tegra210/soc.c M src/soc/nvidia/tegra210/sor.c M src/soc/qualcomm/ipq40xx/i2c.c M src/soc/qualcomm/ipq806x/i2c.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/decompressor.c M src/soc/rockchip/rk3399/gpio.c M src/soc/samsung/exynos5420/dp.c M src/southbridge/amd/agesa/hudson/hda.c M src/southbridge/amd/agesa/hudson/lpc.c M src/southbridge/amd/agesa/hudson/sata.c M src/southbridge/amd/agesa/hudson/sd.c M src/southbridge/amd/agesa/hudson/sm.c M src/southbridge/amd/agesa/hudson/usb.c M src/southbridge/amd/amd8111/smbus.c M src/southbridge/amd/amd8111/usb.c M src/southbridge/amd/cimx/sb800/cfg.c M src/southbridge/amd/cimx/sb800/lpc.c M src/southbridge/amd/pi/hudson/hda.c M src/southbridge/amd/pi/hudson/sata.c M src/southbridge/amd/pi/hudson/sd.c M src/southbridge/amd/pi/hudson/sm.c M src/southbridge/amd/pi/hudson/usb.c M src/southbridge/amd/rs780/cmn.c M src/southbridge/amd/rs780/early_setup.c M src/southbridge/amd/sb700/fadt.c M src/southbridge/amd/sb700/lpc.c M src/southbridge/amd/sb800/fadt.c M src/southbridge/amd/sb800/lpc.c M src/southbridge/amd/sr5650/cmn.h M src/southbridge/broadcom/bcm5785/lpc.c M src/southbridge/intel/bd82x6x/early_spi.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/usb_xhci.c M src/southbridge/intel/bd82x6x/watchdog.c M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/pmutil.c M src/southbridge/intel/common/usb_debug.c M src/southbridge/intel/fsp_bd82x6x/early_spi.c M src/southbridge/intel/fsp_bd82x6x/early_usb.c M src/southbridge/intel/fsp_i89xx/early_spi.c M src/southbridge/intel/fsp_i89xx/early_usb.c M src/southbridge/intel/fsp_rangeley/early_spi.c M src/southbridge/intel/fsp_rangeley/early_usb.c M src/southbridge/intel/fsp_rangeley/smbus.c M src/southbridge/intel/i82371eb/i82371eb.h M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801ix/smihandler.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/i82870/pci_parity.c M src/southbridge/intel/ibexpeak/madt.c M src/southbridge/intel/lynxpoint/early_spi.c M src/southbridge/intel/lynxpoint/early_usb.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/rcba.c M src/southbridge/nvidia/ck804/ck804.c M src/southbridge/nvidia/ck804/enable_usbdebug.c M src/southbridge/nvidia/ck804/smbus.c M src/southbridge/nvidia/mcp55/enable_usbdebug.c M src/southbridge/nvidia/mcp55/fadt.c M src/southbridge/nvidia/mcp55/mcp55.c M src/southbridge/nvidia/mcp55/smbus.c M src/southbridge/ricoh/rl5c476/rl5c476.c M src/southbridge/ti/pci1x2x/pci1x2x.c M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c M src/southbridge/ti/pcixx12/pcixx12.c M src/southbridge/via/common/early_smbus_delay.c M src/southbridge/via/common/early_smbus_is_busy.c M src/southbridge/via/common/early_smbus_reset.c M src/southbridge/via/common/early_smbus_wait_until_ready.c M src/southbridge/via/common/via_early_smbus.h M src/superio/fintek/f71805f/superio.c M src/superio/fintek/f71808a/f71808a_hwm.c M src/superio/fintek/f71808a/f71808a_multifunc.c M src/superio/fintek/f71808a/fintek_internal.h M src/superio/fintek/f71808a/superio.c M src/superio/fintek/f71859/superio.c M src/superio/fintek/f71863fg/superio.c M src/superio/fintek/f71869ad/f71869ad_hwm.c M src/superio/fintek/f71869ad/f71869ad_multifunc.c M src/superio/fintek/f71869ad/fintek_internal.h M src/superio/fintek/f71869ad/superio.c M src/superio/fintek/f71872/superio.c M src/superio/fintek/f81865f/superio.c M src/superio/fintek/f81866d/f81866d_hwm.c M src/superio/fintek/f81866d/f81866d_uart.c M src/superio/fintek/f81866d/fintek_internal.h M src/superio/fintek/f81866d/superio.c M src/superio/ite/it8623e/superio.c M src/superio/ite/it8712f/superio.c M src/superio/ite/it8716f/superio.c M src/superio/ite/it8718f/early_serial.c M src/superio/ite/it8728f/superio.c M src/superio/ite/it8783ef/it8783ef.h M src/superio/nsc/pc87309/early_serial.c M src/superio/nsc/pc87309/superio.c M src/superio/nsc/pc87360/early_serial.c M src/superio/nsc/pc87360/superio.c M src/superio/nsc/pc87366/early_serial.c M src/superio/nsc/pc87366/superio.c M src/superio/nsc/pc87382/superio.c M src/superio/nsc/pc87384/superio.c M src/superio/nsc/pc87392/early_serial.c M src/superio/nsc/pc87392/superio.c M src/superio/nsc/pc87417/early_serial.c M src/superio/nsc/pc87417/superio.c M src/superio/nsc/pc97317/superio.c M src/superio/nuvoton/nct5104d/superio.c M src/superio/nuvoton/nct5572d/superio.c M src/superio/nuvoton/nct6776/superio.c M src/superio/nuvoton/nct6779d/superio.c M src/superio/nuvoton/nct6791d/superio.c M src/superio/nuvoton/wpcm450/superio.c M src/superio/renesas/m3885x/superio.c M src/superio/serverengines/pilot/early_init.c M src/superio/smsc/dme1737/superio.c M src/superio/smsc/kbc1100/superio.c M src/superio/smsc/lpc47b272/superio.c M src/superio/smsc/lpc47b397/superio.c M src/superio/smsc/lpc47m10x/superio.c M src/superio/smsc/lpc47m15x/superio.c M src/superio/smsc/lpc47n207/lpc47n207.h M src/superio/smsc/lpc47n227/superio.c M src/superio/smsc/mec1308/superio.c M src/superio/smsc/sch4037/superio.c M src/superio/smsc/sio1036/superio.c M src/superio/smsc/smscsuperio/superio.c M src/superio/winbond/w83627dhg/superio.c M src/superio/winbond/w83627ehg/superio.c M src/superio/winbond/w83627hf/superio.c M src/superio/winbond/w83627thg/superio.c M src/superio/winbond/w83627uhg/superio.c M src/superio/winbond/w83667hg-a/superio.c M src/superio/winbond/w83977tf/superio.c M src/superio/winbond/wpcd376i/superio.c 472 files changed, 7 insertions(+), 465 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/29307/18 -- To view, visit https://review.coreboot.org/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 18 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: src: Remove unneeded include <arch/io.h>
by Elyes HAOUAS (Code Review) 29 Oct '18

29 Oct '18

Elyes HAOUAS has posted comments on this change. ( https://review.coreboot.org/29307 ) Change subject: src: Remove unneeded include <arch/io.h> ...................................................................... Patch Set 17: (1 comment) https://review.coreboot.org/#/c/29307/17/src/mainboard/asus/maximus_iv_gene… File src/mainboard/asus/maximus_iv_gene-z/romstage.c: https://review.coreboot.org/#/c/29307/17/src/mainboard/asus/maximus_iv_gene… PS17, Line 17: > `PNP_DEV`, for example, is used in this file, but only defined in […] Thank you. I'll fix it -- To view, visit https://review.coreboot.org/29307 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia18c77876121594a272a07d56acfaa863d0ccb25 Gerrit-Change-Number: 29307 Gerrit-PatchSet: 17 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-Comment-Date: Mon, 29 Oct 2018 08:13:05 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit October 2018