coreboot-gerrit October 2018

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Change in coreboot[master]: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the...
by Philipp Hug (Code Review) 29 Oct '18

29 Oct '18

Philipp Hug has uploaded this change for review. ( https://review.coreboot.org/29339 Change subject: src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode ...................................................................... src/arch/riscv/misaligned.c: Fix an off-by-one error when loading the opcode Pointer to opcode increases by unit uint16_t not byte. Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/misaligned.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/29339/1 diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index ba96102..ebff2d6 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -160,7 +160,7 @@ static int fetch_32bit_instruction(uintptr_t vaddr, uintptr_t *insn, int *size) { uint32_t l = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 0); - uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 2); + uint32_t h = (uint32_t)mprv_read_mxr_u16((uint16_t *)vaddr + 1); uint32_t ins = (h << 16) | l; if ((EXTRACT_FIELD(ins, 0x3) == 3) && (EXTRACT_FIELD(ins, 0x1c) != 0x7)) { -- To view, visit https://review.coreboot.org/29339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2986ca5402ad86d80e0eb955478bfbdc5d50e1f5 Gerrit-Change-Number: 29339 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx>

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Change in coreboot[master]: soc/amd/stoneyridge: Get rid of void pointer math
by Richard Spiegel (Code Review) 29 Oct '18

29 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29337 Change subject: soc/amd/stoneyridge: Get rid of void pointer math ...................................................................... soc/amd/stoneyridge: Get rid of void pointer math Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects. BUG=b:118484178 TEST=Build and boot grunt. Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/northbridge.c M src/soc/amd/stoneyridge/southbridge.c 2 files changed, 17 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/29337/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2ae52c..8d2e99f 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -182,20 +182,22 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest) { - void *addr, *current; + u8 *addr, *current; /* Skip the HEST header. */ - current = (void *)(hest + 1); + current = (u8 *)(hest + 1); addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, + (acpi_hest_esd_t *)current, 0, + (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2); addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, - (void *)((u32)addr + 2), *(UINT16 *)addr - 2); + current += acpi_create_hest_error_source(hest, + (acpi_hest_esd_t *)current, 1, + (u8 *)((u32)addr + 2), *(UINT16 *)addr - 2); return (unsigned long)current; } diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 326ea61..40f9cbe 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -429,27 +429,27 @@ void sb_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_SPEED_CONFIG, + write16((u16 *)((u8 *)base + SPI100_SPEED_CONFIG), (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) | (tpm << SPI_TPM_SPEED_NEW_SH)); - write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); + write16((u16 *)((u8 *)base + SPI100_ENABLE), SPI_USE_SPI100); } void sb_disable_4dw_burst(void) { uintptr_t base = sb_spibase(); - write16((void *)base + SPI100_HOST_PREF_CONFIG, - read16((void *)base + SPI100_HOST_PREF_CONFIG) + write16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG), + read16((u16 *)((u8 *)base + SPI100_HOST_PREF_CONFIG)) & ~SPI_RD4DW_EN_HOST); } void sb_read_mode(u32 mode) { uintptr_t base = sb_spibase(); - write32((void *)base + SPI_CNTRL0, - (read32((void *)base + SPI_CNTRL0) + write32((u32 *)((u8 *)base + SPI_CNTRL0), + (read32((u32 *)((u8 *)base + SPI_CNTRL0)) & ~SPI_READ_MODE_MASK) | mode); } @@ -914,11 +914,11 @@ gnvs->aoac.espi = 1; amdfw_rom = 0x20000 - (0x80000 << CONFIG_AMD_FWM_POSITION_INDEX); - xhci_fw = read32((void *)(amdfw_rom + XHCI_FW_SIG_OFFSET)); + xhci_fw = read32((u32 *)((u8 *)amdfw_rom + XHCI_FW_SIG_OFFSET)); - fwaddr = 2 + read16((void *)(xhci_fw + XHCI_FW_ADDR_OFFSET + fwaddr = 2 + read16((u16 *)((u8 *)xhci_fw + XHCI_FW_ADDR_OFFSET + XHCI_FW_BOOTRAM_SIZE)); - fwsize = read16((void *)(xhci_fw + XHCI_FW_SIZE_OFFSET + fwsize = read16((u16 *)((u8 *)xhci_fw + XHCI_FW_SIZE_OFFSET + XHCI_FW_BOOTRAM_SIZE)); gnvs->fw00 = 0; gnvs->fw01 = ((32 * KiB) << 16) + 0; -- To view, visit https://review.coreboot.org/29337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5 Gerrit-Change-Number: 29337 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: mb/sifive/hifive-unleashed: Use if (IS_ENABLED(...))
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29336 Change subject: mb/sifive/hifive-unleashed: Use if (IS_ENABLED(...)) ...................................................................... mb/sifive/hifive-unleashed: Use if (IS_ENABLED(...)) "if" is preferable over "#if", because it lets the compiler perform syntax and type checks even if CONFIG_CONSOLE_SERIAL is disabled. Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/mainboard/sifive/hifive-unleashed/romstage.c 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/29336/1 diff --git a/src/mainboard/sifive/hifive-unleashed/romstage.c b/src/mainboard/sifive/hifive-unleashed/romstage.c index 3767491..8277141 100644 --- a/src/mainboard/sifive/hifive-unleashed/romstage.c +++ b/src/mainboard/sifive/hifive-unleashed/romstage.c @@ -36,9 +36,8 @@ clock_init(); // re-initialize UART - #if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) uart_init(CONFIG_UART_FOR_CONSOLE); - #endif sdram_init(); -- To view, visit https://review.coreboot.org/29336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I45a763f2d854fbe9082795bc74de7a9d0fded3c9 Gerrit-Change-Number: 29336 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by build bot (Jenkins) (Code Review) 29 Oct '18

29 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29333 ) Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... Patch Set 2: (4 comments) https://review.coreboot.org/#/c/29333/2/src/soc/intel/braswell/northcluster… File src/soc/intel/braswell/northcluster.c: https://review.coreboot.org/#/c/29333/2/src/soc/intel/braswell/northcluster… PS2, Line 110: if (fsp_reserved_memory_area){ space required before the open brace '{' https://review.coreboot.org/#/c/29333/2/src/soc/intel/braswell/northcluster… PS2, Line 111: fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area)); line over 80 characters https://review.coreboot.org/#/c/29333/2/src/soc/intel/braswell/northcluster… PS2, Line 113: else that open brace { should be on the previous line https://review.coreboot.org/#/c/29333/2/src/soc/intel/braswell/northcluster… PS2, Line 113: else else should follow close brace '}' -- To view, visit https://review.coreboot.org/29333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Gerrit-Change-Number: 29333 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 14:39:00 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29331 ) Change subject: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid. ...................................................................... src/drivers/pc80/tpm/tis.c: Dont use port value when invalid. port is allocated in ACPI, without checking for value. Don't use port value when zero. BUG=N/A TEST=Portwell PQ-M107 Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> Reviewed-on: https://review.coreboot.org/29331 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/pc80/tpm/tis.c 1 file changed, 3 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 6b84614..f7d9d6f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -911,7 +912,8 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_write_mem32fixed(1, CONFIG_TPM_TIS_BASE_ADDRESS, 0x5000); - acpigen_write_io16(port, port, 1, 2, 1); + if (port) + acpigen_write_io16(port, port, 1, 2, 1); if (CONFIG_TPM_PIRQ) { /* -- To view, visit https://review.coreboot.org/29331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Gerrit-Change-Number: 29331 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid.
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29331 ) Change subject: src/drivers/pc80/tpm/tis.c: Dont use port value when invalid. ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia44281b82d003b29bffbf985b774ddd661b65c4e Gerrit-Change-Number: 29331 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 14:26:36 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/sifive/fu540: Add helper function to get tlclk frequency
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29335 ) Change subject: soc/sifive/fu540: Add helper function to get tlclk frequency ...................................................................... Patch Set 1: Philipp, how does TLCLKSEL work? Wesley Terpstra said on the forum that it determines if tlclk is coreclk or coreclk/2, but how does software read it out? (https://forums.sifive.com/t/hifive-unleashed-documentation-is-here/1152/9) -- To view, visit https://review.coreboot.org/29335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Gerrit-Change-Number: 29335 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Comment-Date: Mon, 29 Oct 2018 14:26:28 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/sifive/fu540: Add helper function to get tlclk frequency
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29335 Change subject: soc/sifive/fu540: Add helper function to get tlclk frequency ...................................................................... soc/sifive/fu540: Add helper function to get tlclk frequency tlclk is not specific to the UART block in the FU540, so let's calculate its frequency in clock.c. Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/include/soc/clock.h M src/soc/sifive/fu540/uart.c 3 files changed, 13 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/29335/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index a8b61f1..edebe42 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -262,3 +262,14 @@ / (divr + 1) / (1ul << divq); } + +/* Get the TileLink clock's frequency, in KHz */ +int clock_get_tlclk_khz(void) +{ + /* + * The TileLink bus and most peripherals use tlclk, which is coreclk/2, + * as input. + */ + + return clock_get_coreclk_khz() / 2; +} diff --git a/src/soc/sifive/fu540/include/soc/clock.h b/src/soc/sifive/fu540/include/soc/clock.h index d54c666..706c9c0 100644 --- a/src/soc/sifive/fu540/include/soc/clock.h +++ b/src/soc/sifive/fu540/include/soc/clock.h @@ -18,5 +18,6 @@ void clock_init(void); int clock_get_coreclk_khz(void); +int clock_get_tlclk_khz(void); #endif /* __SOC_SIFIVE_HIFIFE_U_CLOCK_H__ */ diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index 454b13d..b59b789 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -29,9 +29,5 @@ unsigned int uart_platform_refclk(void) { - /* - * The SiFive UART uses tlclk, which is coreclk/2, as input - */ - - return clock_get_coreclk_khz() * KHz / 2; + return clock_get_tlclk_khz() * KHz; } -- To view, visit https://review.coreboot.org/29335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I270920027f1132253e413a1bf9feb4fe279b651a Gerrit-Change-Number: 29335 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/sifive/fu540: Simplify UART refclk calculation
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29334 Change subject: soc/sifive/fu540: Simplify UART refclk calculation ...................................................................... soc/sifive/fu540: Simplify UART refclk calculation clock_get_coreclk_khz() already detects whether the PLL or the input clock (hfclk) is used. Tested on HiFive Unleashed. Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M src/soc/sifive/fu540/Makefile.inc M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/uart.c 3 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/29334/1 diff --git a/src/soc/sifive/fu540/Makefile.inc b/src/soc/sifive/fu540/Makefile.inc index e2bdd03..d9bcb2c 100644 --- a/src/soc/sifive/fu540/Makefile.inc +++ b/src/soc/sifive/fu540/Makefile.inc @@ -17,6 +17,7 @@ bootblock-y += clint.c bootblock-y += media.c bootblock-y += bootblock.c +bootblock-y += clock.c romstage-y += uart.c romstage-y += media.c diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 20dce23..a8b61f1 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -242,6 +242,7 @@ } #endif /* ENV_ROMSTAGE */ +/* Get the core clock's frequency, in KHz */ int clock_get_coreclk_khz(void) { if (read32(&prci->coreclksel) & PRCI_CORECLK_MASK) diff --git a/src/soc/sifive/fu540/uart.c b/src/soc/sifive/fu540/uart.c index b563be1..454b13d 100644 --- a/src/soc/sifive/fu540/uart.c +++ b/src/soc/sifive/fu540/uart.c @@ -30,11 +30,8 @@ unsigned int uart_platform_refclk(void) { /* - * The SiFive UART uses tlclk, which is coreclk/2 as input + * The SiFive UART uses tlclk, which is coreclk/2, as input */ - if (ENV_BOOTBLOCK) - return 33330000 / 2; - else - return clock_get_coreclk_khz() * KHz / 2; + return clock_get_coreclk_khz() * KHz / 2; } -- To view, visit https://review.coreboot.org/29334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I264977b0de0b81ef74a014984b6d33638ab33f4b Gerrit-Change-Number: 29334 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP mem...
by build bot (Jenkins) (Code Review) 29 Oct '18

29 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29333 ) Change subject: src/soc/intel/braswell/northcluster.c: Correct calculation of FSP memory area ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/29333/1/src/soc/intel/braswell/northcluster… File src/soc/intel/braswell/northcluster.c: https://review.coreboot.org/#/c/29333/1/src/soc/intel/braswell/northcluster… PS1, Line 110: if (fsp_reserved_memory_area){ space required before the open brace '{' https://review.coreboot.org/#/c/29333/1/src/soc/intel/braswell/northcluster… PS1, Line 111: fsp_res_base_k = (RES_IN_KIB((unsigned int)fsp_reserved_memory_area)); line over 80 characters https://review.coreboot.org/#/c/29333/1/src/soc/intel/braswell/northcluster… PS1, Line 113: else that open brace { should be on the previous line https://review.coreboot.org/#/c/29333/1/src/soc/intel/braswell/northcluster… PS1, Line 113: else else should follow close brace '}' -- To view, visit https://review.coreboot.org/29333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If68bda39ba2b1f3be4ed4bc872710be7bbd4948b Gerrit-Change-Number: 29333 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 14:00:29 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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coreboot-gerrit October 2018