coreboot-gerrit October 2018

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Elyes HAOUAS (Code Review) 29 Oct '18

29 Oct '18

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/29312 to look at the new patch set (#11). Change subject: src: Add missing include <stdint.h> ...................................................................... src: Add missing include <stdint.h> Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/include/arch/pmp.h M src/cpu/intel/model_206ax/model_206ax.h M src/include/cpu/amd/multicore.h M src/include/pc80/keyboard.h M src/mainboard/google/rambi/variants/banjo/include/variant/variant.h M src/mainboard/google/rambi/variants/candy/include/variant/variant.h M src/mainboard/google/rambi/variants/clapper/include/variant/variant.h M src/mainboard/google/rambi/variants/enguarde/include/variant/variant.h M src/mainboard/google/rambi/variants/glimmer/include/variant/variant.h M src/mainboard/google/rambi/variants/gnawty/include/variant/variant.h M src/mainboard/google/rambi/variants/heli/include/variant/variant.h M src/mainboard/google/rambi/variants/kip/include/variant/variant.h M src/mainboard/google/rambi/variants/ninja/include/variant/variant.h M src/mainboard/google/rambi/variants/orco/include/variant/variant.h M src/mainboard/google/rambi/variants/quawks/include/variant/variant.h M src/mainboard/google/rambi/variants/rambi/include/variant/variant.h M src/mainboard/google/rambi/variants/squawks/include/variant/variant.h M src/mainboard/google/rambi/variants/sumo/include/variant/variant.h M src/mainboard/google/rambi/variants/swanky/include/variant/variant.h M src/mainboard/google/rambi/variants/winky/include/variant/variant.h M src/mainboard/google/smaug/pmic.h M src/mainboard/intel/harcuvar/spd/spd.h M src/northbridge/amd/amdmct/mct/mct.h M src/northbridge/amd/lx/raminit.h M src/security/tpm/tss/common/tss_common.h M src/soc/intel/apollolake/include/soc/heci.h M src/soc/intel/baytrail/include/soc/iomap.h M src/soc/intel/braswell/include/soc/iomap.h M src/soc/intel/cannonlake/include/soc/lpc.h M src/soc/intel/common/block/include/intelblocks/smm.h M src/soc/intel/common/block/include/intelblocks/vmx.h M src/soc/intel/fsp_baytrail/include/soc/iomap.h M src/soc/intel/icelake/include/soc/lpc.h M src/soc/mediatek/mt8173/include/soc/da9212.h M src/soc/mediatek/mt8173/include/soc/mt6311.h M src/soc/qualcomm/ipq40xx/include/soc/ebi2.h M src/soc/rockchip/rk3399/include/soc/tsadc.h M src/southbridge/amd/sr5650/chip.h 38 files changed, 77 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/29312/11 -- To view, visit https://review.coreboot.org/29312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Gerrit-Change-Number: 29312 Gerrit-PatchSet: 11 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: security/memory: Add memory scrubber interface
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29325 Change subject: security/memory: Add memory scrubber interface ...................................................................... security/memory: Add memory scrubber interface * Add memory scrubbing for FSP 2.0 Cannonlake+ * Add unsafe memory scrambling for broadwell de * Add platform independent FOSS scrubber Change-Id: Ice492bedd5afa2d151cfba78edbbedd433d30273 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- A src/security/memory/Kconfig A src/security/memory/Makefile.inc A src/security/memory/scrubber.c 3 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/29325/1 diff --git a/src/security/memory/Kconfig b/src/security/memory/Kconfig new file mode 100644 index 0000000..6880fe5 --- /dev/null +++ b/src/security/memory/Kconfig @@ -0,0 +1,42 @@ +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Facebook Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +menu "Platform Memory" + +config MEMORY_SCRUB_DATA + bool "Enforce Memory Scrubbing" + default n + +if MEMORY_SCRUB_DATA + +config MEMORY_FSP_MEM_SW_WIPE + bool "Enable Software Memory Wiping" + default n + +config MEMORY_FSP_MEM_SCRAMBLE + bool "Enable Memory Scrambling" + default n + default y if SOC_INTEL_FSP_BROADWELL_DE + depends on SOC_INTEL_FSP_BROADWELL_DE + select FSP_MEMORY_SCRAMBLING + +config MEMORY_FSP_MEM_CLEAN + bool "Enable Memory Cleaning" + default y if SOC_INTEL_CANNONLAKE + depends on SOC_INTEL_CANNONLAKE + select USE_CANNONLAKE_CLEAN_MEMORY + +endif + +endmenu # Platform Memory diff --git a/src/security/memory/Makefile.inc b/src/security/memory/Makefile.inc new file mode 100644 index 0000000..b1385b0 --- /dev/null +++ b/src/security/memory/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_MEMORY_FSP_MEM_SW_WIPE) += scrubber.c +postcar-$(CONFIG_MEMORY_FSP_MEM_SW_WIPE) += scrubber.c diff --git a/src/security/memory/scrubber.c b/src/security/memory/scrubber.c new file mode 100644 index 0000000..7ce078e --- /dev/null +++ b/src/security/memory/scrubber.c @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Facebook Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <arch/x86/random.h> + +// TODO, page tables if X86 + get_random_number -- To view, visit https://review.coreboot.org/29325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ice492bedd5afa2d151cfba78edbbedd433d30273 Gerrit-Change-Number: 29325 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29324 Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... soc/intel/cannonlake: Add additional UPD * Add CleanMemory option Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/fsp_params.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/29324/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index abe029a..ddd5382 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -262,6 +262,11 @@ endchoice +config USE_CANNONLAKE_CLEAN_MEMORY + bool "Use Clean Memory" + help + Ask MRC to clear memory content. + config FSP_HEADER_PATH string default "src/vendorcode/intel/fsp/fsp2_0/cannonlake/" if !SOC_INTEL_COFFEELAKE diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 6167346..43eb153 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -205,6 +205,11 @@ params->Device4Enable = config->Device4Enable; params->SkipMpInit = !chip_get_fsp_mp_init(); + if (IS_ENABLED(CONFIG_USE_CANNONLAKE_CLEAN_MEMORY)) + params->CleanMemory = 1; + else + params->CleanMemory = 0; + /* VrConfig Settings for 5 domains * 0 = System Agent, 1 = IA Core, 2 = Ring, * 3 = GT unsliced, 4 = GT sliced */ -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: src: Add missing include <stdint.h>
by Nico Huber (Code Review) 29 Oct '18

29 Oct '18

Nico Huber has posted comments on this change. ( https://review.coreboot.org/29312 ) Change subject: src: Add missing include <stdint.h> ...................................................................... Patch Set 10: (4 comments) https://review.coreboot.org/#/c/29312/10/src/soc/intel/baytrail/include/soc… File src/soc/intel/baytrail/include/soc/iomap.h: https://review.coreboot.org/#/c/29312/10/src/soc/intel/baytrail/include/soc… PS10, Line 19: #include <stdint.h> needs __ACPI__ guard https://review.coreboot.org/#/c/29312/10/src/soc/intel/baytrail/include/soc… PS10, Line 82: #ifndef __ACPI__ This guards the C code below from being included in ASL. The #include needs the same guard. https://review.coreboot.org/#/c/29312/10/src/soc/intel/braswell/include/soc… File src/soc/intel/braswell/include/soc/iomap.h: https://review.coreboot.org/#/c/29312/10/src/soc/intel/braswell/include/soc… PS10, Line 20: #include <stdint.h> same here https://review.coreboot.org/#/c/29312/10/src/soc/intel/fsp_baytrail/include… File src/soc/intel/fsp_baytrail/include/soc/iomap.h: https://review.coreboot.org/#/c/29312/10/src/soc/intel/fsp_baytrail/include… PS10, Line 19: #include <stdint.h> and here -- To view, visit https://review.coreboot.org/29312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06 Gerrit-Change-Number: 29312 Gerrit-PatchSet: 10 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 12:17:15 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add additional UPDs
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has uploaded this change for review. ( https://review.coreboot.org/29323 Change subject: soc/intel/fsp_broadwell_de: Add additional UPDs ...................................................................... soc/intel/fsp_broadwell_de: Add additional UPDs * Add MemScrambling and MemEccSupport options. Change-Id: I2687a52d4fa6f88d1a5fb5e83cc02419d688f6b4 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- M src/soc/intel/fsp_broadwell_de/fsp/Kconfig M src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c 2 files changed, 27 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/29323/1 diff --git a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig index 32fe0b8..1beb264 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/fsp/Kconfig @@ -102,6 +102,17 @@ help Path to the file which contains the SPD data for Channel 1, DIMM 1. +config FSP_MEMORY_SCRAMBLING + bool "Enable Memory Scrambling" + default n + help + Enable data scrambling of memory during ram initialization. + See https://en.wikipedia.org/wiki/Memory_controller#Security + +config FSP_MEMORY_ECC_SUPPORT + bool "Enable ECC Memory support" + default y + config FSP_HYPERTHREADING bool "Enable Hyper-Threading" default y diff --git a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c index 800f686..7fe3f21 100644 --- a/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c @@ -91,6 +91,22 @@ UpdData->MemDownEnable ? "Enabled" : "Disabled"); /* + * Memory Scrambling + */ + if (IS_ENABLED(CONFIG_FSP_MEMORY_SCRAMBLING)) + UpdData->MemScrambling = 1; + else + UpdData->MemScrambling = 0; + + /* + * Memory ECC support + */ + if (IS_ENABLED(CONFIG_FSP_MEMORY_ECC_SUPPORT)) + UpdData->MemEccSupport = 1; + else + UpdData->MemEccSupport = 0; + + /* * Fast Boot */ if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) -- To view, visit https://review.coreboot.org/29323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2687a52d4fa6f88d1a5fb5e83cc02419d688f6b4 Gerrit-Change-Number: 29323 Gerrit-PatchSet: 1 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com>

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Change in coreboot[master]: crossgcc: LLVM: Build only useful targets
by Jonathan Neuschäfer (Code Review) 29 Oct '18

29 Oct '18

Jonathan Neuschäfer has uploaded this change for review. ( https://review.coreboot.org/29322 Change subject: crossgcc: LLVM: Build only useful targets ...................................................................... crossgcc: LLVM: Build only useful targets LLVM supports a lot of CPU targets. Build only those that we might need. Note that I didn't enable RISCV yet, because it's marked experimental in LLVM 6.0. I also didn't enable PowerPC, because coreboot's PowerPC support is very dysfunctional. This brings LLVM/clang's contribution to util/crossgcc/xgcc from 1.9 GiB down to 1.7 GiB. Change-Id: Ib92a90cd5b13ab84c9f15f1b18cff7a1f513e219 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- M util/crossgcc/buildgcc 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/29322/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index dea42ad..38ed24b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -864,6 +864,8 @@ build_LLVM() { + LLVM_TARGETS="AArch64;ARM;Mips;X86" + cd .. || exit 1 ln -sf "$PWD/$CFE_DIR" "$LLVM_DIR/tools/clang" ln -sf "$PWD/$CTE_DIR" "$LLVM_DIR/tools/clang/tools/extra" @@ -872,7 +874,8 @@ $CMAKE -G "Unix Makefiles" -DCMAKE_INSTALL_PREFIX="$DESTDIR$TARGETDIR" \ -DCLANG_VENDOR="coreboot toolchain v$CROSSGCC_VERSION $CROSSGCC_DATE - " \ - -DCMAKE_BUILD_TYPE=Release ../$LLVM_DIR || touch .failed + -DCMAKE_BUILD_TYPE=Release -DLLVM_TARGETS_TO_BUILD="$LLVM_TARGETS" \ + ../$LLVM_DIR || touch .failed # shellcheck disable=SC2086 $MAKE $JOBS || touch .failed $MAKE install || touch .failed -- To view, visit https://review.coreboot.org/29322 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib92a90cd5b13ab84c9f15f1b18cff7a1f513e219 Gerrit-Change-Number: 29322 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: mb/lenovo/t430: Set USB always on when calling SMI sleep
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29031 ) Change subject: mb/lenovo/t430: Set USB always on when calling SMI sleep ...................................................................... mb/lenovo/t430: Set USB always on when calling SMI sleep Looks like we must do it in the same way as in l520, t420, t420s, t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be handled differently. Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66 Signed-off-by: Peter Lemenkov <lemenkov(a)gmail.com> Reviewed-on: https://review.coreboot.org/29031 Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/lenovo/t430/smihandler.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/mainboard/lenovo/t430/smihandler.c b/src/mainboard/lenovo/t430/smihandler.c index 286f07a..910fc1a 100644 --- a/src/mainboard/lenovo/t430/smihandler.c +++ b/src/mainboard/lenovo/t430/smihandler.c @@ -72,9 +72,9 @@ void mainboard_smi_sleep(u8 slp_typ) { - if (slp_typ == 3) { - h8_usb_always_on(); + h8_usb_always_on(); + if (slp_typ == 3) { u8 ec_wake = ec_read(0x32); /* If EC wake events are enabled, enable wake on EC WAKE GPE. */ if (ec_wake & 0x14) { -- To view, visit https://review.coreboot.org/29031 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66 Gerrit-Change-Number: 29031 Gerrit-PatchSet: 3 Gerrit-Owner: Peter Lemenkov <lemenkov(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: Improve payload fit
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29319 ) Change subject: Documentation: Improve payload fit ...................................................................... Documentation: Improve payload fit * Convert '' to ` * Add example how to use mkimage Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/29319 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M Documentation/lib/payloads/fit.md 1 file changed, 16 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved Jonathan Neuschäfer: Looks good to me, approved diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index ac7b3e6..53be92e 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -25,7 +25,7 @@ The FIT parser needs architecure support. ### aarch64 -The source code can be found in ''src/arch/arm64/fit.c''. +The source code can be found in `src/arch/arm64/fit.c`. On aarch64 the kernel (a section named 'kernel') must be in **Image** format and it needs a devicetree (a section named 'fdt') to boot. @@ -83,7 +83,7 @@ ## Building FIT image -The FIT image has to be built by calling ''mkimage''. You can use +The FIT image has to be built by calling `mkimage`. You can use the following example configuration: ``` @@ -148,9 +148,20 @@ }; ``` -It includes a compressed initrd **initramfs.cpio.xz**, which will be -decompressed by the Linux kernel, a compressed kernel **Image.lzma**, which will -be decompressed by the FIT loader and an uncompressed devicetree blob. +Save it as ITS file `config.its` along with the other files defined here: +* target.dtb +* initramfs.cpio.xz +* Image.lzma + +Generate the `uImage` that will be included into the CBFS by calling + +```bash +mkimage -f config.its uImage +``` + +The generated file includes a compressed initrd **initramfs.cpio.xz**, which +will be decompressed by the Linux kernel, a compressed kernel **Image.lzma**, +which will be decompressed by the FIT loader and an uncompressed devicetree blob. [uImage.FIT]: https://raw.githubusercontent.com/u-boot/u-boot/master/doc/uImage.FIT/howto… [U-Boot]: https://www.denx.de/wiki/U-Boot -- To view, visit https://review.coreboot.org/29319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Gerrit-Change-Number: 29319 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: Documentation: Improve payload fit
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29319 ) Change subject: Documentation: Improve payload fit ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29319 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id83db3db51582cb0d6ded7f3152b5549fba1f2e7 Gerrit-Change-Number: 29319 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 11:21:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: Documentation/mainboard: Add emulation/spike-riscv.md
by Philipp Deppenwiese (Code Review) 29 Oct '18

29 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/28874 ) Change subject: Documentation/mainboard: Add emulation/spike-riscv.md ...................................................................... Documentation/mainboard: Add emulation/spike-riscv.md Move the usage instructions from their ad-hoc place in Kconfig.name to the Documentation directory, and expand them a bit. Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/28874 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-by: Philipp Hug <philipp(a)hug.cx> --- A Documentation/mainboard/emulation/spike-riscv.md M Documentation/mainboard/index.md M src/mainboard/emulation/spike-riscv/Kconfig.name 3 files changed, 29 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved Philipp Hug: Looks good to me, but someone else must approve diff --git a/Documentation/mainboard/emulation/spike-riscv.md b/Documentation/mainboard/emulation/spike-riscv.md new file mode 100644 index 0000000..55e87d9 --- /dev/null +++ b/Documentation/mainboard/emulation/spike-riscv.md @@ -0,0 +1,23 @@ +# Spike RISC-V emulator + +[Spike], also known as riscv-isa-sim, is a commonly used [RISC-V] emulator. + + +## Installation + +- Download `riscv-fesvr` and `riscv-isa-sim` from <https://github.com/riscv/> +- Apply the two patches in <https://github.com/riscv/riscv-isa-sim/pull/53>, + which are necessary in order to have a serial console +- Compile `riscv-fesvr` and then `riscv-isa-sim` + + +## Building coreboot and running it in Spike + +- Configure coreboot and run `make` as usual +- Run `util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf` to + convert coreboot to an ELF that Spike can load +- Run `spike -m1024 build/coreboot.elf` + + +[Spike]: https://github.com/riscv/riscv-isa-sim +[RISC-V]: https://riscv.org/ diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index c346a3b..c1e5262 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -10,6 +10,12 @@ - [CN81XX EVB SFF](cavium/cn8100_sff_evb.md) +## Emulation + +The boards in this section are not real mainboards, but emulators. + +- [Spike RISC-V emulator](emulation/spike-riscv.md) + ## Foxconn - [D41S](foxconn/d41s.md) diff --git a/src/mainboard/emulation/spike-riscv/Kconfig.name b/src/mainboard/emulation/spike-riscv/Kconfig.name index 3a82ab1..17549c6 100644 --- a/src/mainboard/emulation/spike-riscv/Kconfig.name +++ b/src/mainboard/emulation/spike-riscv/Kconfig.name @@ -1,7 +1,3 @@ config BOARD_EMULATION_SPIKE_RISCV bool "SPIKE riscv" help - To run coreboot in spike: - * run "make" as usual - * util/riscv/make-spike-elf.sh build/coreboot.{rom,elf} - * spike -m1024 build/coreboot.elf -- To view, visit https://review.coreboot.org/28874 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106 Gerrit-Change-Number: 28874 Gerrit-PatchSet: 4 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Ronald G. Minnich <rminnich(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018