coreboot-gerrit October 2018

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Change in coreboot[master]: soc/amd/stoneyridge: Get rid of domain_read_resources
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/29345 Change subject: soc/amd/stoneyridge: Get rid of domain_read_resources ...................................................................... soc/amd/stoneyridge: Get rid of domain_read_resources The function domain_read_resources() didn't have any code to actually reserve any resources - it was just creating an empty resource entry. I looked at fixing it to actually reserve the space, but the values in the registers at the point when this runs aren't the final values that we want to reserve anyway, they're temp values with a range much larger than we want to reserve. I next looked at moving the amd_initcpuio() function earlier so that we could get the correct values for the registers, but even that doesn't give us what we really want. Ultimately removing this whole function seems to be the right thing. BUG=None TEST=Verify that the only resource that changes is the empty resource: PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080 Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/soc/amd/stoneyridge/chip.c M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 1 insertion(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/29345/1 diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 33c1730..ef65887 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -114,7 +114,7 @@ }; struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, + .read_resources = pci_domain_read_resources, .set_resources = domain_set_resources, .enable_resources = domain_enable_resources, .scan_bus = pci_domain_scan_bus, diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index a2ae52c..cb81360 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -392,43 +392,6 @@ pci_write_config32(dev, HDA_DEV_CTRL_STATUS, value); } -void domain_read_resources(struct device *dev) -{ - unsigned int reg; - struct device *addr_map = dev_find_slot(0, ADDR_DEVFN); - - /* Find the already assigned resource pairs */ - for (reg = 0x80 ; reg <= 0xd8 ; reg += 0x08) { - u32 base, limit; - base = pci_read_config32(addr_map, reg); - limit = pci_read_config32(addr_map, reg + 4); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev = dev_find_slot(0, HT_DEVFN); - if (reg < 0xc0) /* mmio */ - nodeid = (limit & 0xf) + (base & 0x30); - else /* io */ - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - - reg_link = (limit >> 4) & 7; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, - IOINDEX(0x1000 + reg, - reg_link)); - if (res) - res->flags = 1; - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - void domain_enable_resources(struct device *dev) { /* Must be called after PCI enumeration and resource allocation */ -- To view, visit https://review.coreboot.org/29345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1 Gerrit-Change-Number: 29345 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: cbfs: Get rid of void pointer math
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29344 Change subject: cbfs: Get rid of void pointer math ...................................................................... cbfs: Get rid of void pointer math Pointer math with void pointers is illegal in many compilers, though it works with GCC because it assumes size of void to be 1. Change the pointers or add parenthesis to force a proper order that will not cause compile errors if compiled with a different compiler, and more importantly, don't have unsuspected side effects. BUG=b:118484178 TEST=none. Change-Id: I1bbdc9499d257c5051fd7a86ca8b5c68bbf2e81d Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M payloads/coreinfo/cbfs_module.c M util/cbfstool/cbfs_image.c 2 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/29344/1 diff --git a/payloads/coreinfo/cbfs_module.c b/payloads/coreinfo/cbfs_module.c index 275c84e..6f40081 100644 --- a/payloads/coreinfo/cbfs_module.c +++ b/payloads/coreinfo/cbfs_module.c @@ -69,7 +69,7 @@ return NULL; if (f->magic == LARCHIVE_MAGIC) return f; - f = (void *)f + ntohl(header->align); + f = (void *)(f + ntohl(header->align)); } } diff --git a/util/cbfstool/cbfs_image.c b/util/cbfstool/cbfs_image.c index 74572a9..7abedea 100644 --- a/util/cbfstool/cbfs_image.c +++ b/util/cbfstool/cbfs_image.c @@ -723,8 +723,8 @@ len = addr_next - addr - min_entry_size; /* keep space for master header pointer */ - if ((void *)entry + min_entry_size + len > buffer_get(&image->buffer) + - buffer_size(&image->buffer) - sizeof(int32_t)) { + if ((void *)(entry + min_entry_size + len) > buffer_get(&image->buffer) + + buffer_size(&image->buffer) - sizeof(int32_t)) { len -= sizeof(int32_t); } cbfs_create_empty_entry(entry, CBFS_COMPONENT_NULL, len, ""); -- To view, visit https://review.coreboot.org/29344 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1bbdc9499d257c5051fd7a86ca8b5c68bbf2e81d Gerrit-Change-Number: 29344 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Daniel Kurtz (Code Review) 30 Oct '18

30 Oct '18

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… File src/soc/amd/common/block/pi/agesawrapper.c: https://review.coreboot.org/#/c/29343/1/src/soc/amd/common/block/pi/agesawr… PS1, Line 328: if (!dev->enabled if (dev->enabled) ? -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 21:04:19 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: mb/google/kahlee: Disable IOMMU
by Daniel Kurtz (Code Review) 30 Oct '18

30 Oct '18

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/29342 ) Change subject: mb/google/kahlee: Disable IOMMU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Gerrit-Change-Number: 29342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 21:00:48 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: add Nanya memory option
by Furquan Shaikh (Code Review) 30 Oct '18

30 Oct '18

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/29341 ) Change subject: mb/google/poppy/variant/nocturne: add Nanya memory option ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29341 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b Gerrit-Change-Number: 29341 Gerrit-PatchSet: 2 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 20:42:56 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: simplify timer interrupt handling
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Philipp Hug has posted comments on this change. ( https://review.coreboot.org/29340 ) Change subject: riscv: simplify timer interrupt handling ...................................................................... Patch Set 4: > Patch Set 2: > > I think this patch would be clearer without the formatting changes. Would you mind to split them out? Oops, sorry for that. -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Comment-Date: Mon, 29 Oct 2018 20:34:50 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: riscv: simplify timer interrupt handling
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29340 to look at the new patch set (#4). Change subject: riscv: simplify timer interrupt handling ...................................................................... riscv: simplify timer interrupt handling Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M src/arch/riscv/trap_handler.c 1 file changed, 8 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/4 -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 4 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Raul Rangel (Code Review) 30 Oct '18

30 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 20:31:05 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: riscv: simplify timer interrupt handling
by Philipp Hug (Code Review) 30 Oct '18

30 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29340 to look at the new patch set (#3). Change subject: riscv: simplify timer interrupt handling ...................................................................... riscv: simplify timer interrupt handling Just disable the timer interrupt and notify supervisor. To receive another timer interrupt just set timecmp and enable machine mode timer interrupt again. TEST=Run linux on sifive unleashed Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Signed-off-by: Philipp Hug <philipp(a)hug.cx> --- M 3rdparty/blobs M src/arch/riscv/trap_handler.c 2 files changed, 9 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/29340/3 -- To view, visit https://review.coreboot.org/29340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I5d693f872bd492c9d0017b514882a4cebd5ccadd Gerrit-Change-Number: 29340 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>

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Change in coreboot[master]: mb/google/kahlee: Disable IOMMU
by Raul Rangel (Code Review) 30 Oct '18

30 Oct '18

Raul Rangel has posted comments on this change. ( https://review.coreboot.org/29342 ) Change subject: mb/google/kahlee: Disable IOMMU ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Gerrit-Change-Number: 29342 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 29 Oct 2018 20:30:07 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit October 2018