coreboot-gerrit October 2018

coreboot-gerrit@coreboot.org

1 participants
1285 discussions

Change in coreboot[master]: util/board_status: Add missing space
by Jonathan Neuschäfer (Code Review) 30 Oct '18

30 Oct '18

Jonathan Neuschäfer has posted comments on this change. ( https://review.coreboot.org/29348 ) Change subject: util/board_status: Add missing space ...................................................................... Patch Set 1: > It displays properly for me without the space. Oh, you're right. These are two arguments to `echo`, and `echo` prints spaces between all the arguments. (This is not C) -- To view, visit https://review.coreboot.org/29348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3542069a7ae21f5463e97d37f599b1bf0f6ca78 Gerrit-Change-Number: 29348 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:52:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: util/board_status: Add missing space
by Angel Pons (Code Review) 30 Oct '18

30 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29348 ) Change subject: util/board_status: Add missing space ...................................................................... Patch Set 1: Code-Review-1 It displays properly for me without the space. -- To view, visit https://review.coreboot.org/29348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie3542069a7ae21f5463e97d37f599b1bf0f6ca78 Gerrit-Change-Number: 29348 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:50:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: siemens/mc_apl3: Add new mainboard variant mc_apl3
by Werner Zeh (Code Review) 30 Oct '18

30 Oct '18

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/29353 ) Change subject: siemens/mc_apl3: Add new mainboard variant mc_apl3 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Gerrit-Change-Number: 29353 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:49:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: nb/intel/x4x/raminit: Add missing space
by Angel Pons (Code Review) 30 Oct '18

30 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29346 ) Change subject: nb/intel/x4x/raminit: Add missing space ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/29346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I42033d2f184e424818edf844cf6cf84ea07d7ed5 Gerrit-Change-Number: 29346 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:47:23 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: mb/asus/p5qc: Fix spelling of Marvell
by Angel Pons (Code Review) 30 Oct '18

30 Oct '18

Angel Pons has posted comments on this change. ( https://review.coreboot.org/29347 ) Change subject: mb/asus/p5qc: Fix spelling of Marvell ...................................................................... Patch Set 1: Does it need to be in uppercase? I'd rather use "Marvell", since it is not an acronym. -- To view, visit https://review.coreboot.org/29347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb Gerrit-Change-Number: 29347 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Oct 2018 09:46:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Interface for updating Tcc in mainboard
by Kane Chen (Code Review) 30 Oct '18

30 Oct '18

Kane Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/29354 ) Change subject: soc/intel/apollolake: Interface for updating Tcc in mainboard ...................................................................... soc/intel/apollolake: Interface for updating Tcc in mainboard This change provides an interface for mainboard to set Tcc before BIOS reset complete happens in romstage. With this change, we can add code to update Tcc in mainboard or variants. BUG=b:117789732 Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/apollolake/include/soc/romstage.h M src/soc/intel/apollolake/romstage.c 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29354/2 -- To view, visit https://review.coreboot.org/29354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db Gerrit-Change-Number: 29354 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/apollolake: Interface for updating Tcc in mainboard
by Kane Chen (Code Review) 30 Oct '18

30 Oct '18

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/29354 Change subject: soc/intel/apollolake: Interface for updating Tcc in mainboard ...................................................................... soc/intel/apollolake: Interface for updating Tcc in mainboard This change provides an interface for mainboard to set Tcc before BIOS reset complete happens in romstage. With this change, we can add code to update Tcc in mainboard or variants. BUG=b:117789732 Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/apollolake/include/soc/romstage.h M src/soc/intel/apollolake/romstage.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/29354/1 diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index fe3add6..4a97826 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -24,5 +24,6 @@ void set_max_freq(void); void mainboard_memory_init_params(FSPM_UPD *mupd); void mainboard_save_dimm_info(void); +void mainboard_update_tcc(void); #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index d2ec6c1..6980032 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -52,6 +52,7 @@ #include <timer.h> #include <delay.h> #include "chip.h" +#include <baseboard/variants.h> static const uint8_t hob_variable_guid[16] = { 0x7d, 0x14, 0x34, 0xa0, 0x0c, 0x69, 0x54, 0x41, @@ -198,6 +199,9 @@ s3wake = pmc_fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + /* Set Tcc before BIOS Reset Complete */ + mainboard_update_tcc(); + if (punit_init()) set_max_freq(); else @@ -397,3 +401,8 @@ { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } + +void __weak mainboard_update_tcc(void) +{ + /* Place holder for updating Tcc. */ +} -- To view, visit https://review.coreboot.org/29354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I287ba2b0001f0bef0b7a0d85b33f7d2df127f2db Gerrit-Change-Number: 29354 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

1 0

Change in coreboot[master]: siemens/mc_apl3: Add new mainboard variant mc_apl3
by Mario Scheithauer (Code Review) 30 Oct '18

30 Oct '18

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29353 Change subject: siemens/mc_apl3: Add new mainboard variant mc_apl3 ...................................................................... siemens/mc_apl3: Add new mainboard variant mc_apl3 This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl3 mainboard will follow in separate commits. Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 6 files changed, 240 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/29353/1 diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 783207c..ee86a4d 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -18,11 +18,13 @@ string default "mc_apl1" if BOARD_SIEMENS_MC_APL1 default "mc_apl2" if BOARD_SIEMENS_MC_APL2 + default "mc_apl3" if BOARD_SIEMENS_MC_APL3 config MAINBOARD_PART_NUMBER string default "MC APL1" if BOARD_SIEMENS_MC_APL1 default "MC APL2" if BOARD_SIEMENS_MC_APL2 + default "MC APL3" if BOARD_SIEMENS_MC_APL3 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 7f5f263..e1c2aa1 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SIEMENS_MC_APL2 bool "-> MC APL2" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL3 + bool "-> MC APL3" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig new file mode 100644 index 0000000..3c5a9fa --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -0,0 +1,16 @@ + +if BOARD_SIEMENS_MC_APL3 + +config BOARD_SIEMENS_MC_APL3_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +config DEVICETREE + string + default "variants/mc_apl3/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb new file mode 100644 index 0000000..f3e8a77 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Proximity Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD + }, + }" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c new file mode 100644 index 0000000..ccf3ab8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <gpio.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + struct device *dev = NULL; + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x4a sets the swing level to 0.58 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); -- To view, visit https://review.coreboot.org/29353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Gerrit-Change-Number: 29353 Gerrit-PatchSet: 1 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

Change in coreboot[master]: mb/google/poppy/variants/nami: Enable radium touchscreen support
by Ren Kuo (Code Review) 30 Oct '18

30 Oct '18

Ren Kuo has posted comments on this change. ( https://review.coreboot.org/29239 ) Change subject: mb/google/poppy/variants/nami: Enable radium touchscreen support ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/29239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I51a0068ed68063435b5bf20eebce4ee5114bf42f Gerrit-Change-Number: 29239 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 06:44:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: amd: [test] Fix IORR0 MTRR
by Elyes HAOUAS (Code Review) 30 Oct '18

30 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29352 Change subject: amd: [test] Fix IORR0 MTRR ...................................................................... amd: [test] Fix IORR0 MTRR Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/agesa/family12/fixme.c M src/cpu/amd/agesa/family14/fixme.c M src/cpu/amd/agesa/family15tn/fixme.c M src/cpu/amd/agesa/family16kb/fixme.c M src/cpu/amd/mtrr/amd_mtrr.c M src/cpu/amd/pi/00630F01/fixme.c M src/cpu/amd/pi/00660F01/fixme.c M src/cpu/amd/pi/00730F01/fixme.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/agesa/family15tn/northbridge.c M src/northbridge/amd/agesa/family16kb/northbridge.c M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c M src/northbridge/amd/pi/00630F01/northbridge.c M src/northbridge/amd/pi/00660F01/northbridge.c M src/northbridge/amd/pi/00730F01/northbridge.c 16 files changed, 7 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/1 diff --git a/src/cpu/amd/agesa/family12/fixme.c b/src/cpu/amd/agesa/family12/fixme.c index 9df43e5..faaff23 100644 --- a/src/cpu/amd/agesa/family12/fixme.c +++ b/src/cpu/amd/agesa/family12/fixme.c @@ -17,7 +17,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family14/fixme.c b/src/cpu/amd/agesa/family14/fixme.c index a49cefb..4957b07 100644 --- a/src/cpu/amd/agesa/family14/fixme.c +++ b/src/cpu/amd/agesa/family14/fixme.c @@ -17,7 +17,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <AGESA.h> #include "amdlib.h" /* Define AMD Ontario APPU SSID/SVID */ diff --git a/src/cpu/amd/agesa/family15tn/fixme.c b/src/cpu/amd/agesa/family15tn/fixme.c index a0ae193..0a02389 100644 --- a/src/cpu/amd/agesa/family15tn/fixme.c +++ b/src/cpu/amd/agesa/family15tn/fixme.c @@ -17,7 +17,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/agesa/family16kb/fixme.c b/src/cpu/amd/agesa/family16kb/fixme.c index 2d74c7b..d27355d 100644 --- a/src/cpu/amd/agesa/family16kb/fixme.c +++ b/src/cpu/amd/agesa/family16kb/fixme.c @@ -17,7 +17,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> -#include <AGESA.h> #include "amdlib.h" void amd_initcpuio(void) diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 8cb6658..3c581f0 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -138,7 +138,7 @@ * undefined side effects. */ msr.lo = msr.hi = 0; - for (i = IORR_FIRST; i <= IORR_LAST; i++) + for (i = IORR0_BASE; i <= IORR1_MASK; i++) wrmsr(i, msr); /* Enable Variable Mtrrs diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index ae2a2df..5b3e0c8 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -18,7 +18,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> -#include <AGESA.h> #include <amdlib.h> void amd_initcpuio(void) diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index e028b6f..95bee23 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -18,7 +18,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> -#include <AGESA.h> #include <amdlib.h> void amd_initcpuio(void) diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index 163066b..f415b36 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -18,7 +18,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesa_helper.h> #include <Porting.h> -#include <AGESA.h> #include <amdlib.h> void amd_initcpuio(void) diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 46d66f8..d139eca 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -1,20 +1,10 @@ #ifndef CPU_AMD_MTRR_H #define CPU_AMD_MTRR_H -/* FIXME - * Replace - * #define IORR_FIRST 0xC0010016 - * #define IORR_LAST 0xC0010019 - * with - * #define IORR0_BASE 0xC0010016 - * #define IORR0_MASK 0xC0010017 - * #define IORR1_BASE 0xC0010018 - * #define IORR1_MASK 0xC0010019 - * those are also defined in vendorcode <AGESA.h> file. - */ - -#define IORR_FIRST 0xC0010016 -#define IORR_LAST 0xC0010019 +#define IORR0_BASE 0xC0010016 +#define IORR0_MASK 0xC0010017 +#define IORR1_BASE 0xC0010018 +#define IORR1_MASK 0xC0010019 #define MTRR_READ_MEM (1 << 4) #define MTRR_WRITE_MEM (1 << 3) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 7248eb7..fb2ca61 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -28,7 +28,6 @@ #include <lib.h> #include <cpu/cpu.h> #include <cbmem.h> -#include <AGESA.h> #include <cpu/x86/lapic.h> #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index a42ee5c..0e7601a 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -31,7 +31,6 @@ #include <cpu/amd/msr.h> #include <cpu/amd/mtrr.h> #include <Porting.h> -#include <AGESA.h> #include <Options.h> #include <Topology.h> #include <northbridge/amd/agesa/state_machine.h> diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c index 5aadccc..8461484 100644 --- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c @@ -816,7 +816,7 @@ u32 lo, hi; hi = TestAddr >> 24; lo = TestAddr << 8; - _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ + _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */ hi = 0xFF; lo = 0xFC000800; /* 64MB Mask */ _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 8b6a8d4..7ca310d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -2148,7 +2148,7 @@ u32 lo, hi; hi = TestAddr >> 24; lo = TestAddr << 8; - _WRMSR(IORR_FIRST, lo, hi); /* IORR0 Base */ + _WRMSR(IORR0_BASE, lo, hi); /* IORR0 Base */ hi = 0xFF; lo = 0xFC000800; /* 64MB Mask */ _WRMSR(0xC0010017, lo, hi); /* IORR0 Mask */ diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index f6cb285..691e17f 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <Porting.h> -#include <AGESA.h> #include <FieldAccessors.h> #include <Topology.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index fb3610d..05ce428 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -27,7 +27,6 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <Porting.h> -#include <AGESA.h> #include <FieldAccessors.h> #include <Topology.h> #include <cpu/x86/lapic.h> diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 7125e1e..8044c8c 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -29,7 +29,6 @@ #include <cpu/cpu.h> #include <cbmem.h> #include <Porting.h> -#include <AGESA.h> #include <FieldAccessors.h> #include <Topology.h> #include <cpu/x86/lapic.h> -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2018