coreboot-gerrit October 2018

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Change in coreboot[master]: intel/basecode/fw_update: Add ELOG events to ucode update
by Rizwan Qureshi (Code Review) 30 Oct '18

30 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29357 to look at the new patch set (#3). Change subject: intel/basecode/fw_update: Add ELOG events to ucode update ...................................................................... intel/basecode/fw_update: Add ELOG events to ucode update Add ELOG entries for ucode update module. TEST=verified that the eventlog shows event 0xb2 1 | 2018-10-30 06:06:52 | System boot | 161 2 | 2018-10-30 06:06:52 | Unknown | 0xb2 3 | 2018-10-30 06:07:09 | System boot | 162 Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/elog.h M src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/elog.c A src/soc/intel/common/basecode/fw_update/elog.h M src/soc/intel/common/basecode/fw_update/ucode_update.c 5 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29357/3 -- To view, visit https://review.coreboot.org/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 3 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/basecode/fw_update: Add ELOG events to ucode update
by Rizwan Qureshi (Code Review) 30 Oct '18

30 Oct '18

Rizwan Qureshi has uploaded a new patch set (#2). ( https://review.coreboot.org/29357 ) Change subject: intel/basecode/fw_update: Add ELOG events to ucode update ...................................................................... intel/basecode/fw_update: Add ELOG events to ucode update Add ELOG entries for ucode update module. TEST=verified that the eventlog shows event 0xb2 1 | 2018-10-30 06:06:52 | System boot | 161 2 | 2018-10-30 06:06:52 | Unknown | 0xb2 3 | 2018-10-30 06:07:09 | System boot | 162 Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/elog.h M src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/elog.c A src/soc/intel/common/basecode/fw_update/elog.h M src/soc/intel/common/basecode/fw_update/ucode_update.c 5 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29357/2 -- To view, visit https://review.coreboot.org/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 2 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/basecode/fw_upadte: Add ELOG events to ucode update
by build bot (Jenkins) (Code Review) 30 Oct '18

30 Oct '18

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/29357 ) Change subject: intel/basecode/fw_upadte: Add ELOG events to ucode update ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29357/1/src/soc/intel/common/basecode/fw_up… File src/soc/intel/common/basecode/fw_update/elog.c: https://review.coreboot.org/#/c/29357/1/src/soc/intel/common/basecode/fw_up… PS1, Line 30: return (elog_add_event_raw(event_type, &event, sizeof(event))); return is not a function, parentheses are not required -- To view, visit https://review.coreboot.org/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 13:37:03 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: intel/basecode/fw_upadte: Add ELOG events to ucode update
by Rizwan Qureshi (Code Review) 30 Oct '18

30 Oct '18

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/29357 Change subject: intel/basecode/fw_upadte: Add ELOG events to ucode update ...................................................................... intel/basecode/fw_upadte: Add ELOG events to ucode update Add ELOG entries for ucode update module. TEST=verified that the eventlog shows event 0xb2 1 | 2018-10-30 06:06:52 | System boot | 161 2 | 2018-10-30 06:06:52 | Unknown | 0xb2 3 | 2018-10-30 06:07:09 | System boot | 162 Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/elog.h M src/soc/intel/common/basecode/fw_update/Makefile.inc A src/soc/intel/common/basecode/fw_update/elog.c A src/soc/intel/common/basecode/fw_update/elog.h M src/soc/intel/common/basecode/fw_update/ucode_update.c 5 files changed, 76 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/29357/1 diff --git a/src/include/elog.h b/src/include/elog.h index 8aecf2c..49e2dd4 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -152,6 +152,7 @@ #define ELOG_WAKE_SOURCE_PME_XHCI_USB_2 0x1d #define ELOG_WAKE_SOURCE_PME_XHCI_USB_3 0x1e #define ELOG_WAKE_SOURCE_PME_WIFI 0x1f +#define ELOG_UCODE_UPDATE 0x20 struct elog_event_data_wake { u8 source; @@ -231,6 +232,17 @@ u32 event_complement; } __packed; +/* Microcode Update events */ +#define ELOG_TYPE_INTEL_UCODE_UPDATE 0xb2 +#define ELOG_INTEL_UCODE_UPDATE_FAIL -1 +#define ELOG_INTEL_UCODE_UPDATE_PASS 0 +struct elog_event_intel_ucode { + u32 uc_current; + u32 uc_slot; + u32 uc_staging; + int status; +} __packed; + #if IS_ENABLED(CONFIG_ELOG) /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); diff --git a/src/soc/intel/common/basecode/fw_update/Makefile.inc b/src/soc/intel/common/basecode/fw_update/Makefile.inc index f58961b..5631e00 100644 --- a/src/soc/intel/common/basecode/fw_update/Makefile.inc +++ b/src/soc/intel/common/basecode/fw_update/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_TOP_SWAP_BASED_VBOOT_UCODE_UPDATE) += ucode_update.c +ramstage-$(CONFIG_TOP_SWAP_BASED_VBOOT_UCODE_UPDATE) += elog.c diff --git a/src/soc/intel/common/basecode/fw_update/elog.c b/src/soc/intel/common/basecode/fw_update/elog.c new file mode 100644 index 0000000..8daf674 --- /dev/null +++ b/src/soc/intel/common/basecode/fw_update/elog.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <elog.h> +#include "elog.h" + +int ucode_elog_event(u32 current, u32 slot, u32 staging, int status) +{ + const int event_type = ELOG_TYPE_INTEL_UCODE_UPDATE; + struct elog_event_intel_ucode event = { + .uc_current = current, + .uc_slot = slot, + .uc_staging = staging, + .status = status, + }; + + return (elog_add_event_raw(event_type, &event, sizeof(event))); +} + diff --git a/src/soc/intel/common/basecode/fw_update/elog.h b/src/soc/intel/common/basecode/fw_update/elog.h new file mode 100644 index 0000000..d56c779 --- /dev/null +++ b/src/soc/intel/common/basecode/fw_update/elog.h @@ -0,0 +1,22 @@ + +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +/* + * Add microcode update ELOG event + * return 0 on success, -1 on failure. + */ +int ucode_elog_event(u32 current, u32 slot, u32 staging, int status); diff --git a/src/soc/intel/common/basecode/fw_update/ucode_update.c b/src/soc/intel/common/basecode/fw_update/ucode_update.c index 4a7c194..eeb6aec 100644 --- a/src/soc/intel/common/basecode/fw_update/ucode_update.c +++ b/src/soc/intel/common/basecode/fw_update/ucode_update.c @@ -19,6 +19,7 @@ #include <commonlib/region.h> #include <console/console.h> #include <cpu/intel/microcode.h> +#include <elog.h> #include <fmap.h> #include <halt.h> #include <intelbasecode/ucode_update.h> @@ -29,6 +30,7 @@ #include <stdlib.h> #include <stdint.h> #include <types.h> +#include "elog.h" #define locate_staging_rw(rdev) \ fmap_locate_area_as_rdev_rw(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG, \ @@ -188,7 +190,10 @@ } printk(BIOS_INFO, "Microcode staging area updated, restart!\n"); - /* TODO: Add ELOG entry */ + + if (ucode_elog_event(current_ucode, slot_rev, staging_rev, + ELOG_INTEL_UCODE_UPDATE_PASS) < 0) + printk(BIOS_ERR, "Failed to log microcode update event.\n"); /* Finished writing, disable safety and reset */ configure_rtc_buc_top_swap(TS_ENABLE); @@ -205,6 +210,8 @@ update_failed: - /* TODO: Write Elog */ + if (ucode_elog_event(0, 0, 0, ELOG_INTEL_UCODE_UPDATE_FAIL) < 0) + printk(BIOS_ERR, "Failed to log microcode update event.\n"); + return CB_ERR; } -- To view, visit https://review.coreboot.org/29357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idda32a1073b3dc8e3f57e079b69fc415a2837899 Gerrit-Change-Number: 29357 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29324 ) Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... Patch Set 5: @intel guys do you have some info about the performance and internals what it does? Just changing the seed of the scrambler or overwriting the whole memory. If so where does the random come from? -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 12:24:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

1 0

Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29324 ) Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... Patch Set 5: Code-Review+2 (1 comment) https://review.coreboot.org/#/c/29324/5/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/29324/5/src/soc/intel/cannonlake/Kconfig@269 PS5, Line 269: Ask MRC to clear memory content. > Which memory ? DRAM ? […] @intel -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 12:22:43 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/29324 ) Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... Patch Set 3: (3 comments) https://review.coreboot.org/#/c/29324/3/src/soc/intel/cannonlake/Kconfig File src/soc/intel/cannonlake/Kconfig: https://review.coreboot.org/#/c/29324/3/src/soc/intel/cannonlake/Kconfig@266 PS3, Line 266: bool "Use Clean Memory" > Let FSP clean memory Done https://review.coreboot.org/#/c/29324/3/src/soc/intel/cannonlake/Kconfig@268 PS3, Line 268: Ask MRC to clear memory content. > Elaborate a little? Is clean and clear the same? This is the description of the Intel documentation. IDK https://review.coreboot.org/#/c/29324/3/src/soc/intel/cannonlake/romstage/f… File src/soc/intel/cannonlake/romstage/fsp_params.c: https://review.coreboot.org/#/c/29324/3/src/soc/intel/cannonlake/romstage/f… PS3, Line 59: if (IS_ENABLED(CONFIG_USE_CANNONLAKE_CLEAN_MEMORY)) : m_cfg->CleanMemory = 1; : else : m_cfg->CleanMemory = 0; > Use ternary operator? […] Nope. Harder to read and not better code -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 3 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 12:20:49 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: siemens/mc_apl3: Add new mainboard variant mc_apl3
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/29353 ) Change subject: siemens/mc_apl3: Add new mainboard variant mc_apl3 ...................................................................... siemens/mc_apl3: Add new mainboard variant mc_apl3 This mainboard is based on mc_apl1. In a first step, it concerns a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl3 mainboard will follow in separate commits. Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com> Reviewed-on: https://review.coreboot.org/29353 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_apl1/Kconfig M src/mainboard/siemens/mc_apl1/Kconfig.name A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig A src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc A src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb A src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c 6 files changed, 240 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Werner Zeh: Looks good to me, approved diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig index 783207c..ee86a4d 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig +++ b/src/mainboard/siemens/mc_apl1/Kconfig @@ -18,11 +18,13 @@ string default "mc_apl1" if BOARD_SIEMENS_MC_APL1 default "mc_apl2" if BOARD_SIEMENS_MC_APL2 + default "mc_apl3" if BOARD_SIEMENS_MC_APL3 config MAINBOARD_PART_NUMBER string default "MC APL1" if BOARD_SIEMENS_MC_APL1 default "MC APL2" if BOARD_SIEMENS_MC_APL2 + default "MC APL3" if BOARD_SIEMENS_MC_APL3 config MAX_CPUS int diff --git a/src/mainboard/siemens/mc_apl1/Kconfig.name b/src/mainboard/siemens/mc_apl1/Kconfig.name index 7f5f263..e1c2aa1 100644 --- a/src/mainboard/siemens/mc_apl1/Kconfig.name +++ b/src/mainboard/siemens/mc_apl1/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_SIEMENS_MC_APL2 bool "-> MC APL2" select BOARD_SIEMENS_BASEBOARD_MC_APL1 + +config BOARD_SIEMENS_MC_APL3 + bool "-> MC APL3" + select BOARD_SIEMENS_BASEBOARD_MC_APL1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig new file mode 100644 index 0000000..3c5a9fa --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Kconfig @@ -0,0 +1,16 @@ + +if BOARD_SIEMENS_MC_APL3 + +config BOARD_SIEMENS_MC_APL3_VAR + def_bool y + select DRIVER_INTEL_I210 + select DRIVERS_I2C_RX6110SA + select DRIVER_SIEMENS_NC_FPGA + select NC_FPGA_NOTIFY_CB_READY + select APL_SKIP_SET_POWER_LIMITS + +config DEVICETREE + string + default "variants/mc_apl3/devicetree.cb" + +endif # BOARD_SIEMENS_MC_APL3 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc new file mode 100644 index 0000000..f3c87b2 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += mainboard.c diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb new file mode 100644 index 0000000..f3e8a77 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -0,0 +1,119 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "sci_irq" = "SCIS_IRQ10" + + # Disable unused clkreq of PCIe root ports + register "pcie_rp_clkreq_pin[0]" = "3" # PCIe-PCI-Bridge + register "pcie_rp_clkreq_pin[1]" = "2" # FPGA + register "pcie_rp_clkreq_pin[2]" = "0" # MACPHY + register "pcie_rp_clkreq_pin[3]" = "1" # MACPHY + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # 0:HS400(Default), 1:HS200, 2:DDR50 + register "emmc_host_max_speed" = "2" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C0 | Proximity Sensor | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_STANDARD + }, + }" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen - Display + device pci 03.0 off end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 off end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 off end # - Shared SRAM + device pci 0e.0 off end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - RP 2 - PCIe A 0 - MACPHY + device pci 13.1 on end # - RP 3 - PCIe A 1 - MACPHY + device pci 13.2 off end # - RP 4 - PCIe-A 2 + device pci 13.3 off end # - RP 5 - PCIe-A 3 + device pci 14.0 on end # - RP 0 - PCIe-B 0 - PCIe-PCI-Bridge + device pci 14.1 on end # - RP 1 - PCIe-B 1 - FPGA + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + # Enable external RTC chip + chip drivers/i2c/rx6110sa + register "pmon_sampling" = "PMON_SAMPL_256_MS" + register "bks_on" = "0" + register "bks_off" = "1" + register "iocut_en" = "1" + register "set_user_date" = "1" + register "user_year" = "04" + register "user_month" = "07" + register "user_day" = "01" + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA + end + end + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1d.0 off end # - UFS + device pci 1e.0 off end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c new file mode 100644 index 0000000..ccf3ab8 --- /dev/null +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2018 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <gpio.h> +#include <hwilib.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <soc/pcr_ids.h> +#include <timer.h> +#include <timestamp.h> +#include <baseboard/variants.h> + +#define TX_DWORD3 0xa8c + +void variant_mainboard_final(void) +{ + struct device *dev = NULL; + + /* + * PIR6 register mapping for PCIe root ports + * INTA#->PIRQB#, INTB#->PIRQC#, INTC#->PIRQD#, INTD#-> PIRQA# + */ + pcr_write16(PID_ITSS, 0x314c, 0x0321); + + /* Disable clock outputs 1-5 (CLKOUT) for XIO2001 PCIe to PCI Bridge. */ + dev = dev_find_device(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2001, 0); + if (dev) + pci_write_config8(dev, 0xd8, 0x3e); + + /* Enable CLKRUN_EN for power gating LPC */ + lpc_enable_pci_clk_cntl(); + + /* + * Enable LPC PCE (Power Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341D bit3 and bit0. + * Enable LPC CCE (Clock Control Enable) by setting IOSF-SB port 0xD2 + * offset 0x341C bit [3:0]. + */ + pcr_or32(PID_LPC, PCR_LPC_PRC, (PCR_LPC_CCE_EN | PCR_LPC_PCE_EN)); + + /* + * Correct the SATA transmit signal via the High Speed I/O Transmit + * Control Register 3. + * Bit [23:16] set the output voltage swing for TX line. + * The value 0x4a sets the swing level to 0.58 V. + */ + pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); +} + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +static void finalize_boot(void *unused) +{ + /* Set coreboot ready LED. */ + gpio_output(CNV_RGI_DT, 1); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); -- To view, visit https://review.coreboot.org/29353 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791 Gerrit-Change-Number: 29353 Gerrit-PatchSet: 2 Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: drivers/spi: Winbond specific write-protection enable
by Philipp Deppenwiese (Code Review) 30 Oct '18

30 Oct '18

Philipp Deppenwiese has submitted this change and it was merged. ( https://review.coreboot.org/25105 ) Change subject: drivers/spi: Winbond specific write-protection enable ...................................................................... drivers/spi: Winbond specific write-protection enable Extend the SPI interface to enable write-protection. Tested on Cavium EVB CN81xx using W25Q128. Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/25105 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> --- M src/drivers/spi/spi_flash.c M src/drivers/spi/winbond.c M src/include/spi_flash.h 3 files changed, 356 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Philipp Deppenwiese: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index c484088..cc21ccb 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -454,6 +454,55 @@ return flash->ops->get_write_protection(flash, region); } +int spi_flash_set_write_protected(const struct spi_flash *flash, + const struct region *region, + const bool non_volatile, + const enum spi_flash_status_reg_lockdown mode) +{ + struct region flash_region = { 0 }; + int ret; + + if (!flash) + return -1; + + flash_region.size = flash->size; + + if (!region_is_subregion(&flash_region, region)) + return -1; + + if (!flash->ops->set_write_protection) { + printk(BIOS_WARNING, "SPI: Setting write-protection is not " + "implemented for this vendor.\n"); + return 0; + } + + ret = flash->ops->set_write_protection(flash, region, non_volatile, + mode); + + if (ret == 0 && mode != SPI_WRITE_PROTECTION_PRESERVE) { + printk(BIOS_INFO, "SPI: SREG lock-down was set to "); + switch (mode) { + case SPI_WRITE_PROTECTION_NONE: + printk(BIOS_INFO, "NEVER\n"); + break; + case SPI_WRITE_PROTECTION_PIN: + printk(BIOS_INFO, "WP\n"); + break; + case SPI_WRITE_PROTECTION_REBOOT: + printk(BIOS_INFO, "REBOOT\n"); + break; + case SPI_WRITE_PROTECTION_PERMANENT: + printk(BIOS_INFO, "PERMANENT\n"); + break; + default: + printk(BIOS_INFO, "UNKNOWN\n"); + break; + } + } + + return ret; +} + static uint32_t volatile_group_count CAR_GLOBAL; int spi_flash_volatile_group_begin(const struct spi_flash *flash) diff --git a/src/drivers/spi/winbond.c b/src/drivers/spi/winbond.c index e2c6538..9eb3352 100644 --- a/src/drivers/spi/winbond.c +++ b/src/drivers/spi/winbond.c @@ -10,6 +10,8 @@ #include <spi-generic.h> #include <string.h> #include <assert.h> +#include <delay.h> +#include <lib.h> #include "spi_flash_internal.h" @@ -28,6 +30,10 @@ #define CMD_W25_CE 0xc7 /* Chip Erase */ #define CMD_W25_DP 0xb9 /* Deep Power-down */ #define CMD_W25_RES 0xab /* Release from DP, and Read Signature */ +#define CMD_VOLATILE_SREG_WREN 0x50 /* Write Enable for Volatile SREG */ + +/* tw: Maximum time to write a flash cell in milliseconds */ +#define WINBOND_FLASH_TIMEOUT 30 struct winbond_spi_flash_params { uint16_t id; @@ -75,6 +81,27 @@ }; }; +struct status_regs { + union { + struct { +#if defined(__BIG_ENDIAN) + union status_reg2 reg2; + union { + union status_reg1_bp3 reg1_bp3; + union status_reg1_bp4 reg1_bp4; + }; +#else + union { + union status_reg1_bp3 reg1_bp3; + union status_reg1_bp4 reg1_bp4; + }; + union status_reg2 reg2; +#endif + }; + u16 u; + }; +}; + static const struct winbond_spi_flash_params winbond_spi_flash_table[] = { { .id = 0x3015, @@ -351,6 +378,228 @@ return region_is_subregion(&wp_region, region); } +/** + * Common method to write some bit of the status register 1 & 2 at the same + * time. Only change bits that are one in @mask. + * Compare the final result to make sure that the register isn't locked. + * + * @param mask: The bits that are affected by @val + * @param val: The bits to write + * @param non_volatile: Make setting permanent + * + * @return 0 on success + */ +static int winbond_flash_cmd_status(const struct spi_flash *flash, + const u16 mask, + const u16 val, + const bool non_volatile) +{ + struct { + u8 cmd; + u16 sreg; + } __packed cmdbuf; + u8 reg8; + int ret; + + if (!flash) + return -1; + + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR, &reg8, sizeof(reg8)); + if (ret) + return ret; + + cmdbuf.sreg = reg8; + + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg8, sizeof(reg8)); + if (ret) + return ret; + + cmdbuf.sreg |= reg8 << 8; + + if ((val & mask) == (cmdbuf.sreg & mask)) + return 0; + + if (non_volatile) { + ret = spi_flash_cmd(&flash->spi, CMD_W25_WREN, NULL, 0); + } else { + ret = spi_flash_cmd(&flash->spi, CMD_VOLATILE_SREG_WREN, NULL, + 0); + } + if (ret) + return ret; + + cmdbuf.sreg &= ~mask; + cmdbuf.sreg |= val & mask; + cmdbuf.cmd = CMD_W25_WRSR; + + /* Legacy method of writing status register 1 & 2 */ + ret = spi_flash_cmd_write(&flash->spi, (u8 *)&cmdbuf, sizeof(cmdbuf), + NULL, 0); + if (ret) + return ret; + + if (non_volatile) { + /* Wait tw */ + ret = spi_flash_cmd_wait_ready(flash, WINBOND_FLASH_TIMEOUT); + if (ret) + return ret; + } else { + /* Wait tSHSL */ + udelay(1); + } + + /* Now read the status register to make sure it's not locked */ + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR, &reg8, sizeof(reg8)); + if (ret) + return ret; + + cmdbuf.sreg = reg8; + + ret = spi_flash_cmd(&flash->spi, CMD_W25_RDSR2, &reg8, sizeof(reg8)); + if (ret) + return ret; + + cmdbuf.sreg |= reg8 << 8; + + printk(BIOS_DEBUG, "WINBOND: SREG=%02x SREG2=%02x\n", + cmdbuf.sreg & 0xff, + cmdbuf.sreg >> 8); + + /* Compare against expected result */ + if ((val & mask) != (cmdbuf.sreg & mask)) { + printk(BIOS_ERR, "WINBOND: SREG is locked!\n"); + ret = -1; + } + + return ret; +} + +/* + * Available on all devices. + * Protect a region starting from start of flash or end of flash. + * The caller must provide a supported protected region size. + * SEC isn't supported and set to zero. + * Write block protect bits to Status/Status2 Reg. + * Optionally lock the status register if lock_sreg is set with the provided + * mode. + * + * @param flash: The flash to operate on + * @param region: The region to write protect + * @param non_volatile: Make setting permanent + * @param mode: Optional status register lock-down mode + * + * @return 0 on success + */ +static int +winbond_set_write_protection(const struct spi_flash *flash, + const struct region *region, + const bool non_volatile, + const enum spi_flash_status_reg_lockdown mode) +{ + const struct winbond_spi_flash_params *params; + struct status_regs mask, val; + struct region wp_region; + u8 cmp, bp, tb; + int ret; + + /* Need to touch TOP or BOTTOM */ + if (region_offset(region) != 0 && + (region_offset(region) + region_sz(region)) != flash->size) + return -1; + + params = (const struct winbond_spi_flash_params *)flash->driver_private; + if (!params) + return -1; + + if (params->bp_bits != 3 && params->bp_bits != 4) { + /* FIXME: not implemented */ + return -1; + } + + wp_region = *region; + + if (region_offset(&wp_region) == 0) + tb = 0; + else + tb = 1; + + if (region_sz(&wp_region) > flash->size / 2) { + cmp = 1; + wp_region.offset = tb ? 0 : region_sz(&wp_region); + wp_region.size = flash->size - region_sz(&wp_region); + tb = !tb; + } else { + cmp = 0; + } + + if (region_sz(&wp_region) == 0) { + bp = 0; + } else if (IS_POWER_OF_2(region_sz(&wp_region)) && + (region_sz(&wp_region) >= + (1 << params->protection_granularity_shift))) { + bp = log2(region_sz(&wp_region)) - + params->protection_granularity_shift + 1; + } else { + printk(BIOS_ERR, "WINBOND: ERROR: unsupported region size\n"); + return -1; + } + + /* Write block protection bits */ + + if (params->bp_bits == 3) { + val.reg1_bp3 = (union status_reg1_bp3) { .bp = bp, .tb = tb, + .sec = 0 }; + mask.reg1_bp3 = (union status_reg1_bp3) { .bp = ~0, .tb = 1, + .sec = 1 }; + } else { + val.reg1_bp4 = (union status_reg1_bp4) { .bp = bp, .tb = tb }; + mask.reg1_bp4 = (union status_reg1_bp4) { .bp = ~0, .tb = 1 }; + } + + val.reg2 = (union status_reg2) { .cmp = cmp }; + mask.reg2 = (union status_reg2) { .cmp = 1 }; + + if (mode != SPI_WRITE_PROTECTION_PRESERVE) { + u8 srp; + switch (mode) { + case SPI_WRITE_PROTECTION_NONE: + srp = 0; + break; + case SPI_WRITE_PROTECTION_PIN: + srp = 1; + break; + case SPI_WRITE_PROTECTION_REBOOT: + srp = 2; + break; + case SPI_WRITE_PROTECTION_PERMANENT: + srp = 3; + break; + default: + return -1; + } + + if (params->bp_bits == 3) { + val.reg1_bp3.srp0 = !!(srp & 1); + mask.reg1_bp3.srp0 = 1; + } else { + val.reg1_bp4.srp0 = !!(srp & 1); + mask.reg1_bp4.srp0 = 1; + } + + val.reg2.srp1 = !!(srp & 2); + mask.reg2.srp1 = 1; + } + + ret = winbond_flash_cmd_status(flash, mask.u, val.u, non_volatile); + if (ret) + return ret; + + printk(BIOS_DEBUG, "WINBOND: write-protection set to range " + "0x%08zx-0x%08zx\n", region_offset(region), + region_offset(region) + region_sz(region)); + + return ret; +} static const struct spi_flash_ops spi_flash_ops = { .write = winbond_write, @@ -362,6 +611,7 @@ .read = spi_flash_cmd_read_fast, #endif .get_write_protection = winbond_get_write_protection, + .set_write_protection = winbond_set_write_protection, }; int spi_flash_probe_winbond(const struct spi_slave *spi, u8 *idcode, diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 9f8d2d0..64ad7fe 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -27,6 +27,25 @@ struct spi_flash; /* + * SPI write protection is enforced by locking the status register. + * The following modes are known. It depends on the flash chip if the + * mode is actually supported. + * + * PRESERVE : Keep the previous status register lock-down setting (noop) + * NONE : Status register isn't locked + * PIN : Status register is locked as long as the ~WP pin is active + * REBOOT : Status register is locked until power failure + * PERMANENT: Status register is permanently locked + */ +enum spi_flash_status_reg_lockdown { + SPI_WRITE_PROTECTION_PRESERVE = -1, + SPI_WRITE_PROTECTION_NONE = 0, + SPI_WRITE_PROTECTION_PIN, + SPI_WRITE_PROTECTION_REBOOT, + SPI_WRITE_PROTECTION_PERMANENT +}; + +/* * Representation of SPI flash operations: * read: Flash read operation. * write: Flash write operation. @@ -45,10 +64,26 @@ * Hardware write protection mechanism aren't accounted. * If the write protection could be changed, due to unlocked status * register for example, 0 should be returned. - * Returns -1 on error. + * Returns 0 on success. */ int (*get_write_protection)(const struct spi_flash *flash, const struct region *region); + /* + * Enable the status register write protection, if supported on the + * requested region, and optionally enable status register lock-down. + * Returns 0 if the whole region was software write protected. + * Hardware write protection mechanism aren't accounted. + * If the status register is locked and the requested configuration + * doesn't match the selected one, return an error. + * Only a single region is supported ! + * + * @return 0 on success + */ + int + (*set_write_protection)(const struct spi_flash *flash, + const struct region *region, + const bool non_volatile, + const enum spi_flash_status_reg_lockdown mode); }; @@ -120,6 +155,27 @@ int spi_flash_is_write_protected(const struct spi_flash *flash, const struct region *region); /* + * Enable the vendor dependent SPI flash write protection. The region not + * covered by write-protection will be set to write-able state. + * Only a single write-protected region is supported. + * Some flash ICs require the region to be aligned in the block size, sector + * size or page size. + * Some flash ICs require the region to start at TOP or BOTTOM. + * + * @param flash : A SPI flash device + * @param region: A subregion of the device's region + * @param non_volatile: Write status register non-volatile + * @param mode: Optional lock-down of status register + + * @return 0 on success + */ +int +spi_flash_set_write_protected(const struct spi_flash *flash, + const struct region *region, + const bool non_volatile, + const enum spi_flash_status_reg_lockdown mode); + +/* * Some SPI controllers require exclusive access to SPI flash when volatile * operations like erase or write are being performed. In such cases, * volatile_group_begin will gain exclusive access to SPI flash if not already -- To view, visit https://review.coreboot.org/25105 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ie3765b013855538eca37bc7800d3f9d5d09b8402 Gerrit-Change-Number: 25105 Gerrit-PatchSet: 35 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph (1001864) Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org>

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coreboot-gerrit October 2018