coreboot-gerrit October 2018

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Change in coreboot[master]: soc/intel/apollolake: Improve cold boot and S3 resume
by John Zhao (Code Review) 30 Oct '18

30 Oct '18

John Zhao has uploaded this change for review. ( https://review.coreboot.org/29363 Change subject: soc/intel/apollolake: Improve cold boot and S3 resume ...................................................................... soc/intel/apollolake: Improve cold boot and S3 resume FSP 2.0.7.1 provides UPD interface to execute IPC command. Configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay from default 100ms to 10ms to improve cold boot and S3 resume performance. BUG=b:118676361 CQ-DEPEND=CL:*703187 TEST=Verified booting to kernel. Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Signed-off-by: John Zhao <john.zhao(a)intel.com> --- M src/soc/intel/apollolake/chip.c M src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h 2 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/29363/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 9ee6dbb..976c45a 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -567,6 +567,15 @@ * has set up. Hence skipping in FSP. */ silconfig->SkipSpiPCP = 1; + + /* + * FSP provides UPD interface to execute IPC command. In order to improve boot + * performance, configure PmicPmcIpcCtrl for PMC to program PMIC PCH_PWROK delay + * from 100ms (default) to 10ms. + * PWROKDELAY[2:0]: 000=2.5ms, 001=5.0ms, 010=10ms, 011=15ms, 100=20ms, + * 101=50ms, 110=75ms, 111=100ms (default) + */ + silconfig->PmicPmcIpcCtrl = 2; #endif } diff --git a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h index cc194b2..e8d02c7 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/glk/FspsUpd.h @@ -1715,9 +1715,15 @@ **/ UINT8 SkipSpiPCP; -/** Offset 0x03AB +/** Offset 0x03AB - PMIC PCH_WROK delay configuration - IPC Configuration + Upd for changing PCH_WROK delay configuration : I2C_Slave_Address (31:23) + Register_Offset + (23:16) + OR Value (15:8) + AND Value (7:0) **/ - UINT8 ReservedFspsUpd[5]; + UINT32 PmicPmcIpcCtrl; + +/** Offset 0x03AF +**/ + UINT8 ReservedFspsUpd[1]; } FSP_S_CONFIG; /** Fsp S SGX Configuration -- To view, visit https://review.coreboot.org/29363 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I05656c9083a855112120b7f1b0ec01c42f582409 Gerrit-Change-Number: 29363 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Enable ISH from device
by Bora Guvendik (Code Review) 30 Oct '18

30 Oct '18

Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/29274 ) Change subject: soc/intel/cannonlake: Enable ISH from device ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29274/1/src/soc/intel/cannonlake/romstage/f… File src/soc/intel/cannonlake/romstage/fsp_params.c: https://review.coreboot.org/#/c/29274/1/src/soc/intel/cannonlake/romstage/f… PS1, Line 59: const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH); move this to the beginning of the function -- To view, visit https://review.coreboot.org/29274 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Gerrit-Change-Number: 29274 Gerrit-PatchSet: 1 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Kyoung Il Kim <kyoung.il.kim(a)intel.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 20:40:47 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/29362 ) Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... Abandoned duplicate -- To view, visit https://review.coreboot.org/29362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ib09913ef9307826f6b78068fc8a56fd852bdab2a Gerrit-Change-Number: 29362 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has abandoned this change. ( https://review.coreboot.org/29350 ) Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... Abandoned duplicate -- To view, visit https://review.coreboot.org/29350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee Gerrit-Change-Number: 29350 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/29350 ) Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... Patch Set 1: Yes... my mistake. -- To view, visit https://review.coreboot.org/29350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dab279019fe9ca55522ab3e65f51b9f459529ee Gerrit-Change-Number: 29350 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Tue, 30 Oct 2018 20:27:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Create MMIO ACPI access functions
by Richard Spiegel (Code Review) 30 Oct '18

30 Oct '18

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/29362 Change subject: soc/amd/stoneyridge: Create MMIO ACPI access functions ...................................................................... soc/amd/stoneyridge: Create MMIO ACPI access functions Now that the relationship between IO access and MMIO access has been established, create read/write functions to access ACPI standard registers through MMIO. BUG=b:118049037 TEST=Build grunt Change-Id: Ib09913ef9307826f6b78068fc8a56fd852bdab2a Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/sb_util.c 2 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/29362/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 681f149..6b96c81 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -444,6 +444,12 @@ void pm_write8(u8 reg, u8 value); void pm_write16(u8 reg, u16 value); void pm_write32(u8 reg, u32 value); +u8 acpi_mmio_read8(u8 reg); +u16 acpi_mmio_read16(u8 reg); +u32 acpi_mmio_read32(u8 reg); +void acpi_mmio_write8(u8 reg, u8 value); +void acpi_mmio_write16(u8 reg, u16 value); +void acpi_mmio_write32(u8 reg, u32 value); u32 misc_read32(u8 reg); void misc_write32(u8 reg, u32 value); uint8_t smi_read8(uint8_t offset); diff --git a/src/soc/amd/stoneyridge/sb_util.c b/src/soc/amd/stoneyridge/sb_util.c index 9daf0bb..f6bfcc9 100644 --- a/src/soc/amd/stoneyridge/sb_util.c +++ b/src/soc/amd/stoneyridge/sb_util.c @@ -56,6 +56,36 @@ return read32((void *)(PM_MMIO_BASE + reg)); } +u8 acpi_mmio_read8(u8 reg) +{ + return read8((u8 *)(ACPI_REG_MMIO_BASE + reg)); +} + +u16 acpi_mmio_read16(u8 reg) +{ + return read16((u16 *)(ACPI_REG_MMIO_BASE + reg)); +} + +u32 acpi_mmio_read32(u8 reg) +{ + return read32((u32 *)(ACPI_REG_MMIO_BASE + reg)); +} + +void acpi_mmio_write8(u8 reg, u8 value) +{ + write8((u8 *)(ACPI_REG_MMIO_BASE + reg), value); +} + +void acpi_mmio_write16(u8 reg, u16 value) +{ + write16((u16 *)(ACPI_REG_MMIO_BASE + reg), value); +} + +void acpi_mmio_write32(u8 reg, u32 value) +{ + write32((u32 *)(ACPI_REG_MMIO_BASE + reg), value); +} + void smi_write32(uint8_t offset, uint32_t value) { write32((void *)(APU_SMI_BASE + offset), value); -- To view, visit https://review.coreboot.org/29362 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib09913ef9307826f6b78068fc8a56fd852bdab2a Gerrit-Change-Number: 29362 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... soc/amd/stoneyridge: Set IOMMU support to follow device setting Instead of forcing the IOMMU to be enabled, change it to only be enabled if the device is enabled in devicetree. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/29343 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> --- M src/soc/amd/common/block/pi/agesawrapper.c M src/soc/amd/stoneyridge/northbridge.c 2 files changed, 8 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Daniel Kurtz: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 87e0b69..181eafd 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -29,6 +29,7 @@ #include <amdblocks/agesawrapper.h> #include <amdblocks/image.h> #include <amdblocks/BiosCallOuts.h> +#include <soc/pci_devs.h> #include <soc/southbridge.h> #include <soc/northbridge.h> #include <soc/cpu.h> @@ -323,8 +324,11 @@ */ AMD_LATE_PARAMS *LateParams = create_struct(&AmdParamStruct); - LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; - LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + const struct device *dev = dev_find_slot(0, IOMMU_DEVFN); + if (dev && dev->enabled) { + LateParams->GnbLateConfiguration.GnbIoapicId = CONFIG_MAX_CPUS + 1; + LateParams->GnbLateConfiguration.FchIoapicId = CONFIG_MAX_CPUS; + } timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = AmdInitLate(LateParams); diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index 5fb28c0..3a0c77d 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -506,7 +506,8 @@ void SetNbEnvParams(GNB_ENV_CONFIGURATION *params) { - params->IommuSupport = TRUE; + const struct device *dev = SOC_IOMMU_DEV; + params->IommuSupport = dev && dev->enabled; set_board_env_params(params); } -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/kahlee: Disable IOMMU
by Martin Roth (Code Review) 30 Oct '18

30 Oct '18

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/29342 ) Change subject: mb/google/kahlee: Disable IOMMU ...................................................................... mb/google/kahlee: Disable IOMMU Unfortunately Stoney has an issue where enabling the IOMMU causes a 10%-50% decrease in the integrated graphics performance. It is also disabled by default on other stoney platforms. BUG=b:118612241 TEST=Verify that IOMMU is disabled. Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/29342 Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Daniel Kurtz <djkurtz(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/kahlee/variants/aleena/devicetree.cb M src/mainboard/google/kahlee/variants/careena/devicetree.cb M src/mainboard/google/kahlee/variants/delan/devicetree.cb M src/mainboard/google/kahlee/variants/grunt/devicetree.cb M src/mainboard/google/kahlee/variants/liara/devicetree.cb 5 files changed, 5 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Daniel Kurtz: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb index 5438e6d..27a8e28 100644 --- a/src/mainboard/google/kahlee/variants/aleena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/aleena/devicetree.cb @@ -58,7 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/careena/devicetree.cb b/src/mainboard/google/kahlee/variants/careena/devicetree.cb index b541c03..23253b2 100644 --- a/src/mainboard/google/kahlee/variants/careena/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/careena/devicetree.cb @@ -61,7 +61,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/delan/devicetree.cb b/src/mainboard/google/kahlee/variants/delan/devicetree.cb index 0dfe204..fd30d5d 100644 --- a/src/mainboard/google/kahlee/variants/delan/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/delan/devicetree.cb @@ -55,7 +55,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb index 5a8906b..b37e1bf 100644 --- a/src/mainboard/google/kahlee/variants/grunt/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/grunt/devicetree.cb @@ -61,7 +61,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU (Disabled for performance and battery) device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge diff --git a/src/mainboard/google/kahlee/variants/liara/devicetree.cb b/src/mainboard/google/kahlee/variants/liara/devicetree.cb index cea3425..343fbeb 100644 --- a/src/mainboard/google/kahlee/variants/liara/devicetree.cb +++ b/src/mainboard/google/kahlee/variants/liara/devicetree.cb @@ -58,7 +58,7 @@ end device domain 0 on device pci 0.0 on end # Root Complex - device pci 0.2 on end # IOMMU + device pci 0.2 off end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge -- To view, visit https://review.coreboot.org/29342 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d Gerrit-Change-Number: 29342 Gerrit-PatchSet: 3 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corr...
by Nick Vaccaro (Code Review) 30 Oct '18

30 Oct '18

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/29361 ) Change subject: mb/google/poppy/variant/nocturne: adjust RcompTarget to fix DRAM corruption ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/29361/1/src/mainboard/google/poppy/variants… File src/mainboard/google/poppy/variants/nocturne/memory.c: https://review.coreboot.org/#/c/29361/1/src/mainboard/google/poppy/variants… PS1, Line 36: 30 > Does this value work for both KBL and AML? Was this change validated on all the different Nocturne S […] That is a question for Intel. I posted this CL per their request in comment #134 on b:111812662. I personally haven't performed any verification on this change. -- To view, visit https://review.coreboot.org/29361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefc3957f915a39a47ad6018459e65b70d1b34091 Gerrit-Change-Number: 29361 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 19:30:34 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/amd/stoneyridge: Set IOMMU support to follow device setting
by Daniel Kurtz (Code Review) 30 Oct '18

30 Oct '18

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/29343 ) Change subject: soc/amd/stoneyridge: Set IOMMU support to follow device setting ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/29343 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e Gerrit-Change-Number: 29343 Gerrit-PatchSet: 2 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 30 Oct 2018 19:18:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit October 2018