October 2018 - coreboot-gerrit

Change in coreboot[master]: nb/intel/haswell: Add a PCI ID for a Mini-HD audio controller
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29379 Change subject: nb/intel/haswell: Add a PCI ID for a Mini-HD audio controller ...................................................................... nb/intel/haswell: Add a PCI ID for a Mini-HD audio controller The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS. Change-Id: I3679d1ab0ae08726bff04c5985d6d93437b2fb81 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/northbridge/intel/haswell/minihd.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/29379/1 diff --git a/src/northbridge/intel/haswell/minihd.c b/src/northbridge/intel/haswell/minihd.c index 52710bb..4f7e201 100644 --- a/src/northbridge/intel/haswell/minihd.c +++ b/src/northbridge/intel/haswell/minihd.c @@ -128,7 +128,7 @@ .ops_pci = &minihd_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x0a0c, 0 }; +static const unsigned short pci_device_ids[] = { 0x0a0c, 0x0c0c, 0 }; static const struct pci_driver haswell_minihd __pci_driver = { .ops = &minihd_ops, -- To view, visit https://review.coreboot.org/29379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3679d1ab0ae08726bff04c5985d6d93437b2fb81 Gerrit-Change-Number: 29379 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Add a PCI ID for an SMBus controller
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29377 Change subject: sb/intel/lynxpoint: Add a PCI ID for an SMBus controller ...................................................................... sb/intel/lynxpoint: Add a PCI ID for an SMBus controller The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS. Change-Id: Idc222392a0973f9ea62b943d18dd762b48c76d17 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/smbus.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/29377/1 diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index f9deb7d..307d7d4 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -109,7 +109,10 @@ .ops_pci = &smbus_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x1c22, 0x1e22, 0x9c22, 0 }; +static const unsigned short pci_device_ids[] = { + 0x1c22, 0x1e22, 0x8c22, 0x9c22, + 0 +}; static const struct pci_driver pch_smbus __pci_driver = { .ops = &smbus_ops, -- To view, visit https://review.coreboot.org/29377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Idc222392a0973f9ea62b943d18dd762b48c76d17 Gerrit-Change-Number: 29377 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: nb/intel/haswell: Add a PCI ID for a desktop memory controller
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29378 Change subject: nb/intel/haswell: Add a PCI ID for a desktop memory controller ...................................................................... nb/intel/haswell: Add a PCI ID for a desktop memory controller The PCI ID was taken from the output of `lspci` on an ASRock H81M-HDS. Change-Id: Ie162cb7a27e313ffe612659e8444657a3772d3c9 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/northbridge.c 2 files changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/29378/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 3099a59..d14ee4f 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -210,6 +210,7 @@ u8 reserved[34]; } __packed; +#define PCI_DEVICE_ID_HSW_DESKTOP 0x0c00 #define PCI_DEVICE_ID_HSW_MOBILE 0x0c04 #define PCI_DEVICE_ID_HSW_ULT 0x0a04 diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index 0453246..ccfb234 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -461,6 +461,12 @@ .ops_pci = &intel_pci_ops, }; +static const struct pci_driver mc_driver_hsw_normal __pci_driver = { + .ops = &mc_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_HSW_DESKTOP, +}; + static const struct pci_driver mc_driver_hsw_mobile __pci_driver = { .ops = &mc_ops, .vendor = PCI_VENDOR_ID_INTEL, -- To view, visit https://review.coreboot.org/29378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie162cb7a27e313ffe612659e8444657a3772d3c9 Gerrit-Change-Number: 29378 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: sb/intel/lynxpoint: Add PCI IDs for more SKUs
by Tristan Corrick (Code Review) Oct. 31, 2018

Oct. 31, 2018

Tristan Corrick has uploaded this change for review. ( https://review.coreboot.org/29376 Change subject: sb/intel/lynxpoint: Add PCI IDs for more SKUs ...................................................................... sb/intel/lynxpoint: Add PCI IDs for more SKUs The PCI IDs were taken from the Intel Lynx Point datasheet [1]. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: Ie4a264e9325d185334c3d7f7d2ed3c394ac33059 Signed-off-by: Tristan Corrick <tristan(a)corrick.kiwi> --- M src/southbridge/intel/lynxpoint/lpc.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/29376/1 diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 5b09fed..6483e6d 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -856,6 +856,11 @@ 0x8c4c, /* Q85 SKU */ 0x8c4e, /* Q87 SKU */ 0x8c4f, /* QM87 SKU */ + 0x8c50, /* B85 SKU */ + 0x8c52, /* C222 SKU */ + 0x8c54, /* C224 SKU */ + 0x8c56, /* C226 SKU */ + 0x8c5c, /* H81 SKU */ 0x9c41, /* LP Full Featured Engineering Sample */ 0x9c43, /* LP Premium SKU */ 0x9c45, /* LP Mainstream SKU */ -- To view, visit https://review.coreboot.org/29376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ie4a264e9325d185334c3d7f7d2ed3c394ac33059 Gerrit-Change-Number: 29376 Gerrit-PatchSet: 1 Gerrit-Owner: Tristan Corrick <tristan(a)corrick.kiwi>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM de...
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has abandoned this change. ( https://review.coreboot.org/29374 ) Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM devices ...................................................................... Abandoned Need to solve merge conflict -- To view, visit https://review.coreboot.org/29374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I97aeb725ee5fb162b958e4f83f73814c55a6066b Gerrit-Change-Number: 29374 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29375 Change subject: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources ...................................................................... src/soc/intel/braswell/northcluster.c: Reserve local APIC resources The resources of the local APIC are not reserved. Use mmio_resource() to add local APIC resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/29375/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 3245a28..b4964f3 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/memmap.h> +#include <cpu/x86/lapic.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> @@ -149,6 +150,13 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); + /* + * Reserve local APIC + */ + base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE); + size_k = (0x00100000/1024); + mmio_resource(dev, index++, base_k, size_k); + chromeos_reserve_ram_oops(dev, index++); } -- To view, visit https://review.coreboot.org/29375 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903 Gerrit-Change-Number: 29375 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has abandoned this change. ( https://review.coreboot.org/29370 ) Change subject: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources ...................................................................... Abandoned Merge conflict -- To view, visit https://review.coreboot.org/29370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd Gerrit-Change-Number: 29370 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE dev...
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has uploaded a new patch set (#2). ( https://review.coreboot.org/29373 ) Change subject: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE devices ...................................................................... src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPE devices ACPI code for LPE devices is enabled, but devices are disabled on the platform. Remove the LPE devices when these are disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/southcluster.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29373/2 -- To view, visit https://review.coreboot.org/29373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d Gerrit-Change-Number: 29373 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM de...
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29374 Change subject: src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM devices ...................................................................... src/soc/intel/braswell/acpi/lpss.asl: Remove disabled SPI1 and PWM devices ACPI code for these devices is enabled, but devices are disabled on the platform. Remove these devices when disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I97aeb725ee5fb162b958e4f83f73814c55a6066b Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/lpss.asl 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/29374/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 6e3adcd..1f44e78 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -127,6 +127,13 @@ string default "soc/intel/braswell/bootblock/timestamp.inc" +config INCLUDE_SPI1_AND_PWM + bool "Include ASL code for SPI1 and PWM devices" + default y + help + Enable this if the SPI1 and PWM interfaces are supported + This requires an FSP update. + config ENABLE_LPE_DEVICES bool "Include ASL code for LPE devices" default y diff --git a/src/soc/intel/braswell/acpi/lpss.asl b/src/soc/intel/braswell/acpi/lpss.asl index 4cc93cc..5e71101 100644 --- a/src/soc/intel/braswell/acpi/lpss.asl +++ b/src/soc/intel/braswell/acpi/lpss.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -522,6 +523,11 @@ } } +// +// Remove the devices that can't be enabled from ASL. This will keep Linux from trying to +// use them even tough they are disabled. +// +#if IS_ENABLED(CONFIG_INCLUDE_SPI1_AND_PWM) Device (SPI1) { Name (_HID, "8086228E") @@ -630,6 +636,7 @@ } } } +#endif Device (UAR1) { -- To view, visit https://review.coreboot.org/29374 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I97aeb725ee5fb162b958e4f83f73814c55a6066b Gerrit-Change-Number: 29374 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPEdevices
by Frans Hendriks (Code Review) Oct. 31, 2018

Oct. 31, 2018

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29373 Change subject: src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPEdevices ...................................................................... src/soc/intel/braswell/acpi/southcluster.asl: Remove disabled LPEdevices ACPI code for LPE devices enabled, but devcies are disabled on the platform Remove the LPE devices when these are disabled. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/acpi/southcluster.asl 2 files changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/29373/1 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 2ba7992..6e3adcd 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -127,4 +127,10 @@ string default "soc/intel/braswell/bootblock/timestamp.inc" +config ENABLE_LPE_DEVICES + bool "Include ASL code for LPE devices" + default y + help + Enable this if the LPE interfaces are supported + endif diff --git a/src/soc/intel/braswell/acpi/southcluster.asl b/src/soc/intel/braswell/acpi/southcluster.asl index f7e3168..7ec8c54 100644 --- a/src/soc/intel/braswell/acpi/southcluster.asl +++ b/src/soc/intel/braswell/acpi/southcluster.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Google Inc. + * Copyright (C) 2018 Eltan B.V. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -287,6 +288,8 @@ /* SCC Devices */ #include "scc.asl" +#if IS_ENABLED(CONFIG_ENABLE_LPE_DEVICES) /* LPE Device */ #include "lpe.asl" +#endif } -- To view, visit https://review.coreboot.org/29373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9973ba88df82c61863d16a7b4f3955af2efb7a0d Gerrit-Change-Number: 29373 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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