coreboot-gerrit October 2018

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources
by Frans Hendriks (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29370 to look at the new patch set (#2). Change subject: src/soc/intel/braswell/northcluster.c: Reserve local APIC resources ...................................................................... src/soc/intel/braswell/northcluster.c: Reserve local APIC resources The resources of the local APIC are not reserved. Use mmio_resource() to add local APIC resources. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29370/2 -- To view, visit https://review.coreboot.org/29370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd Gerrit-Change-Number: 29370 Gerrit-PatchSet: 2 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/cannonlake: Add additional UPD
by Philipp Deppenwiese (Code Review) 31 Oct '18

31 Oct '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/29324 ) Change subject: soc/intel/cannonlake: Add additional UPD ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Iddd2ffac59561941319563d1bbc45c542f99da27 Gerrit-Change-Number: 29324 Gerrit-PatchSet: 5 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: soc/intel/fsp_broadwell_de: Add additional UPDs
by Philipp Deppenwiese (Code Review) 31 Oct '18

31 Oct '18

Philipp Deppenwiese has abandoned this change. ( https://review.coreboot.org/29323 ) Change subject: soc/intel/fsp_broadwell_de: Add additional UPDs ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/29323 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I2687a52d4fa6f88d1a5fb5e83cc02419d688f6b4 Gerrit-Change-Number: 29323 Gerrit-PatchSet: 2 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent o...
by Frans Hendriks (Code Review) 31 Oct '18

31 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29371 Change subject: src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS. ...................................................................... src/drivers/intel/fsp1_1/raminit.c: Make check FSP HOBs independent of CONFIG_DISPLAY_HOBS. Check for FSP HOBS is disabled when CONFIG_DISPLAY_HOBS is disabled. Use the CONFIG_DISPLAY_HOBS for determination of display HOB info only. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/drivers/intel/fsp1_1/raminit.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/29371/1 diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index c7d8722..3adced2 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -50,10 +50,8 @@ VPD_DATA_REGION *vpd_ptr; UPD_DATA_REGION *upd_ptr; int fsp_verification_failure = 0; -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; -#endif /* * Find and copy the UPD region to the stack so the platform can modify @@ -193,7 +191,6 @@ memory_info_hob); } -#if IS_ENABLED(CONFIG_DISPLAY_HOBS) if (hob_list_ptr == NULL) die("ERROR - HOB pointer is NULL!\n"); @@ -241,8 +238,8 @@ "ERROR - Missing one or more required FSP HOBs!\n"); /* Display the HOBs */ - print_hob_type_structure(0, hob_list_ptr); -#endif + if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) + print_hob_type_structure(0, hob_list_ptr); /* Get the address of the CBMEM region for the FSP reserved memory */ fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY); -- To view, visit https://review.coreboot.org/29371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3776fa37866c7ef3aea090842387660c22bbdd4d Gerrit-Change-Number: 29371 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve of local APIC
by Frans Hendriks (Code Review) 31 Oct '18

31 Oct '18

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29370 Change subject: src/soc/intel/braswell/northcluster.c: Reserve of local APIC ...................................................................... src/soc/intel/braswell/northcluster.c: Reserve of local APIC The resources of the local APIC are not reserved. Use mmio_resource() to add local APIC resource. BUG=N/A TEST=Intel CherryHill CRB Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd Signed-off-by: Frans Hendriks <fhendriks(a)eltan.com> --- M src/soc/intel/braswell/northcluster.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29370/1 diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index ea64483..0b21682 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <fsp/memmap.h> +#include <cpu/x86/lapic.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/iosf.h> @@ -149,6 +150,13 @@ reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); + /* + * Reserve local APIC + */ + base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE); + size_k = (0x00100000/1024); + mmio_resource(dev, index++, base_k, size_k); + if (IS_ENABLED(CONFIG_CHROMEOS)) chromeos_reserve_ram_oops(dev, index++); } -- To view, visit https://review.coreboot.org/29370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd Gerrit-Change-Number: 29370 Gerrit-PatchSet: 1 Gerrit-Owner: Frans Hendriks <fhendriks(a)eltan.com>

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Change in coreboot[master]: cpu/amd: Replace MSR addresses with macros
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29369 to look at the new patch set (#2). Change subject: cpu/amd: Replace MSR addresses with macros ...................................................................... cpu/amd: Replace MSR addresses with macros Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/car/cache_as_ram.inc M src/cpu/amd/microcode/microcode.c M src/include/cpu/amd/msr.h 3 files changed, 8 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29369/2 -- To view, visit https://review.coreboot.org/29369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Gerrit-Change-Number: 29369 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: cpu/amd: Replace MSR addresses with macros
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29369 Change subject: cpu/amd: Replace MSR addresses with macros ...................................................................... cpu/amd: Replace MSR addresses with macros Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/car/cache_as_ram.inc M src/cpu/amd/microcode/microcode.c M src/include/cpu/amd/msr.h 3 files changed, 7 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/29369/1 diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 7cbf1db..e4c2704 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -415,26 +415,26 @@ jmp_if_not_fam15h(fam15_car_msr_setup_complete) /* Disable streaming store (DisSS = 1) */ - mov $0xc0011020, %ecx + mov $LS_CFG_MSR, %ecx rdmsr bts $28, %eax wrmsr /* Disable speculative ITLB reloads (DisSpecTlbRld = 1) */ - mov $0xc0011021, %ecx + mov $IC_CFG_MSR, %ecx rdmsr bts $9, %eax wrmsr /* Disable speculative DTLB reloads (DisSpecTlbRld = 1) and set DisHwPf = 1 */ - mov $0xc0011022, %ecx + mov $DC_CFG_MSR, %ecx rdmsr bts $4, %eax bts $13, %eax wrmsr /* Disable CR0 combining (CombineCr0Cd = 0) */ - mov $0xc001102b, %ecx + mov $BU_CFG3_MSR, %ecx rdmsr btr $49-32, %edx wrmsr diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 68b6953..dad040b 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -121,7 +121,7 @@ msr.hi = 0; msr.lo = (uint32_t)m; - wrmsr(0xc0010020, msr); + wrmsr(MSR_PATCH_LOADER, msr); UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id); diff --git a/src/include/cpu/amd/msr.h b/src/include/cpu/amd/msr.h index 46ec70d..5d7b5e4 100644 --- a/src/include/cpu/amd/msr.h +++ b/src/include/cpu/amd/msr.h @@ -58,6 +58,8 @@ #define PSTATE_3_MSR 0xC0010067 #define PSTATE_4_MSR 0xC0010068 +#define MSR_PATCH_LOADER 0xC0010020 + #define MSR_COFVID_STS 0xC0010071 #define MSR_CSTATE_ADDRESS 0xC0010073 #define OSVW_ID_Length 0xC0010140 -- To view, visit https://review.coreboot.org/29369 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia296e1f9073b45c9137d17fbef29ce4fdfabcb7c Gerrit-Change-Number: 29369 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: amd/mtrr: Fix IORR MTRR
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#7). Change subject: amd/mtrr: Fix IORR MTRR ...................................................................... amd/mtrr: Fix IORR MTRR IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c 4 files changed, 11 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/7 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 7 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: mb/google/fizz: Remove variant_cros_gpios from variant
by David Wu (Code Review) 31 Oct '18

31 Oct '18

David Wu has uploaded this change for review. ( https://review.coreboot.org/29368 Change subject: mb/google/fizz: Remove variant_cros_gpios from variant ...................................................................... mb/google/fizz: Remove variant_cros_gpios from variant This change removes the function defintions from variant so that the weak definition in baseboard can be used. Refer to CL:813944. BUG=none BRANCH=master TEST=Build and boot on DUT Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781 Signed-off-by: David Wu <David_Wu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/fizz/variants/karma/gpio.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/29368/1 diff --git a/src/mainboard/google/fizz/variants/karma/gpio.c b/src/mainboard/google/fizz/variants/karma/gpio.c index e6bb83b..29c6f88 100644 --- a/src/mainboard/google/fizz/variants/karma/gpio.c +++ b/src/mainboard/google/fizz/variants/karma/gpio.c @@ -273,14 +273,3 @@ *num = ARRAY_SIZE(early_gpio_table); return early_gpio_table; } - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} -- To view, visit https://review.coreboot.org/29368 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781 Gerrit-Change-Number: 29368 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com>

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Change in coreboot[master]: amd/mtrr: Fix IORR MTRR
by Elyes HAOUAS (Code Review) 31 Oct '18

31 Oct '18

Hello Richard Spiegel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/29352 to look at the new patch set (#6). Change subject: amd/mtrr: Fix IORR MTRR ...................................................................... amd/mtrr: Fix IORR MTRR IORR MTRR definitions renamed to avoid collision between <cpu/amd/mtrr.h> and <AGESA.h>. Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/cpu/amd/mtrr/amd_mtrr.c M src/include/cpu/amd/mtrr.h M src/northbridge/amd/amdmct/mct/mctdqs_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c 4 files changed, 11 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29352/6 -- To view, visit https://review.coreboot.org/29352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3eeb0c69bbb76039039dc90683670cafcb00ed36 Gerrit-Change-Number: 29352 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit October 2018