Change in coreboot[master]: src/soc/intel/braswell/northcluster.c: Reserve of local APIC

[Frans Hendriks (Code Review)]

Frans Hendriks has uploaded this change for review. ( https://review.coreboot.org/29370

Change subject: src/soc/intel/braswell/northcluster.c: Reserve of local APIC
......................................................................

src/soc/intel/braswell/northcluster.c: Reserve of local APIC

The resources of the local APIC are not reserved.
Use mmio_resource() to add local APIC resource.

BUG=N/A
TEST=Intel CherryHill CRB

Change-Id: I58b69f8efb109c31f967eef2f7b6b3d5eeaa66fd
Signed-off-by: Frans Hendriks 
---
M src/soc/intel/braswell/northcluster.c
1 file changed, 8 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/29370/1

diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c
index ea64483..0b21682 100644
--- a/src/soc/intel/braswell/northcluster.c
+++ b/src/soc/intel/braswell/northcluster.c
@@ -22,6 +22,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <fsp/memmap.h>
+#include <cpu/x86/lapic.h>
 #include <fsp/util.h>
 #include <soc/iomap.h>
 #include <soc/iosf.h>
@@ -149,6 +150,13 @@
    reserved_ram_resource(dev, index++, (0xc0000 >> 10),
    		      (0x100000 - 0xc0000) >> 10);

+	/*
+	 * Reserve local APIC
+	 */
+	base_k = RES_IN_KIB(LAPIC_DEFAULT_BASE);
+	size_k = (0x00100000/1024);
+	mmio_resource(dev, index++, base_k, size_k);
+
    if (IS_ENABLED(CONFIG_CHROMEOS))
    	chromeos_reserve_ram_oops(dev, index++);
 }