coreboot-gerrit September 2017

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Change in coreboot[master]: google/cyan: fix variant memory/silicon init params overrride
by Matt DeVillier (Code Review) 26 Sep '17

26 Sep '17

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/21704 Change subject: google/cyan: fix variant memory/silicon init params overrride ...................................................................... google/cyan: fix variant memory/silicon init params overrride The mainboard_memory_init_params() and mainboard_silicon_init_params() methods already have weak declarations in drivers/intel/fsp1_1, so having them declared as weak in the cyan baseboard has the effect of them not being called at all unless overriden at the variant level. Therefore, remove the weak declarations in the baseboard and ensure that each variant has its own init functions if needed. TEST: build/boot google/cyan Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/cyan/ramstage.c M src/mainboard/google/cyan/romstage.c M src/mainboard/google/cyan/variants/celes/Makefile.inc A src/mainboard/google/cyan/variants/celes/romstage.c M src/mainboard/google/cyan/variants/cyan/Makefile.inc A src/mainboard/google/cyan/variants/cyan/romstage.c M src/mainboard/google/cyan/variants/edgar/Makefile.inc A src/mainboard/google/cyan/variants/edgar/romstage.c M src/mainboard/google/cyan/variants/reks/Makefile.inc A src/mainboard/google/cyan/variants/reks/romstage.c 10 files changed, 112 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/21704/1 diff --git a/src/mainboard/google/cyan/ramstage.c b/src/mainboard/google/cyan/ramstage.c index 093a49b..1da5b44 100644 --- a/src/mainboard/google/cyan/ramstage.c +++ b/src/mainboard/google/cyan/ramstage.c @@ -12,10 +12,3 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ - -#include <soc/ramstage.h> - -__attribute__ ((weak)) -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ -} diff --git a/src/mainboard/google/cyan/romstage.c b/src/mainboard/google/cyan/romstage.c index 57c40e0..39088bb 100644 --- a/src/mainboard/google/cyan/romstage.c +++ b/src/mainboard/google/cyan/romstage.c @@ -15,7 +15,6 @@ */ #include <soc/romstage.h> -#include <chip.h> /* All FSP specific code goes in this block */ void mainboard_romstage_entry(struct romstage_params *rp) @@ -26,17 +25,4 @@ /* Call back into chipset code with platform values updated. */ romstage_common(rp); -} - -__attribute__ ((weak)) -void mainboard_memory_init_params(struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - /* Update SPD data */ - if (!IS_ENABLED(CONFIG_BOARD_GOOGLE_CYAN)) { - memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; - } - memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; - memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; - memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; } diff --git a/src/mainboard/google/cyan/variants/celes/Makefile.inc b/src/mainboard/google/cyan/variants/celes/Makefile.inc index 0fcc9ad..23d2c72 100644 --- a/src/mainboard/google/cyan/variants/celes/Makefile.inc +++ b/src/mainboard/google/cyan/variants/celes/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/celes/romstage.c b/src/mainboard/google/cyan/variants/celes/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/celes/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/cyan/Makefile.inc b/src/mainboard/google/cyan/variants/cyan/Makefile.inc index ea80446..76de7be 100644 --- a/src/mainboard/google/cyan/variants/cyan/Makefile.inc +++ b/src/mainboard/google/cyan/variants/cyan/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/cyan/romstage.c b/src/mainboard/google/cyan/variants/cyan/romstage.c new file mode 100644 index 0000000..717db35 --- /dev/null +++ b/src/mainboard/google/cyan/variants/cyan/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_DDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/edgar/Makefile.inc b/src/mainboard/google/cyan/variants/edgar/Makefile.inc index e553c88..d9a7c7b 100644 --- a/src/mainboard/google/cyan/variants/edgar/Makefile.inc +++ b/src/mainboard/google/cyan/variants/edgar/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/edgar/romstage.c b/src/mainboard/google/cyan/variants/edgar/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/edgar/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} diff --git a/src/mainboard/google/cyan/variants/reks/Makefile.inc b/src/mainboard/google/cyan/variants/reks/Makefile.inc index 6577124..db2eea3 100644 --- a/src/mainboard/google/cyan/variants/reks/Makefile.inc +++ b/src/mainboard/google/cyan/variants/reks/Makefile.inc @@ -14,6 +14,7 @@ ## GNU General Public License for more details. ## +romstage-y += romstage.c romstage-y += spd_util.c ramstage-y += gpio.c diff --git a/src/mainboard/google/cyan/variants/reks/romstage.c b/src/mainboard/google/cyan/variants/reks/romstage.c new file mode 100644 index 0000000..b720e3d --- /dev/null +++ b/src/mainboard/google/cyan/variants/reks/romstage.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/romstage.h> +#include <chip.h> + +void mainboard_memory_init_params(struct romstage_params *params, + MEMORY_INIT_UPD *memory_params) +{ + memory_params->PcdMemoryTypeEnable = MEM_LPDDR3; + memory_params->PcdMemorySpdPtr = (u32)params->pei_data->spd_data_ch0; + memory_params->PcdMemChannel0Config = params->pei_data->spd_ch0_config; + memory_params->PcdMemChannel1Config = params->pei_data->spd_ch1_config; +} -- To view, visit https://review.coreboot.org/21704 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Gerrit-Change-Number: 21704 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: mainboard/intel/cannonlake_rvp: Add smi support in board
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21542 ) Change subject: mainboard/intel/cannonlake_rvp: Add smi support in board ...................................................................... Patch Set 7: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61141/ : SUCCESS -- To view, visit https://review.coreboot.org/21542 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509 Gerrit-Change-Number: 21542 Gerrit-PatchSet: 7 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: AndreX Andraos <andrex.andraos(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:54:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Refactor GPIO functions
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21684 ) Change subject: amd/stoneyridge: Refactor GPIO functions ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61139/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16307/ : SUCCESS -- To view, visit https://review.coreboot.org/21684 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47 Gerrit-Change-Number: 21684 Gerrit-PatchSet: 3 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:39:23 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Fix GPIO ASL
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21614 ) Change subject: google/kahlee: Fix GPIO ASL ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61140/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16308/ : SUCCESS -- To view, visit https://review.coreboot.org/21614 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Gerrit-Change-Number: 21614 Gerrit-PatchSet: 4 Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:37:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Move AmdInitEnv to ramstage
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21613 ) Change subject: amd/stoneyridge: Move AmdInitEnv to ramstage ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61136/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16304/ : SUCCESS -- To view, visit https://review.coreboot.org/21613 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5 Gerrit-Change-Number: 21613 Gerrit-PatchSet: 4 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:36:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Revert CAR teardown wbinvd
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20967 ) Change subject: soc/amd/stoneyridge: Revert CAR teardown wbinvd ...................................................................... Patch Set 11: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61138/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16306/ : SUCCESS -- To view, visit https://review.coreboot.org/20967 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a Gerrit-Change-Number: 20967 Gerrit-PatchSet: 11 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:35:15 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Put AGESA heap into cbmem
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21594 ) Change subject: amd/stoneyridge: Put AGESA heap into cbmem ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61135/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16303/ : SUCCESS -- To view, visit https://review.coreboot.org/21594 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848 Gerrit-Change-Number: 21594 Gerrit-PatchSet: 6 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:32:54 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/stoneyridge: Add postcar stage
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20966 ) Change subject: soc/amd/stoneyridge: Add postcar stage ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61137/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16305/ : SUCCESS -- To view, visit https://review.coreboot.org/20966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1 Gerrit-Change-Number: 20966 Gerrit-PatchSet: 11 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:32:50 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common: Clean up GetHeapBase function
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21593 ) Change subject: soc/amd/common: Clean up GetHeapBase function ...................................................................... Patch Set 6: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61134/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16302/ : SUCCESS -- To view, visit https://review.coreboot.org/21593 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789 Gerrit-Change-Number: 21593 Gerrit-PatchSet: 6 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:29:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/stoneyridge: Clean up include files in northbridge.h
by build bot (Jenkins) (Code Review) 26 Sep '17

26 Sep '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21615 ) Change subject: amd/stoneyridge: Clean up include files in northbridge.h ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/61133/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/16301/ : SUCCESS -- To view, visit https://review.coreboot.org/21615 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d Gerrit-Change-Number: 21615 Gerrit-PatchSet: 3 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Sep 2017 18:27:50 +0000 Gerrit-HasComments: No

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coreboot-gerrit September 2017