coreboot-gerrit January 2016

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New patch to review for coreboot: intel/sklrvp: Remove mainboard
by Martin Roth 26 Jan '16

26 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13469 -gerrit commit ac2d80f8685a474f80413e02f5506125bd8e15f9 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 26 09:25:09 2016 -0700 intel/sklrvp: Remove mainboard The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/intel/sklrvp/Kconfig | 44 ---- src/mainboard/intel/sklrvp/Kconfig.name | 2 - src/mainboard/intel/sklrvp/Makefile.inc | 24 -- src/mainboard/intel/sklrvp/abuild.disabled | 2 - src/mainboard/intel/sklrvp/acpi/chromeos.asl | 20 -- src/mainboard/intel/sklrvp/acpi/ec.asl | 14 - src/mainboard/intel/sklrvp/acpi/mainboard.asl | 221 ---------------- src/mainboard/intel/sklrvp/acpi/superio.asl | 14 - src/mainboard/intel/sklrvp/acpi_tables.c | 15 -- src/mainboard/intel/sklrvp/board_info.txt | 2 - src/mainboard/intel/sklrvp/chromeos.c | 70 ----- src/mainboard/intel/sklrvp/chromeos.fmd | 37 --- src/mainboard/intel/sklrvp/cmos.layout | 135 ---------- src/mainboard/intel/sklrvp/devicetree.cb | 142 ----------- src/mainboard/intel/sklrvp/dsdt.asl | 49 ---- src/mainboard/intel/sklrvp/fadt.c | 48 ---- src/mainboard/intel/sklrvp/gpio_rvp3.h | 351 -------------------------- src/mainboard/intel/sklrvp/onboard.h | 37 --- src/mainboard/intel/sklrvp/pei_data.c | 51 ---- src/mainboard/intel/sklrvp/ramstage.c | 23 -- src/mainboard/intel/sklrvp/romstage.c | 80 ------ src/mainboard/intel/sklrvp/spd/Makefile.inc | 37 --- src/mainboard/intel/sklrvp/spd/empty.spd.hex | 16 -- src/mainboard/intel/sklrvp/spd/rvp3.spd.hex | 16 -- src/mainboard/intel/sklrvp/spd/spd.c | 114 --------- src/mainboard/intel/sklrvp/spd/spd.h | 33 --- 26 files changed, 1597 deletions(-) diff --git a/src/mainboard/intel/sklrvp/Kconfig b/src/mainboard/intel/sklrvp/Kconfig deleted file mode 100644 index 0872aac..0000000 --- a/src/mainboard/intel/sklrvp/Kconfig +++ /dev/null @@ -1,44 +0,0 @@ -if BOARD_INTEL_SKLRVP - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select BOARD_ROMSIZE_KB_16384 - select HAVE_ACPI_RESUME - select HAVE_ACPI_TABLES - select HAVE_OPTION_TABLE - select HAVE_SMI_HANDLER - select MAINBOARD_HAS_CHROMEOS - select MAINBOARD_HAS_LPC_TPM - select MMCONF_SUPPORT - select MONOTONIC_TIMER_MSR - select PCIEXP_L1_SUB_STATE - select SOC_INTEL_SKYLAKE - -config CHROMEOS - select LID_SWITCH - select CHROMEOS_RAMOOPS_DYNAMIC - select CHROMEOS_VBNV_CMOS - select VBOOT_DYNAMIC_WORK_BUFFER - select VIRTUAL_DEV_SWITCH - -config IRQ_SLOT_COUNT - int - default 18 - -config BOOT_MEDIA_SPI_BUS - int - default 0 - -config MAINBOARD_DIR - string - default "intel/sklrvp" - -config MAINBOARD_PART_NUMBER - string - default "Skylake RVP" - -config MAX_CPUS - int - default 8 - -endif diff --git a/src/mainboard/intel/sklrvp/Kconfig.name b/src/mainboard/intel/sklrvp/Kconfig.name deleted file mode 100644 index c970f01..0000000 --- a/src/mainboard/intel/sklrvp/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_SKLRVP - bool "Skylake RVP3" diff --git a/src/mainboard/intel/sklrvp/Makefile.inc b/src/mainboard/intel/sklrvp/Makefile.inc deleted file mode 100644 index 048b023..0000000 --- a/src/mainboard/intel/sklrvp/Makefile.inc +++ /dev/null @@ -1,24 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Google Inc. -## Copyright (C) 2015 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -subdirs-y += spd - -romstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -romstage-y += pei_data.c - -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c -ramstage-y += pei_data.c -ramstage-y += ramstage.c diff --git a/src/mainboard/intel/sklrvp/abuild.disabled b/src/mainboard/intel/sklrvp/abuild.disabled deleted file mode 100644 index 7d1725a..0000000 --- a/src/mainboard/intel/sklrvp/abuild.disabled +++ /dev/null @@ -1,2 +0,0 @@ -Successful builds for this board require the Skylake FSP binary and header files -along with the Skylake microcode files from Intel. diff --git a/src/mainboard/intel/sklrvp/acpi/chromeos.asl b/src/mainboard/intel/sklrvp/acpi/chromeos.asl deleted file mode 100644 index 5c86fc5..0000000 --- a/src/mainboard/intel/sklrvp/acpi/chromeos.asl +++ /dev/null @@ -1,20 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -Name (OIPG, Package() { - Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button - Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect -}) diff --git a/src/mainboard/intel/sklrvp/acpi/ec.asl b/src/mainboard/intel/sklrvp/acpi/ec.asl deleted file mode 100644 index de9dc8c..0000000 --- a/src/mainboard/intel/sklrvp/acpi/ec.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ diff --git a/src/mainboard/intel/sklrvp/acpi/mainboard.asl b/src/mainboard/intel/sklrvp/acpi/mainboard.asl deleted file mode 100644 index 45f17bf..0000000 --- a/src/mainboard/intel/sklrvp/acpi/mainboard.asl +++ /dev/null @@ -1,221 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <soc/gpio.h> -#include <mainboard/intel/sklrvp/onboard.h> - -/* - * LPC Trusted Platform Module - */ -Scope (\_SB.PCI0.LPCB) -{ - #include <drivers/pc80/tpm/acpi/tpm.asl> -} - -/* - * WLAN connected to Root Port 3, becomes Root Port 1 after coalesce - */ -Scope (\_SB.PCI0.RP01) -{ - Device (WLAN) - { - Name (_ADR, 0x00000000) - - /* GPIO10 is PCH_WLAN_WAKE_L */ - Name (GPIO, 10) - - Name (_PRW, Package() { GPIO, 3 }) - - } -} - -Scope (\_SB.PCI0.I2C0) -{ - Device (ETPA) - { - Name (_HID, "SYN2393") - Name (_CID, "PNP0C50") - Name (_DDN, "Synaptic Touchpad") - Name (_UID, 3) - Name (ISTP, 1) /* Touchpad */ - - /* Fetch HidDescriptorAddress, Register offset in the - * I2C device at which the HID descriptor can be read - */ - Method (_DSM, 4, NotSerialized) - { - If (LEqual (Arg0, ToUUID ( - "3cdff6f7-4267-4555-ad05-b30a3d8938de"))) - { - If (LEqual (Arg2, Zero)) - { - If (LEqual (Arg1, One)) - { - Return (Buffer (One) - { - 0x03 - }) - } - Else - { - Return (Buffer (One) - { - 0x00 - }) - } - } - If (LEqual (Arg2, One)) - { - Return (0x20) - } - } - Else - { - Return (Buffer (One) - { - 0x00 - }) - } - - Return (Zero) - } - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TOUCHPAD_I2C_ADDR, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.PCI0.I2C0", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Level, ActiveLow) - { BOARD_TOUCHPAD_IRQ } - }) - } - - //----------------------------------- - // HD Audio I2S Codec device - // Realtek ALC286S (I2SC = 2) - //----------------------------------- - Device (HDAC) - { - Name (_HID, "INT343A") - Name (_CID, "INT343A") - Name (_DDN, "Intel(R) Smart Sound Technology Audio Codec") - Name (_UID, 1) - - Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings - { - /* update Audio codec slave address in runtime */ - Name (RBUF, ResourceTemplate () - { - I2cSerialBus (0x1C, ControllerInitiated, 400000, - AddressingMode7Bit, "\\_SB.PCI0.I2C0", - 0x00, ResourceConsumer, ,) - }) - - /* update interrupt number in runtime */ - Name (SBFI, ResourceTemplate () - { - Interrupt (ResourceConsumer, Level, ActiveLow, - ExclusiveAndWake) - { - GPP_E22_IRQ - } - }) - } - - Method (_STA, 0, NotSerialized) - { - Return (0xF) /* I2S Codec Enabled */ - } - } -} - -Scope (\_SB.PCI0.I2C1) -{ - Device (ATSA) - { - Name (_HID, "ATML3432") - Name (_DDN, "Atmel Touchscreen") - Name (_UID, 5) - Name (_S0W, 4) - Name (ISTP, 0) /* TouchScreen */ - Name (_CID, "PNP0C50") - - /* Fetch HidDescriptorAddress, Register offset in the - * I2C device at which the HID descriptor can be read - */ - Method (_DSM, 4, NotSerialized) - { - If (LEqual (Arg0, ToUUID ( - "3cdff6f7-4267-4555-ad05-b30a3d8938de"))) - { - If (LEqual (Arg2, Zero)) - { - If (LEqual (Arg1, One)) - { - Return (Buffer (One) - { - 0x03 - }) - } - Else - { - Return (Buffer (One) - { - 0x00 - }) - } - } - - If (LEqual (Arg2, One)) - { - Return (Zero) - } - } - Else - { - Return (Buffer (One) - { - 0x00 - }) - } - - Return (Zero) - } - - Name (_CRS, ResourceTemplate() - { - I2cSerialBus ( - BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress - ControllerInitiated, // SlaveMode - 400000, // ConnectionSpeed - AddressingMode7Bit, // AddressingMode - "\\_SB.PCI0.I2C1", // ResourceSource - ) - - Interrupt (ResourceConsumer, Level, ActiveLow) - { BOARD_TOUCHSCREEN_IRQ } - }) - - Method (_STA, 0, NotSerialized) - { - Return (0xF) - } - } -} diff --git a/src/mainboard/intel/sklrvp/acpi/superio.asl b/src/mainboard/intel/sklrvp/acpi/superio.asl deleted file mode 100644 index de9dc8c..0000000 --- a/src/mainboard/intel/sklrvp/acpi/superio.asl +++ /dev/null @@ -1,14 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ diff --git a/src/mainboard/intel/sklrvp/acpi_tables.c b/src/mainboard/intel/sklrvp/acpi_tables.c deleted file mode 100644 index ccf9f74..0000000 --- a/src/mainboard/intel/sklrvp/acpi_tables.c +++ /dev/null @@ -1,15 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ diff --git a/src/mainboard/intel/sklrvp/board_info.txt b/src/mainboard/intel/sklrvp/board_info.txt deleted file mode 100644 index 15ddb1f..0000000 --- a/src/mainboard/intel/sklrvp/board_info.txt +++ /dev/null @@ -1,2 +0,0 @@ -Category: eval -Release year: 2015 diff --git a/src/mainboard/intel/sklrvp/chromeos.c b/src/mainboard/intel/sklrvp/chromeos.c deleted file mode 100644 index 821b8b8..0000000 --- a/src/mainboard/intel/sklrvp/chromeos.c +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <rules.h> -#include <soc/gpio.h> -#include <string.h> -#include <vendorcode/google/chromeos/chromeos.h> - -#if ENV_RAMSTAGE -#include <boot/coreboot_tables.h> - -#define GPIO_COUNT 6 - -void fill_lb_gpios(struct lb_gpios *gpios) -{ - struct lb_gpio *gpio; - - gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); - gpios->count = GPIO_COUNT; - - gpio = gpios->gpios; - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", - get_recovery_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", - get_developer_mode_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", - get_lid_switch()); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); - fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", gfx_get_init_done()); -} -#endif /* ENV_RAMSTAGE */ - -int get_lid_switch(void) -{ - /* Default to force open */ - return 1; -} - -/* The dev-switch is virtual */ -int get_developer_mode_switch(void) -{ - return 0; -} - -int get_recovery_mode_switch(void) -{ - return 0; -} - -int get_write_protect_state(void) -{ - return 0; -} diff --git a/src/mainboard/intel/sklrvp/chromeos.fmd b/src/mainboard/intel/sklrvp/chromeos.fmd deleted file mode 100644 index f1b9342..0000000 --- a/src/mainboard/intel/sklrvp/chromeos.fmd +++ /dev/null @@ -1,37 +0,0 @@ -FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0xa00000 { - SI_DESC@0x0 0x1000 - SI_ME@0x1000 0x1ff000 - } - SI_BIOS@0xa00000 0x600000 { - RW_SECTION_A@0x0 0x100000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0xeffc0 - RW_FWID_A@0xfffc0 0x40 - } - RW_SECTION_B@0x100000 0x100000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0xeffc0 - RW_FWID_B@0xfffc0 0x40 - } - RW_MRC_CACHE@0x200000 0x10000 - RW_ELOG@0x210000 0x4000 - RW_SHARED@0x214000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 - } - RW_VPD@0x218000 0x2000 - RW_UNUSED@0x21a000 0x6000 - WP_RO@0x300000 0x300000 { - RO_VPD@0x0 0x4000 - RO_UNUSED@0x4000 0xc000 - RO_SECTION@0x10000 0x1f0000 { - FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 - GBB@0x1000 0xef000 - COREBOOT(CBFS)@0xf0000 0x200000 - } - } - } -} diff --git a/src/mainboard/intel/sklrvp/cmos.layout b/src/mainboard/intel/sklrvp/cmos.layout deleted file mode 100644 index 8467747..0000000 --- a/src/mainboard/intel/sklrvp/cmos.layout +++ /dev/null @@ -1,135 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2007-2008 coresystems GmbH -## Copyright (C) 2015 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -# ----------------------------------------------------------------- -entries - -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - -# ----------------------------------------------------------------- -0 120 r 0 reserved_memory -#120 264 r 0 unused - -# ----------------------------------------------------------------- -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 r 0 reboot_bits -#390 2 r 0 unused? - -# ----------------------------------------------------------------- -# coreboot config options: console -392 3 e 5 baud_rate -395 4 e 6 debug_level -#399 1 r 0 unused - -# coreboot config options: cpu -400 1 e 2 hyper_threading -#401 7 r 0 unused - -# coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -#411 5 r 0 unused - -# coreboot config options: bootloader -#Used by ChromeOS: -416 128 r 0 vbnv -#544 440 r 0 unused - -# SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 - -# coreboot config options: check sums -984 16 h 0 check_sum -#1000 24 r 0 amd_reserved - -# ----------------------------------------------------------------- - -enumerations - -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -5 0 115200 -5 1 57600 -5 2 38400 -5 3 19200 -5 4 9600 -5 5 4800 -5 6 2400 -5 7 1200 -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -# ----------------------------------------------------------------- -checksums - -checksum 392 415 984 - - diff --git a/src/mainboard/intel/sklrvp/devicetree.cb b/src/mainboard/intel/sklrvp/devicetree.cb deleted file mode 100644 index deb3ed7..0000000 --- a/src/mainboard/intel/sklrvp/devicetree.cb +++ /dev/null @@ -1,142 +0,0 @@ -chip soc/intel/skylake - - # SerialIO device modes - register "SerialIoDevMode" = "{ \ - [PchSerialIoIndexI2C0] = PchSerialIoPci, \ - [PchSerialIoIndexI2C1] = PchSerialIoPci, \ - [PchSerialIoIndexI2C2] = PchSerialIoPci, \ - [PchSerialIoIndexI2C3] = PchSerialIoPci, \ - [PchSerialIoIndexI2C4] = PchSerialIoPci, \ - [PchSerialIoIndexI2C5] = PchSerialIoPci, \ - [PchSerialIoIndexSpi0] = PchSerialIoPci, \ - [PchSerialIoIndexSpi1] = PchSerialIoPci, \ - [PchSerialIoIndexUart0] = PchSerialIoPci, \ - [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoPci, \ - }" - - # Enable eDP Hotplug with 6ms pulse - register "gpu_dp_d_hotplug" = "0x06" - - # Enable DDI1 Hotplug with 6ms pulse - register "gpu_dp_b_hotplug" = "0x06" - - # Enable DDI2 Hotplug with 6ms pulse - register "gpu_dp_c_hotplug" = "0x06" - - # Set backlight PWM values for eDP - register "gpu_cpu_backlight" = "0x00000200" - register "gpu_pch_backlight" = "0x04000000" - - # Enable Panel and configure power delays - register "gpu_panel_port_select" = "1" # eDP - register "gpu_panel_power_cycle_delay" = "6" # 500ms - register "gpu_panel_power_up_delay" = "2000" # 200ms - register "gpu_panel_power_down_delay" = "500" # 50ms - register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms - register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms - - register "pirqa_routing" = "0x8b" - register "pirqb_routing" = "0x8a" - register "pirqc_routing" = "0x8b" - register "pirqd_routing" = "0x8b" - register "pirqe_routing" = "0x80" - register "pirqf_routing" = "0x80" - register "pirqg_routing" = "0x80" - register "pirqh_routing" = "0x80" - - # Enable S0ix - register "s0ix_enable" = "0" - - # Probeless Trace function - register "ProbelessTrace" = "0" - - # Lan - register "EnableLan" = "0" - - # SATA related - register "EnableSata" = "0" - register "SataSalpSupport" = "0" - register "SataMode" = "0" - register "SataPortsEnable[0]" = "0" - - # Audio related - register "EnableAzalia" = "1" - register "EnableTraceHub" = "0" - register "DspEnable" = "1" - - # I/O Buffer Ownership: - # 0: HD-A Link - # 1 Shared, HD-A Link and I2S Port - # 3: I2S Ports - register "IoBufferOwnership" = "3" - - # USB related - register "SsicPortEnable" = "0" - - # SMBUS - register "SmbusEnable" = "1" - - # Camera - register "Cio2Enable" = "0" - - # eMMC - register "ScsEmmcEnabled" = "1" - register "ScsEmmcHs400Enabled" = "0" - register "ScsSdCardEnabled" = "2" - - # Integrated Sensor - register "IshEnable" = "0" - - # XDCI controller - register "XdciEnable" = "0" - - device cpu_cluster 0 on - device lapic 0 on end - end - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT-Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 on end # UART #1 - device pci 1e.2 on end # GSPI #0 - device pci 1e.3 on end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on end # LPC Interface - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 off end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE - end -end diff --git a/src/mainboard/intel/sklrvp/dsdt.asl b/src/mainboard/intel/sklrvp/dsdt.asl deleted file mode 100644 index a6e2361..0000000 --- a/src/mainboard/intel/sklrvp/dsdt.asl +++ /dev/null @@ -1,49 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -DefinitionBlock( - "dsdt.aml", - "DSDT", - 0x02, // DSDT revision: ACPI v2.0 - "COREv4", // OEM id - "COREBOOT", // OEM table id - 0x20110725 // OEM revision -) -{ - // Some generic macros - #include <soc/intel/skylake/acpi/platform.asl> - - // global NVS and variables - #include <soc/intel/skylake/acpi/globalnvs.asl> - - // CPU - #include <soc/intel/skylake/acpi/cpu.asl> - - Scope (\_SB) { - Device (PCI0) - { - #include <soc/intel/skylake/acpi/systemagent.asl> - #include <soc/intel/skylake/acpi/pch.asl> - } - } - - // Chipset specific sleep states - #include <soc/intel/skylake/acpi/sleepstates.asl> - - // Mainboard specific - #include "acpi/mainboard.asl" -} diff --git a/src/mainboard/intel/sklrvp/fadt.c b/src/mainboard/intel/sklrvp/fadt.c deleted file mode 100644 index 72bc484..0000000 --- a/src/mainboard/intel/sklrvp/fadt.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <string.h> -#include <soc/acpi.h> - -void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) -{ - acpi_header_t *header = &(fadt->header); - - memset((void *) fadt, 0, sizeof(acpi_fadt_t)); - memcpy(header->signature, "FACP", 4); - header->length = sizeof(acpi_fadt_t); - header->revision = 5; - memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); - header->asl_compiler_revision = 1; - - fadt->firmware_ctrl = (unsigned long) facs; - fadt->dsdt = (unsigned long) dsdt; - fadt->model = 1; - fadt->preferred_pm_profile = PM_MOBILE; - - fadt->x_firmware_ctl_l = (unsigned long)facs; - fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = (unsigned long)dsdt; - fadt->x_dsdt_h = 0; - - acpi_fill_in_fadt(fadt); - - header->checksum = - acpi_checksum((void *) fadt, header->length); -} diff --git a/src/mainboard/intel/sklrvp/gpio_rvp3.h b/src/mainboard/intel/sklrvp/gpio_rvp3.h deleted file mode 100644 index 8c5b4c0..0000000 --- a/src/mainboard/intel/sklrvp/gpio_rvp3.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the - * GNU General Public License for more details. - */ -#ifndef _GPIORVP3_H_ -#define _GPIORVP3_H_ - -#include <soc/gpio.h> - -static const GPIO_INIT_CONFIG GpioTableRvp3[] = { -{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_A11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_A12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_A22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_A23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_B0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, - GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, - GpioTermNone}}, -{GPIO_LP_GPP_B17, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, - GpioOutDefault, GpioIntEdge | GpioIntSci, GpioResetDeep, - GpioTermWpd20K}}, -{GPIO_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, - GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, - GpioTermWpu20K}}, -{GPIO_LP_GPP_B19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_B20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_B21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_B22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_C3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermWpd20K}}, -{GPIO_LP_GPP_C6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_C8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_C23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D9, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_D13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, GpioIntEdge | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntLvlEdgDis | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, - GpioOutLow, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntDis, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, - GpioOutDefault, GpioIntEdge | GpioIntSmi, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, - GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetNormal, - GpioTermNone}}, -{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_E20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_E21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermWpd20K}}, -{GPIO_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, - GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, -{GPIO_LP_GPP_F0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F10, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F11, {GpioPadModeNative2, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, - GpioTolerance1v8 | GpioTermNone}}, -{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep,GpioTermNone}}, -{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_F23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntApic, GpioResetDeep, - GpioTermNone}}, -{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, -{GPIO_LP_GPD0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnAcpi, GpioDirIn, - GpioOutDefault, GpioIntLevel | GpioIntSci, GpioResetPwrGood, - GpioTermNone}}, -{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermWpu20K}}, -{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{GPIO_LP_GPD11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone, - GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}}, -}; -#endif diff --git a/src/mainboard/intel/sklrvp/onboard.h b/src/mainboard/intel/sklrvp/onboard.h deleted file mode 100644 index 10a19b3..0000000 --- a/src/mainboard/intel/sklrvp/onboard.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef ONBOARD_H -#define ONBOARD_H - -/* - * Gpio based irq for touchpad, 18th index in North Bank - * MAX_DIRECT_IRQ + GPSW_SIZE + 19 - */ -#define SKLRVP_TOUCHPAD_IRQ 33 - -#define SKLRVP_TOUCH_IRQ 31 - -#define BOARD_TOUCHPAD_NAME "touchpad" -#define BOARD_TOUCHPAD_IRQ SKLRVP_TOUCHPAD_IRQ -#define BOARD_TOUCHPAD_I2C_BUS 0 -#define BOARD_TOUCHPAD_I2C_ADDR 0x20 - -#define BOARD_TOUCHSCREEN_NAME "touchscreen" -#define BOARD_TOUCHSCREEN_IRQ SKLRVP_TOUCH_IRQ -#define BOARD_TOUCHSCREEN_I2C_BUS 0 -#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4c - -#endif diff --git a/src/mainboard/intel/sklrvp/pei_data.c b/src/mainboard/intel/sklrvp/pei_data.c deleted file mode 100644 index 565947c..0000000 --- a/src/mainboard/intel/sklrvp/pei_data.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> - -void mainboard_fill_pei_data(struct pei_data *pei_data) -{ - - /* DQ byte map for sklrvp board */ - const u8 dq_map[2][12] = { - {0x0F, 0xF0 , 0x00, 0xF0 , 0x0F, 0xF0 , - 0x0F, 0x00 , 0xFF, 0x00 , 0xFF, 0x00}, - {0x33, 0xCC , 0x00, 0xCC , 0x33, 0xCC , - 0x33, 0x00 , 0xFF, 0x00 , 0xFF, 0x00} }; - /* DQS CPU<>DRAM map for sklrvp board */ - const u8 dqs_map[2][8] = { - {0, 1, 3, 2, 4, 5, 6, 7}, - {1, 0, 4, 5, 2, 3, 6, 7} }; - - /* Rcomp resistor*/ - const u16 RcompResistor[3] = {200, 81, 162 }; - - /* Rcomp target*/ - const u16 RcompTarget[5] = {100, 40, 40, 23, 40}; - - pei_data->ec_present = 1; - - memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); - memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); - memcpy(pei_data->RcompResistor, RcompResistor, - sizeof(RcompResistor)); - memcpy(pei_data->RcompTarget, RcompTarget, - sizeof(RcompTarget)); -} diff --git a/src/mainboard/intel/sklrvp/ramstage.c b/src/mainboard/intel/sklrvp/ramstage.c deleted file mode 100644 index 8597e1c..0000000 --- a/src/mainboard/intel/sklrvp/ramstage.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Intel Corporation - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "gpio_rvp3.h" -#include <soc/ramstage.h> - -void mainboard_silicon_init_params(SILICON_INIT_UPD *params) -{ - /*update gpio table*/ - params->GpioTablePtr = (UINT32 *)GpioTableRvp3; -} diff --git a/src/mainboard/intel/sklrvp/romstage.c b/src/mainboard/intel/sklrvp/romstage.c deleted file mode 100644 index 979af43..0000000 --- a/src/mainboard/intel/sklrvp/romstage.c +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <ec/google/chromeec/ec.h> -#include <soc/cpu.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include "spd/spd.h" - -void mainboard_romstage_entry(struct romstage_params *params) -{ - post_code(0x31); - /* Fill out PEI DATA */ - mainboard_fill_pei_data(params->pei_data); - mainboard_fill_spd_data(params->pei_data); - /* Initliaze memory */ - romstage_common(params); -} - -void mainboard_memory_init_params( - struct romstage_params *params, - MEMORY_INIT_UPD *memory_params) -{ - /* Get SPD data passing strucutre and initialize it.*/ - if (params->pei_data->spd_data[0][0][0] != 0) { - memory_params->MemorySpdPtr00 = - (UINT32)(params->pei_data->spd_data[0][0]); - memory_params->MemorySpdPtr10 = - (UINT32)(params->pei_data->spd_data[1][0]); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n", - memory_params->MemorySpdPtr00); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_1\n", - memory_params->MemorySpdPtr01); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n", - memory_params->MemorySpdPtr10); - printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_1\n", - memory_params->MemorySpdPtr11); - } - /* - * Configure the DQ/DQS settings if required. In general the settings - * should be set in the FSP flash image and should not need to be - * changed. - */ - memcpy(memory_params->DqByteMapCh0, params->pei_data->dq_map[0], - sizeof(params->pei_data->dq_map[0])); - memcpy(memory_params->DqByteMapCh1, params->pei_data->dq_map[1], - sizeof(params->pei_data->dq_map[1])); - memcpy(memory_params->DqsMapCpu2DramCh0, params->pei_data->dqs_map[0], - sizeof(params->pei_data->dqs_map[0])); - memcpy(memory_params->DqsMapCpu2DramCh1, params->pei_data->dqs_map[1], - sizeof(params->pei_data->dqs_map[1])); - memcpy(memory_params->RcompResistor, params->pei_data->RcompResistor, - sizeof(params->pei_data->RcompResistor)); - memcpy(memory_params->RcompTarget, params->pei_data->RcompTarget, - sizeof(params->pei_data->RcompTarget)); - - /* update spd length*/ - memory_params->MemorySpdDataLen = SPD_LEN; - memory_params->DqPinsInterleaved = FALSE; -} diff --git a/src/mainboard/intel/sklrvp/spd/Makefile.inc b/src/mainboard/intel/sklrvp/spd/Makefile.inc deleted file mode 100644 index a03a77b..0000000 --- a/src/mainboard/intel/sklrvp/spd/Makefile.inc +++ /dev/null @@ -1,37 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2014 Google Inc. -## Copyright (C) 2015 Intel Corporation. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## - -romstage-y += spd.c - -SPD_BIN = $(obj)/spd.bin - -# SPD data by index. No method for board identification yet -SPD_SOURCES = rvp3 # 0 -SPD_SOURCES += empty # 1 - -SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) - -# Include spd rom data -$(SPD_BIN): $(SPD_DEPS) - for f in $+; \ - do for c in $$(cat $$f | grep -v ^#); \ - do printf $$(printf '\%o' 0x$$c); \ - done; \ - done > $@ - -cbfs-files-y += spd.bin -spd.bin-file := $(SPD_BIN) -spd.bin-type := spd diff --git a/src/mainboard/intel/sklrvp/spd/empty.spd.hex b/src/mainboard/intel/sklrvp/spd/empty.spd.hex deleted file mode 100644 index 9ec39f1..0000000 --- a/src/mainboard/intel/sklrvp/spd/empty.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/sklrvp/spd/rvp3.spd.hex b/src/mainboard/intel/sklrvp/spd/rvp3.spd.hex deleted file mode 100644 index 5291046..0000000 --- a/src/mainboard/intel/sklrvp/spd/rvp3.spd.hex +++ /dev/null @@ -1,16 +0,0 @@ -91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 -78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 -00 00 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 55 00 00 00 00 00 -20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 -20 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/intel/sklrvp/spd/spd.c b/src/mainboard/intel/sklrvp/spd/spd.c deleted file mode 100644 index 9ff45f5..0000000 --- a/src/mainboard/intel/sklrvp/spd/spd.c +++ /dev/null @@ -1,114 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/byteorder.h> -#include <cbfs.h> -#include <console/console.h> -#include <string.h> -#include <soc/gpio.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> -#include <ec/google/chromeec/ec.h> -#include <mainboard/intel/sklrvp/spd/spd.h> - -static void mainboard_print_spd_info(uint8_t spd[]) -{ - const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; - const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; - const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; - const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; - const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; - const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; - char spd_name[SPD_PART_LEN+1] = { 0 }; - - int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; - int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; - int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; - int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; - int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; - int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; - int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; - - /* Module type */ - printk(BIOS_INFO, "SPD: module type is "); - switch (spd[SPD_DRAM_TYPE]) { - case SPD_DRAM_DDR3: - printk(BIOS_INFO, "DDR3\n"); - break; - case SPD_DRAM_LPDDR3: - printk(BIOS_INFO, "LPDDR3\n"); - break; - default: - printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); - break; - } - - /* Module Part Number */ - memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); - spd_name[SPD_PART_LEN] = 0; - printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); - - printk(BIOS_INFO, - "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", - banks, ranks, rows, cols, capmb); - printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", - devw, busw); - - if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { - /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ - printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", - capmb / 8 * busw / devw * ranks); - } -} - -/* Copy SPD data for on-board memory */ -void mainboard_fill_spd_data(struct pei_data *pei_data) -{ - char *spd_file; - size_t spd_file_len; - int spd_index; - - /* Find the SPD data in CBFS. */ - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - die("SPD data not found."); - - /* make sure we have at least one SPD in the file. */ - if (spd_file_len < SPD_LEN) - die("Missing SPD data."); - - /* Add board SKU detection here. Currently we only support one. */ - spd_index = 0; - - /* Make sure we did not overrun the buffer */ - if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - /* Assume same memory in both channels */ - spd_index *= SPD_LEN; - memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); - memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); - - /* Make sure a valid SPD was found */ - if (pei_data->spd_data[0][0][0] == 0) - die("Invalid SPD data."); - - mainboard_print_spd_info(pei_data->spd_data[0][0]); -} diff --git a/src/mainboard/intel/sklrvp/spd/spd.h b/src/mainboard/intel/sklrvp/spd/spd.h deleted file mode 100644 index 301bca5..0000000 --- a/src/mainboard/intel/sklrvp/spd/spd.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MAINBOARD_SPD_H_ -#define _MAINBOARD_SPD_H_ - -#define SPD_LEN 256 - -#define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 -#define SPD_DENSITY_BANKS 4 -#define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 -#define SPD_PART_OFF 128 -#define SPD_PART_LEN 18 - - -#endif /* _MAINBOARD_SPD_H_ */

1 0

New patch to review for coreboot: cbfstool: provide buffer_offset()
by Aaron Durbin 26 Jan '16

26 Jan '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13468 -gerrit commit 756edbbce03212f5c8545e65a65981d2ba29c92a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 26 09:01:14 2016 -0600 cbfstool: provide buffer_offset() Instead of people open coding the offset field access within a struct buffer provide buffer_offset() so that the implementation can change if needed without high touch in the code base. Change-Id: I751c7145687a8529ab549d87e412b7f2d1fb90ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- util/cbfstool/common.h | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/common.h b/util/cbfstool/common.h index 561a17a..42ae1e2 100644 --- a/util/cbfstool/common.h +++ b/util/cbfstool/common.h @@ -62,6 +62,11 @@ static inline size_t buffer_size(const struct buffer *b) return b->size; } +static inline size_t buffer_offset(const struct buffer *b) +{ + return b->offset; +} + /* * Shrink a buffer toward the beginning of its previous space. * Afterward, buffer_delete() remains the means of cleaning it up. */ @@ -125,7 +130,7 @@ static inline void *buffer_get_original_backing(const struct buffer *b) { if (!b) return NULL; - return b->data - b->offset; + return buffer_get(b) - buffer_offset(b); } /* Creates an empty memory buffer with given size.

1 0

New patch to review for coreboot: chromeos: vpd: Avoid reading uninitialized VPDs
by Patrick Georgi 26 Jan '16

26 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13467 -gerrit commit ba8579c1e73a8c307901267e87675b1b1f79f344 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jan 21 11:12:38 2016 -0800 chromeos: vpd: Avoid reading uninitialized VPDs This patch adds a check to the VPD parsing code to avoid reading the whole thing if the first byte ('type' of the first VPD entry) is 0x00 or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types which should never occur as the first entry, so this usually means that the VPD FMAP section has simply never been initialized correctly. This early abort avoids wasting time to read the whole section from SPI flash (which we'd otherwise have to since we're not going to find a Google VPD 2.0 header either). BRANCH=None BUG=None TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to 1.5ms. Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720 Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322897 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index e826d36..d0e2cc1 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -65,11 +65,21 @@ static int32_t get_vpd_size(const char *fmap_name, int32_t *base) } /* Try if we can find a google_vpd_info, otherwise read whole VPD. */ - if (rdev_readat(&vpd, &info, *base, sizeof(info)) == sizeof(info) && - memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) + if (rdev_readat(&vpd, &info, *base, sizeof(info)) != sizeof(info)) { + printk(BIOS_ERR, "ERROR: Failed to read %s header.\n", + fmap_name); + return 0; + } + + if (memcmp(info.header.magic, VPD_INFO_MAGIC, sizeof(info.header.magic)) == 0 && size >= info.size + sizeof(info)) { *base += sizeof(info); size = info.size; + } else if (info.header.tlv.type == VPD_TYPE_TERMINATOR || + info.header.tlv.type == VPD_TYPE_IMPLICIT_TERMINATOR) { + printk(BIOS_WARNING, "WARNING: %s is uninitialized or empty.\n", + fmap_name); + size = 0; } else { size -= GOOGLE_VPD_2_0_OFFSET; }

1 0

Patch set updated for coreboot: chromeos: Add timestamps to measure VPD read times
by Patrick Georgi 26 Jan '16

26 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13139 -gerrit commit cf4c7b9672444af44aa91b5ac1a540eafba73cdc Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jan 20 18:01:15 2016 -0800 chromeos: Add timestamps to measure VPD read times This patch adds three timestamps to coreboot and the cbmem utility that track the time required to read in the Chrome OS Vital Product Data (VPD) blocks (RO and RW). It's useful to account for these like all other large flash accesses, since their size is variable. BRANCH=None BUG=None TEST=Booted Oak, found my weird 100ms gap at the start of ramstage properly accounted for. Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234 Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322831 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/commonlib/include/commonlib/timestamp_serialized.h | 3 +++ src/vendorcode/google/chromeos/cros_vpd.c | 5 +++++ util/cbmem/cbmem.c | 4 ++++ 3 files changed, 12 insertions(+) diff --git a/src/commonlib/include/commonlib/timestamp_serialized.h b/src/commonlib/include/commonlib/timestamp_serialized.h index f7c91c7..6ce0879 100644 --- a/src/commonlib/include/commonlib/timestamp_serialized.h +++ b/src/commonlib/include/commonlib/timestamp_serialized.h @@ -69,6 +69,9 @@ enum timestamp_id { TS_DONE_LOADING = 508, TS_DONE_HASHING = 509, TS_END_HASH_BODY = 510, + TS_START_COPYVPD = 550, + TS_END_COPYVPD_RO = 551, + TS_END_COPYVPD_RW = 552, /* 950+ reserved for vendorcode extensions (950-999: intel/fsp) */ TS_FSP_MEMORY_INIT_START = 950, diff --git a/src/vendorcode/google/chromeos/cros_vpd.c b/src/vendorcode/google/chromeos/cros_vpd.c index 8215454..e826d36 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.c +++ b/src/vendorcode/google/chromeos/cros_vpd.c @@ -10,6 +10,7 @@ #include <fmap.h> #include <stdlib.h> #include <string.h> +#include <timestamp.h> #include "cros_vpd.h" #include "lib_vpd.h" @@ -83,6 +84,8 @@ static void cbmem_add_cros_vpd(int is_recovery) int32_t ro_vpd_base = 0, rw_vpd_base = 0; int32_t ro_vpd_size, rw_vpd_size; + timestamp_add_now(TS_START_COPYVPD); + ro_vpd_size = get_vpd_size("RO_VPD", &ro_vpd_base); rw_vpd_size = get_vpd_size("RW_VPD", &rw_vpd_base); @@ -123,6 +126,7 @@ static void cbmem_add_cros_vpd(int is_recovery) __func__); ro_vpd_size = 0; } + timestamp_add_now(TS_END_COPYVPD_RO); } if (rw_vpd_size) { @@ -143,6 +147,7 @@ static void cbmem_add_cros_vpd(int is_recovery) "%s: Reading RW_VPD FMAP section failed.\n", __func__); } + timestamp_add_now(TS_END_COPYVPD_RW); } } diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index f63c9d4..f58fcf7 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -520,6 +520,10 @@ static const struct timestamp_id_to_name { { TS_DONE_HASHING, "finished calculating body hash (SHA2)" }, { TS_END_HASH_BODY, "finished verifying body signature (RSA)" }, + { TS_START_COPYVPD, "starting to load Chrome OS VPD" }, + { TS_END_COPYVPD_RO, "finished loading Chrome OS VPD (RO)" }, + { TS_END_COPYVPD_RW, "finished loading Chrome OS VPD (RW)" }, + { TS_DC_START, "depthcharge start" }, { TS_RO_PARAMS_INIT, "RO parameter init" }, { TS_RO_VB_INIT, "RO vboot init" },

1 0

Patch merged into coreboot/master: crossgcc: Enable powerpc64-linux target without ppc64-linux headers
by gerrit＠coreboot.org 26 Jan '16

26 Jan '16

the following patch was just integrated into master: commit 0a97d7eeba244b3a18249d07995dcfa884c14920 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 25 09:51:22 2016 +0100 crossgcc: Enable powerpc64-linux target without ppc64-linux headers It may still fail on non-Linux, and the compiler may do fancy things, but it builds. Change-Id: If3456f5fef8d01082a49978dc7cda5450f96f5cc Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13416 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> See https://review.coreboot.org/13416 for details. -gerrit

1 0

Patch set updated for coreboot: intel/skylake: coreboot Cache-as-RAM (CAR) implementation
by Patrick Georgi 26 Jan '16

26 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13138 -gerrit commit d74ed9124e5e55221e73324e6ec2718b2ca63ec9 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 19 19:19:15 2016 +0530 intel/skylake: coreboot Cache-as-RAM (CAR) implementation Now coreboot should do BIOS CAR setup along with NEM mode setup. This patch also provides mechanism to use 16MB code caching benefit although LLC still limited to 1M/1.5M based on SOC LLC limit. Here with unlimited cache line gets replaced. Now we could use unlimited cache size along with well defined data size [pg: updated to current upstream #defines] BUG=chrome-os-partner:48412 BRANCH=glados TEST=Builds and Boots on FAB4 SKU2/3. Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Signed-off-by: pchandri <preetham.chandrian(a)intel.com> Signed-off-by: Dhaval Sharma <dhaval.v.sharma(a)intel.com> Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a Original-Reviewed-on: https://chromium-review.googlesource.com/320855 Original-Commit-Ready: Subrata Banik <subrata.banik(a)intel.com> Original-Tested-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/Kconfig | 8 - src/drivers/intel/fsp1_1/after_raminit.S | 12 +- src/drivers/intel/fsp1_1/cache_as_ram.inc | 19 +- src/soc/intel/skylake/Kconfig | 10 + src/soc/intel/skylake/include/soc/car_setup.S | 340 +++++++++++++++++++++++ src/soc/intel/skylake/include/soc/car_teardown.S | 54 ++++ src/soc/intel/skylake/romstage/romstage.c | 9 + 7 files changed, 435 insertions(+), 17 deletions(-) diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index c959e57..9b2c463 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -23,14 +23,6 @@ if PLATFORM_USES_FSP1_1 comment "Intel FSP 1.1" -config DCACHE_RAM_BASE - hex - default 0xfef00000 - -config DCACHE_RAM_SIZE - hex - default 0x4000 - config HAVE_FSP_BIN bool "Should the Intel FSP binary be added to the flash image" help diff --git a/src/drivers/intel/fsp1_1/after_raminit.S b/src/drivers/intel/fsp1_1/after_raminit.S index 85a0a8c..6fd5ddd 100644 --- a/src/drivers/intel/fsp1_1/after_raminit.S +++ b/src/drivers/intel/fsp1_1/after_raminit.S @@ -20,7 +20,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -.extern fih_car + /* * This is the common entry point after DRAM has been initialized. */ @@ -31,6 +31,14 @@ /* Switch to the stack in RAM */ movl %eax, %esp +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + + /* SOC specific NEM */ + #include <soc/car_teardown.S> + +#else +.extern fih_car + post_code(POST_FSP_TEMP_RAM_EXIT) /* Calculate TempRamExit entry into FSP */ @@ -56,8 +64,8 @@ */ movb $0xBC, %ah jmp .Lhlt - 1: +#endif /* Display the MTRRs */ call soc_display_mtrrs diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.inc b/src/drivers/intel/fsp1_1/cache_as_ram.inc index 35abdb4..6e7e50b 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_1/cache_as_ram.inc @@ -33,17 +33,22 @@ * mm0: low 32-bits of TSC value * mm1: high 32-bits of TSC value */ - - mov %eax, %edi - + movl %eax, %edi cache_as_ram: post_code(0x20) +#if IS_ENABLED(CONFIG_SKIP_FSP_CAR) + /* - * edi: BIST value - * mm0: low 32-bits of TSC value - * mm1: high 32-bits of TSC value + * SOC specific setup + * NOTE: This has to preserve the registers + * mm0, mm1 and edi. */ + #include <soc/car_setup.S> + + post_code(0x28) + +#endif /* * Find the FSP binary in cbfs. @@ -143,7 +148,7 @@ CAR_init_done: rep stosl before_romstage: - post_code(0x23) + post_code(0x2A) /* Call cache_as_ram_main(struct cache_as_ram_params *) */ call cache_as_ram_main diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 58b828f..35b2a18 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -176,4 +176,14 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config DCACHE_RAM_SIZE_TOTAL + hex + default 0x40000 + +config SKIP_FSP_CAR + bool "Skip cache as RAM setup in FSP" + default y + help + Skip Cache as RAM setup in FSP. + endif diff --git a/src/soc/intel/skylake/include/soc/car_setup.S b/src/soc/intel/skylake/include/soc/car_setup.S new file mode 100644 index 0000000..e67a023 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/car_setup.S @@ -0,0 +1,340 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/post_code.h> + +/* + * MTRR definitions + */ +.equ IA32_MTRR_CAP, 0x00fe + +.equ NO_EVICT_MODE, 0x02e0 + +.equ IA32_PQR_ASSOC, 0x0c8f +.equ IA32_L3_MASK_1, 0x0c91 +.equ IA32_L3_MASK_2, 0x0c92 +.equ CACHE_INIT_VALUE, 0 + +/* + * See BWG - chapter "Determining Cacheable Code Region Base Addresses and Ranges". + * + */ + + movl %edi, %ebp /* Put BIST value in a safe place */ + /* + * Ensure that all variable-range MTRR valid flags are clear and + * IA32_MTRR_DEF_TYPE MSR E flag is clear. Note: This is the default state + * after hardware reset. + * + * Initialize all fixed-range and variable-range MTRR register fields to 0. + */ + mov $(MtrrByteCountFixed), %ebx /* EBX = size of Fixed MTRRs */ + + xorl %eax, %eax /* Clear the low dword to write */ + xorl %edx, %edx /* Clear the high dword to write */ + xorl %ecx, %ecx + /* Clearing Fixed Range MTRRs */ +clear_mtrr_fixed: + addl $(-2), %ebx /* need to check it */ + movw (MtrrInitTable)(%ebx), %cx /* cx <- address of mtrr to zero */ + wrmsr + jnz clear_mtrr_fixed /* loop through the whole table */ + + post_code(0x21) + + /* Clearing Variable Range MTRRs */ + movl $MTRR_CAP_MSR, %ecx + rdmsr + movzx %al, %ebx + clr %eax + clr %edx + movl $MTRR_PHYS_BASE(0), %ecx +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(0x22) + + /* + * Configure the default memory type to un-cacheable (UC) in the + * IA32_MTRR_DEF_TYPE MSR. + */ + + movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */ + rdmsr + andl $0xFFFFF300, %eax /* Clear the enable bits and def type UC. */ + wrmsr + + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + /* + * Configure the DataStack region as write-back (WB) cacheable memory type + * using the variable range MTRRs. + * + * + * Set the base address of the DataStack cache range + */ + + movl $CONFIG_DCACHE_RAM_BASE, %eax + orl $MTRR_TYPE_WRBACK, %eax /* Load the write-back cache value */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(0), %ecx /* Load the MTRR index */ + wrmsr /* the value in MTRR_PHYS_BASE_0 */ + + /* + * Set the mask for the DataStack cache range + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %eax + dec %eax + not %eax + orl $MTRR_PHYS_MASK_VALID, %eax /* turn on the Valid flag */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + inc %ecx + wrmsr /* the value in MTRR_PHYS_MASK_0 */ + + post_code(0x23) + + /* + * Enable the MTRRs by setting the IA32_MTRR_DEF_TYPE MSR E flag. + */ + movl $MTRR_DEF_TYPE_MSR, %ecx /* Load the MTRR default type index */ + rdmsr + orl $MTRR_DEF_TYPE_EN, %eax /* Enable variable range MTRRs */ + wrmsr + + post_code(0x24) + + /* + * Enable the logical processor's (BSP) cache: execute INVD and set + * CR0.CD = 0, CR0.NW = 0. + */ + movl %cr0, %eax + and $(~(CR0_CD + CR0_NW)), %eax + invd + movl %eax, %cr0 + + /* + * Enable No-Eviction Mode Setup State by setting + * NO_EVICT_MODE MSR 2E0h bit [0] = '1'. + */ + movl $NO_EVICT_MODE, %ecx + rdmsr + orl $0x01, %eax + wrmsr + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +Find_LLC_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz Find_LLC_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence created Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * +----------------+-------+----------+ + * | LLC Ways | LLC_WAY_MASK_1 | + * +----------------+-------+-------+--+ + * |4 | 0x000E | + * |8 | 0x00FE | + * |12 | 0x0FFE | + * |16 | 0xFFFE | + * +----------------+-------+---------- + + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set IA32_PQR_ASSOC = 0x02 + * + * +----------------+-------+----------------------------------+ + * | IA32_PQR_ASSOC | Values | + * +----------------+-------+-------+--------------------------+ + * |0 | Default value, no way mask should be applied| + * |1 | Apply way mask 1 to LLC | + * |2 | Apply way mask 2 to LLC | + * |3 | Shouldn't be use in NEM Mode | + *+----------------+-------+------------------------------------------+ + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE_TOTAL, %ecx + shr $0x02, %ecx + movl $CACHE_INIT_VALUE, %eax + cld + rep stosl + /* + * Set IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $NO_EVICT_MODE, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x25) + /* + * Configure the BIOS code region as write-protected (WP) cacheable + * memory type using a single variable range MTRR. + * + * Ensure region to cache meets MTRR requirements for + * size and alignment. + */ + movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ + movl $CONFIG_ROM_SIZE, %eax /* Code region size */ + cmpl $0, %edi + jz InvalidParameter + cmpl $0, %eax + jz InvalidParameter + jmp CheckPass + +InvalidParameter: + movl $0x80000002, %eax /* RETURN_INVALID_PARAMETER */ + jmp .Lhlt + +CheckPass: + + post_code(0x26) + + /* + * Program base register + */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ + movl %edi, %eax + orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ + wrmsr + + movl $CONFIG_ROM_SIZE, %eax + + /* + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + dec %eax /* eax - size to cache less one byte */ + not %eax /* eax contains low 32 bits of mask */ + or $MTRR_PHYS_MASK_VALID, %eax + /* + * Program mask register + */ + movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + + post_code(0x27) + + /* + * edi: BIST value + * mm0: low 32-bits of TSC value + * mm1: high 32-bits of TSC value + */ + movl %ebp, %edi /* Restore BIST value */ + + .section .rodata + +MtrrInitTable: + .word MTRR_DEF_TYPE_MSR + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 + +.equ MtrrByteCountFixed, (.-MtrrInitTable) + + .previous diff --git a/src/soc/intel/skylake/include/soc/car_teardown.S b/src/soc/intel/skylake/include/soc/car_teardown.S new file mode 100644 index 0000000..315b3c1 --- /dev/null +++ b/src/soc/intel/skylake/include/soc/car_teardown.S @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +.equ IA32_PQR_ASSOC, 0x0c8f + + /* Disable MTRR by clearing the IA32_MTRR_DEF_TYPE MSR E flag. */ + movl $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + andl $(~MTRR_DEF_TYPE_EN), %eax + wrmsr + + /* Invalidate Cache */ + invd + + /* + * Disable No-Eviction Mode Run State by clearing + * NO_EVICT_MODE MSR 2E0h bit [1] = 0 + */ + movl $0x000002E0, %ecx + rdmsr + andl $~(0x2), %eax + wrmsr + + /* + * Disable No-Eviction Mode Setup State by clearing + * NO_EVICT_MODE MSR 2E0h bit [0] = 0 + */ + rdmsr + andl $~(0x1), %eax + wrmsr + + /* + * Set IA32_PQR_ASSOC = 0x00 + * This step guarantees that no protected way remain in LLC cache, + * all the ways are open for the evictions. + */ + movl $IA32_PQR_ASSOC, %ecx + movl $0x00, %eax + xorl %edx, %edx + wrmsr diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index b872d39..f99f05d 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -96,6 +96,10 @@ void soc_memory_init_params(struct romstage_params *params, upd->SaGv = config->SaGv; upd->RMT = config->Rmt; upd->DdrFreqLimit = config->DdrFreqLimit; + if (IS_ENABLED(CONFIG_SKIP_FSP_CAR)) { + upd->FspCarBase = CONFIG_DCACHE_RAM_BASE; + upd->FspCarSize = CONFIG_DCACHE_RAM_SIZE_TOTAL; + } } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -232,6 +236,11 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, new->ApertureSize); fsp_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); fsp_display_upd_value("RMT", 1, old->RMT, new->RMT); + fsp_display_upd_value("FspCarBase", 1, old->FspCarBase, + new->FspCarBase); + fsp_display_upd_value("FspCarSize", 1, old->FspCarSize, + new->FspCarSize); + } /* SOC initialization after RAM is enabled. */

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Patch set updated for coreboot: mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDT
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13453 -gerrit commit 9ba21041885eee6c2f281c0226f4759afa8a01c4 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:57:17 2016 +1100 mb/intel/d510mo: Add CPU, SMI-trap and PIC to DSDT Change-Id: I80853cadb4762d9bb34926e31d65d248c5683417 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/acpi/platform.asl | 28 ++++++++++++++++++++++++++++ src/mainboard/intel/d510mo/dsdt.asl | 5 ++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/d510mo/acpi/platform.asl b/src/mainboard/intel/d510mo/acpi/platform.asl new file mode 100644 index 0000000..6c92a4e --- /dev/null +++ b/src/mainboard/intel/d510mo/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/intel/d510mo/dsdt.asl b/src/mainboard/intel/d510mo/dsdt.asl index c1f72f9..a7788bd 100644 --- a/src/mainboard/intel/d510mo/dsdt.asl +++ b/src/mainboard/intel/d510mo/dsdt.asl @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2007-2009 coresystems GmbH - * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as @@ -23,8 +23,11 @@ DefinitionBlock( 0x20090419 // OEM revision ) { + #include "acpi/platform.asl" #include <southbridge/intel/i82801gx/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) {

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Patch set updated for coreboot: mb/intel/d510mo: Add missing GPIO and GPEN
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13452 -gerrit commit 694788cabccfe459ca793b2afc0a8f4a951c103a Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 13:52:33 2016 +1100 mb/intel/d510mo: Add missing GPIO and GPEN Change-Id: I56c0a55d57d8beabcb33cf1984b037556a71a8b9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 1 + src/mainboard/intel/d510mo/romstage.c | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index 221cc54..c6f39a0 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -36,6 +36,7 @@ chip northbridge/intel/pineview # Northbridge register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ahci" = "0x0" + register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c index b0bd0c0..6b4f0f6 100644 --- a/src/mainboard/intel/d510mo/romstage.c +++ b/src/mainboard/intel/d510mo/romstage.c @@ -50,6 +50,7 @@ static void mb_gpio_init(void) outl(0x1ff9f7c1, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ outl(0xe0e9e803, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ outl(0xece9e842, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ + outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ outl(0x00002000, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ outl(0x000000fe, DEFAULT_GPIOBASE + 0x30); outl(0x0000007e, DEFAULT_GPIOBASE + 0x34);

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Patch set updated for coreboot: mb/intel/d510mo: Explicitly select NIC on PCI in devicetree
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13455 -gerrit commit f29578d4dd359051cf91a6b478eb68be47819ebd Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:06:26 2016 +1100 mb/intel/d510mo: Explicitly select NIC on PCI in devicetree Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index c0f38de..3cfcf5f 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -43,7 +43,10 @@ chip northbridge/intel/pineview # Northbridge register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio - device pci 1c.0 on end # PCIe 1 + device pci 1c.0 on # PCIe 1 + device pci 0.0 on # NIC + end + end device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4

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Patch set updated for coreboot: mb/intel/d510mo: Use SATA AHCI by default
by Damien Zammit 25 Jan '16

25 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13454 -gerrit commit 96c4d6176cb89c48b9dbfe5c6e343a50bd045d9a Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 14:03:37 2016 +1100 mb/intel/d510mo: Use SATA AHCI by default Change-Id: I6f9772c5bcf9a50dfbc3d1cfaeb79f4454d1fb27 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/intel/d510mo/devicetree.cb | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index df5a0f9..c0f38de 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -38,10 +38,8 @@ chip northbridge/intel/pineview # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x1" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" - register "sata_ahci" = "0x0" + register "sata_ahci" = "0x1" + register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x20000040" device pci 1b.0 on end # Audio

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coreboot-gerrit January 2016