coreboot-gerrit January 2016

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Patch set updated for coreboot: drivers/intel/fsp2_0: Implement FSP memory init wrapper
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13337 -gerrit commit 7d6dab8a4e4c6d7d53cf1cda20c67981284f0d8c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Oct 29 13:00:54 2015 -0700 drivers/intel/fsp2_0: Implement FSP memory init wrapper Change-Id: I7926696a74ccf9cd01898cdf502d16c93785649a Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 4 ++ src/drivers/intel/fsp2_0/Makefile.inc | 1 + src/drivers/intel/fsp2_0/memory_init.c | 127 +++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index a029965..0103921 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -27,6 +27,10 @@ config FSP_S_FILE endif # ADD_FSP_BINARIES +config FIT_CAR_ADDR + hex + default 0xfef27c00 + # Cache As RAM region layout: # # +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xfef80000] diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index b6cb7cd..763b46d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -1,5 +1,6 @@ romstage-y += util.c +romstage-y += memory_init.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c new file mode 100644 index 0000000..c05c286 --- /dev/null +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <cbmem.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> +#include <timestamp.h> + +#define FIT_POINTER (0x100000000ULL - 0x40) +#define FIT_SIZE 0x400 + +struct fsp_memory_init_params { + void *nvs_buffer; + void *rt_buffer; + void **hob_list; +} __attribute__ ((__packed__)); + +struct fsp_init_rt_common_buffer { + void *stack_top; + uint32_t boot_mode; + void *upd_data_rgn; + uint32_t bootloader_tolum_size; +} __attribute__ ((__packed__)); + +typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) + (struct fsp_memory_init_params *); + +static void fill_console_params(struct MEMORY_INIT_UPD *memupd) +{ + /* TODO: Check that FSP actually respects these flags */ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + memupd->SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + memupd->SerialDebugPortType = 2; + memupd->SerialDebugPortStrideSize = 2; + memupd->SerialDebugPortAddress = 0; + } else { + memupd->SerialDebugPortType = 0; + } +} + +__attribute__((weak)) +void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s called\n", __func__); +} + +static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr) +{ + enum fsp_status status; + fsp_memory_init_fn fsp_raminit; + struct fsp_memory_init_params raminit_params; + struct fsp_init_rt_common_buffer rt_buffer; + void *hob_list_ptr; + struct MEMORY_INIT_UPD raminit_upd; + struct UPD_DATA_REGION *upd_region; + + post_code(0x34); + upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base); + memcpy(&raminit_upd, upd_region, sizeof(raminit_upd)); + + /* Zero fill RT Buffer data and start populating fields. */ + memset(&rt_buffer, 0, sizeof(rt_buffer)); + + rt_buffer.upd_data_rgn = &raminit_upd; + rt_buffer.bootloader_tolum_size = cbmem_overhead_size(); + + /* Get any board specific changes */ + raminit_params.nvs_buffer = NULL; + raminit_params.rt_buffer = &rt_buffer; + raminit_params.hob_list = &hob_list_ptr; + + /* Update the UPD data */ + raminit_upd.GpioPadInitTablePtr = NULL; + fill_console_params(&raminit_upd); + platform_fsp_memory_init_params_cb(&raminit_upd); + + /* Call FspMemoryInit */ + fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); + printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); + printk(BIOS_SPEW, "\t%p: rt_buffer\n", raminit_params.rt_buffer); + printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list); + + timestamp_add_now(TS_FSP_MEMORY_INIT_START); + status = fsp_raminit(&raminit_params); + post_code(0x37); + timestamp_add_now(TS_FSP_MEMORY_INIT_END); + + printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status); + + return status; +} + +/* + * Relocate FIT table to FSP-M's stack/data space + * + * FSP-M expects to find FIT entries at some address hardcoded in FSP. + */ +static void relocate_fit(void) +{ + uint32_t fit_loc = read32((void *)FIT_POINTER); + memcpy((void*)CONFIG_FIT_CAR_ADDR, (void*)fit_loc, FIT_SIZE); +} + +enum fsp_status fsp_memory_init(void) +{ + struct fsp_header hdr; + + if (fsp_load_binary(&hdr, "blobs/fsp-m.bin") != CB_SUCCESS) + return FSP_NOT_FOUND; + relocate_fit(); + return do_fsp_memory_init(&hdr); +}

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Patch set updated for coreboot: driver/intel/fsp2_0: Add utility to load an FSP binary to memory
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13336 -gerrit commit f692aecc92c94a6ec34aa65d68a73eac6a816279 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Nov 3 16:54:43 2015 -0800 driver/intel/fsp2_0: Add utility to load an FSP binary to memory Since FSP 2.0 is split into several binaries, implement a common function to load such binaries into memory. Change-Id: Id4a9024163034d8f53eff6fa2f28a7078d690bdc Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/util.h | 21 ++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 34 ++++++++++++++++++++++++++++- 2 files changed, 54 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h new file mode 100644 index 0000000..abdbcf0 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_UTIL_H_ +#define _FSP2_0_UTIL_H_ + +#include <fsp/info_header.h> + +/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */ +enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name); + +#endif /* _FSP2_0_UTIL_H_ */ diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index e1b77a8..405021b 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -11,8 +12,9 @@ */ #include <arch/io.h> +#include <cbfs.h> #include <console/console.h> -#include <fsp/info_header.h> +#include <fsp/util.h> #include <lib.h> #include <string.h> @@ -68,3 +70,33 @@ void fsp_print_header_info(const struct fsp_header *hdr) hdr->silicon_init_entry_offset, hdr->notify_phase_entry_offset); } + +enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name) +{ + struct cbfsf file_desc; + struct region_device file_data; + size_t fsp_load_size; + void *membase; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); + return CB_ERR; + } + + cbfs_file_data(&file_data, &file_desc); + + /* Map just enough of the file to be able to parse the header. */ + membase = rdev_mmap(&file_data, 0, FSP_HDR_OFFSET + FSP_HDR_LEN); + if (fsp_identify(hdr, membase) != CB_SUCCESS) { + printk(BIOS_ERR, "%s did not have a valid FSP header\n", name); + return CB_ERR; + } + + fsp_print_header_info(hdr); + + /* Load binary into memory. */ + fsp_load_size = MIN(hdr->image_size, file_data.region.size); + rdev_readat(&file_data, (void *)hdr->image_base, 0, fsp_load_size); + + return CB_SUCCESS; +}

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Patch set updated for coreboot: soc/apollolake/Kconfig: Enable using FSP 2.0
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13339 -gerrit commit 14b7d17aa5ce5a0c9fd68465c421610791d5f431 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Oct 27 16:28:16 2015 -0700 soc/apollolake/Kconfig: Enable using FSP 2.0 Change-Id: I1bba55c16c2899516c036907946a4db2b1672f31 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 317a439..8bc7ad4 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -35,6 +35,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON select UDELAY_TSC select TSC_CONSTANT_RATE + select PLATFORM_USES_FSP2_0 config X86_TOP4G_BOOTMEDIA_MAP bool

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Patch set updated for coreboot: drivers/intel/fsp2_0: Include stddef.h before FspUpdVpd.h
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13338 -gerrit commit cba02167b4673845d53505ea186fc196bb2964b9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 4 12:00:24 2015 -0800 drivers/intel/fsp2_0: Include stddef.h before FspUpdVpd.h The semantically patched FspUpdVpd.h requires the definition of wchar_t, which is provided by stddef.h. Change-Id: I1093a6ac48e0a616ca86b8109da929dabe9554c5 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 75dcffe..e51b854 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -13,6 +13,7 @@ #ifndef _FSP2_0_API_H_ #define _FSP2_0_API_H_ +#include <stddef.h> #include "FspUpdVpd.h" enum fsp_status {

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Patch set updated for coreboot: intel/strago: Fix GPIO config
by Hannah Williams 26 Jan '16

26 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13431 -gerrit commit 279c1bbb30feca75d1ab0897e4ff72caf6828129 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Fix GPIO config Fix GPIO config for this board: - SD card detect to GPI - SATA GPI to not used - GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination - I2C4 SDA and SCL from not used to Native Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 8b6a0e7..ab8c120 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,7 +74,9 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ + GPI(trig_edge_both, L1, P_20K_H, non_maskable, + en_edge_detect, NA , NA), + /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */ SPARE_PIN,/* 84 spare pin */ @@ -112,11 +114,11 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), /* 37 MF_HDA_DOCKENB */ NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ + NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ + NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ GPIO_NC, /* 52 I2C_NFC_SCL */ NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ @@ -128,7 +130,7 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), + GPIO_NC, /* 76 GPI SATA_GP1 */ Native_M1, /* 77 SATA_LEDN */ GPIO_NC, /* 80 SATA_GP3 */ @@ -169,9 +171,11 @@ static const struct soc_gpio_map gpn_gpio_map[] = { /* 17 GPIO_SUS3 */ GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 18 GPIO_SUS7 */ - GPO_FUNC(0, 0), /* 19 GPIO_SUS1 */ + GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), + /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, NA, non_maskable, en_edge_rx_data, NA , NA), + GPI(trig_edge_high, L2, P_20K_H, non_maskable, + en_edge_rx_data, NA , NA), /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC,

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Patch merged into coreboot/master: xcompile: fill in power8 64bit LE
by gerrit＠coreboot.org 26 Jan '16

26 Jan '16

the following patch was just integrated into master: commit d6577e1cb89ba3b04eab2804627343bbad175a72 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 25 18:16:14 2016 +0100 xcompile: fill in power8 64bit LE Change-Id: Id0316042f665ec9c095887cf6a37a7949ed8e861 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13421 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13421 for details. -gerrit

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Patch merged into coreboot/master: xcompile: also look for *-linux compiler triplet
by gerrit＠coreboot.org 26 Jan '16

26 Jan '16

the following patch was just integrated into master: commit a1a6f7535b004de71e894946321b9c1b1d34e57d Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 25 18:15:45 2016 +0100 xcompile: also look for *-linux compiler triplet Not just *-linux-gnu. Change-Id: Ib817c6d207d3b69ce7595505f2b45f3be35b7d2f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13420 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13420 for details. -gerrit

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Patch merged into coreboot/master: xcompile: document all the variables!
by gerrit＠coreboot.org 26 Jan '16

26 Jan '16

the following patch was just integrated into master: commit 74c86456af23171457464766e3f1072bf5dca490 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Mon Jan 25 18:15:08 2016 +0100 xcompile: document all the variables! What's the exact difference between TARCH, TSUPP and TBFDARCHS? Fear no more, it's documented. Change-Id: I18717eb1e20b1c0a82a485d391de2794a77c59ae Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Reviewed-on: https://review.coreboot.org/13419 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13419 for details. -gerrit

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Patch set updated for coreboot: drivers/intel/fsp2_0: Add initial FspUpdVpd.h header
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13332 -gerrit commit 1e5608bb317aa0e342d2c556f4a2a96ae0bb8ee2 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 2 13:40:06 2015 -0800 drivers/intel/fsp2_0: Add initial FspUpdVpd.h header This is the header which defines the parameter interfaceof the FSP blob. Since thi is specific to the FSP blob, and is subject to change, it is added in a separate commit. Change-Id: I7b7bb77817ec0e757a569f90d0248d50df5e34c8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 447 +++++++++++++++++++++++ 1 file changed, 447 insertions(+) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h new file mode 100644 index 0000000..bdd5999 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -0,0 +1,447 @@ +/** @file + +Copyright (c) 2015, Intel Corporation. All rights reserved.<BR> + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPUPDVPD_H__ +#define __FSPUPDVPD_H__ + +#define MAX_CHANNELS_NUM 2 +#define MAX_DIMMS_NUM 2 + +struct DIMM_INFO { + uint8_t DimmId; + uint32_t SizeInMb; +} __attribute__((packed)); + +struct CHANNEL_INFO { + uint8_t ChannelId; + uint8_t DimmCount; + struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; +} __attribute__((packed)); + +struct FSP_SMBIOS_MEMORY_INFO { + uint8_t Revision; + uint16_t DataWidth; + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + uint8_t MemoryType; + uint16_t MemoryFrequencyInMHz; + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + uint8_t ErrorCorrectionType; + uint8_t ChannelCount; + struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; +} __attribute__((packed)); + +typedef union{ + uint32_t padCnf0; + struct { + uint32_t GPIOTxState:1; ///< 0 GPIO TX State + uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO + uint32_t Reserved1:6; ///< 2-7 Reserved, RO + uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] + uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. + uint32_t Reserved2:4; ///< 13-16 Reserved, RO + uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] + uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO + uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion + uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT + uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge + uint32_t Reserved3:1; ///< 27 RO + uint32_t RXRAW1:1; ///< 28 Override the RX to 1 + uint32_t RXPadStSel:1; ///< 29 RX Pad State Select + uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config + } r; +} BL_CONF_PAD0; + +typedef union{ + uint32_t padCnf1; + struct { + uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO + uint32_t Reserved:1; ///< 7 Reserved. + uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW + uint32_t Term:4; ///< 10-13 Termination, + ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; + ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination + uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW + uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO + } r; +} BL_CONF_PAD1; + +struct BL_GPIO_PAD_INIT { + BL_CONF_PAD0 padConfg0; + BL_CONF_PAD1 padConfg1; + uint8_t Community; + uint16_t MMIO_ADDRESS; + bool HostSw; + bool WakeEnabled; ///< Wake enable for direct IRQ pin + wchar_t *pad_name; ///< GPIO Pin Name for debug purpose +} __attribute__((packed)); + + + +struct TEMP_RAM_INIT_UPD { +/** Offset 0x0020 +**/ + uint64_t Signature; +/** Offset 0x0028 +**/ + uint8_t Revision; +/** Offset 0x0029 +**/ + uint8_t UnusedUpdSpace0[83]; +/** Offset 0x007C +**/ + uint32_t ReservedTempRamInitUpd; +} __attribute__((packed)); + +struct MEMORY_INIT_UPD { +/** Offset 0x0080 +**/ + uint64_t Signature; +/** Offset 0x0088 +**/ + uint8_t Revision; +/** Offset 0x0089 +**/ + uint8_t UnusedUpdSpace1[7]; +/** Offset 0x0090 + Debug Serial Port Base + Debug serial port resource base address, either I/O or MMIO base. +**/ + uint32_t SerialDebugPortAddress; +/** Offset 0x0094 + Debug Serial Port Type + Debug serial port resource type. NONE means no serial port support. +**/ + uint8_t SerialDebugPortType; +/** Offset 0x0095 + Serial Port Debug Device + Select active serial port device. For SOC UART devices,'Debug Serial Port Base' options will be ignored. +**/ + uint8_t SerialDebugPortDevice; +/** Offset 0x0096 + Debug Serial Port Stride Size + Debug serial port register map stride size. +**/ + uint8_t SerialDebugPortStrideSize; +/** Offset 0x0097 +**/ + uint8_t ReservedUpd1; +/** Offset 0x0098 + Memory FastBootSupport + MRC Fast Boot Support +**/ + uint8_t MrcFastBoot; +/** Offset 0x0099 +**/ + uint8_t UnusedUpdSpace2[7]; +/** Offset 0x00A0 + Memory EccSupport + ECC Support +**/ + uint8_t EccSupport; +/** Offset 0x00A1 + Memory DdrFreqLimit + DDR Freq Limit +**/ + uint8_t DdrFreqLimit; +/** Offset 0x00A2 + Memory MaxTolud + MaxTolud +**/ + uint32_t MaxTolud; +/** Offset 0x00A6 + MrcDebugMsgLevel + Set MRC DebugMsg Level +**/ + uint8_t MrcDebugMsgLevel; +/** Offset 0x00A7 + Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Alwarys disable IGD +**/ + uint8_t Igd; +/** Offset 0x00A8 + DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device +**/ + uint8_t IgdDvmt50PreAlloc; +/** Offset 0x00A9 + Aperture Size + Select the Aperture Size. +**/ + uint8_t IgdApertureSize; +/** Offset 0x00AA + GTT Size + Select the GTT Size. +**/ + uint8_t GTTSize; +/** Offset 0x00AB + Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. +**/ + uint8_t PrimaryVideoAdaptor; +/** Offset 0x00AC +**/ + uint8_t PmSupport; +/** Offset 0x00AD +**/ + uint8_t EnableRenderStandby; +/** Offset 0x00AE +**/ + uint8_t PavpEnable; +/** Offset 0x00AF +**/ + uint8_t SataEnable; +/** Offset 0x00B0 + Enable SATA + Enable/disable SATA controller. +**/ + uint8_t EnableSata; +/** Offset 0x00B1 + SATA Mode + Select SATA controller working mode. +**/ + uint8_t SataMode; +/** Offset 0x00B2 + Enable SATA + Enable/disable SATA controller. +**/ + uint8_t SataSalpSupport; +/** Offset 0x00B3 + Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsEnable[2]; +/** Offset 0x00B5 + Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[2]; +/** Offset 0x00B7 + Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpEnable[6]; +/** Offset 0x00BD + Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[6]; +/** Offset 0x00C3 + Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb20Enable[8]; +/** Offset 0x00CB + Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb30Enable[6]; +/** Offset 0x00D1 + Enable XHCI SSIC Eanble + Enable/disable XHCI SSIC port. +**/ + uint8_t SsicPortEnable; +/** Offset 0x00D2 + Enable SMBus + Enable/disable SMBus controller. +**/ + uint8_t SmbusEnable; +/** Offset 0x00D3 +**/ + uint8_t UnusedUpdSpace3[13]; +/** Offset 0x00E0 +**/ + uint8_t IspEn; +/** Offset 0x00E1 +**/ + uint8_t IspAcpiMode; +/** Offset 0x00E2 +**/ + uint32_t AdditionalFvBase; +/** Offset 0x00E6 +**/ + uint8_t UnusedUpdSpace4[122]; +/** Offset 0x0160 +**/ + uint32_t ObbLoadingBase; +/** Offset 0x0164 +**/ + uint32_t ObbFlashBase; +/** Offset 0x0168 +**/ + uint32_t ObbFlashSize; +/** Offset 0x016C +**/ + uint8_t UnusedUpdSpace5[20]; +/** Offset 0x0180 +**/ + uint8_t ObbFileName[16]; +/** Offset 0x0190 +**/ + uint8_t UnusedUpdSpace6[48]; +/** Offset 0x01C0 +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; +/** Offset 0x01C4 +**/ + uint8_t UnusedUpdSpace7[56]; +/** Offset 0x01FC +**/ + uint32_t ReservedMemoryInitUpd; +} __attribute__((packed)); + +struct SILICON_INIT_UPD { +/** Offset 0x0200 +**/ + uint64_t Signature; +/** Offset 0x0208 +**/ + uint8_t Revision; +/** Offset 0x0209 +**/ + uint8_t UnusedUpdSpace8[7]; +/** Offset 0x0210 + Logo Pointer + Points to PEI Display Logo Image +**/ + uint32_t LogoPtr; +/** Offset 0x0214 + Logo Size + Size of PEI Display Logo Image +**/ + uint32_t LogoSize; +/** Offset 0x0218 + Graphics Configuration Ptr + Points to VBT +**/ + uint32_t GraphicsConfigPtr; +/** Offset 0x021C + Enable HD Audio DSP + Enable/disable HD Audio DSP feature. +**/ + uint8_t DspEnable; +/** Offset 0x021D + Select HDAudio IoBuffer Ownership + Select HDAudio IoBuffer Ownership. +**/ + uint8_t IoBufferOwnership; +/** Offset 0x021E + BXT PlatformType + BXT PlatformType. +**/ + uint8_t PlatformType; +/** Offset 0x021F + DynSR + Enable/disable DynSR feature. +**/ + uint8_t DynSR; +/** Offset 0x0220 +**/ + uint8_t UnusedUpdSpace9[20]; +/** Offset 0x0234 +**/ + uint8_t ReservedSiliconInitUpd[292]; +} __attribute__((packed)); + +#define FSP_UPD_SIGNATURE 0x2444505554584224 /* '$BXTUPD$' */ +#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x24445055504D5424 /* '$TMPUPD$' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ + +struct UPD_DATA_REGION { +/** Offset 0x0000 +**/ + uint64_t Signature; +/** Offset 0x0008 +**/ + uint8_t Revision; +/** Offset 0x0009 +**/ + uint8_t ReservedUpd0[7]; +/** Offset 0x0010 +**/ + uint32_t TempRamInitUpdOffset; +/** Offset 0x0014 +**/ + uint32_t MemoryInitUpdOffset; +/** Offset 0x0018 +**/ + uint32_t SiliconInitUpdOffset; +/** Offset 0x001C +**/ + uint32_t ReservedUpd1; +/** Offset 0x0020 +**/ + struct TEMP_RAM_INIT_UPD TempRamInitUpd; +/** Offset 0x0080 +**/ + struct MEMORY_INIT_UPD MemoryInitUpd; +/** Offset 0x0200 +**/ + struct SILICON_INIT_UPD SiliconInitUpd; +/** Offset 0x0358 +**/ + uint8_t UnusedUpdSpace10[166]; +/** Offset 0x03FE +**/ + uint16_t RegionTerminator; +} __attribute__((packed)); + +#define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ +#define FSP_IMAGE_REV 0x01010000 + +struct VPD_DATA_REGION { +/** Offset 0x0000 +**/ + uint64_t PcdVpdRegionSign; +/** Offset 0x0008 + PcdImageRevision +**/ + uint32_t PcdImageRevision; +/** Offset 0x000C +**/ + uint32_t PcdUpdRegionOffset; +/** Offset 0x0010 +**/ + uint32_t PcdUpdRegionSize; +/** Offset 0x0014 +**/ + uint64_t UnusedVpdSpace0; +/** Offset 0x001C +**/ + uint32_t PcdVpdReserved; +} __attribute__((packed)); + +#endif

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Patch set updated for coreboot: soc/apollolake: Add cbmem_top() implementation
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13329 -gerrit commit c847af56f55393f94f40c45da81455fb3b00ecf6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Nov 2 13:47:43 2015 -0800 soc/apollolake: Add cbmem_top() implementation Change-Id: Ibae9f43192f0e498e91ff8a51bd7d1e9a5b31350 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ src/soc/intel/apollolake/memmap.c | 27 +++++++++++++++++++++++++++ src/soc/intel/apollolake/placeholders.c | 5 ----- 3 files changed, 29 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index e57342a..7cddf5a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,12 +18,14 @@ bootblock-y += uart_early.c cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += cpu.c romstage-y += gpio.c +romstage-y += memmap.c romstage-y += mmap_boot.c romstage-y += romstage/romstage.c romstage-y += uart_early.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += uart.c diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c new file mode 100644 index 0000000..7de6217 --- /dev/null +++ b/src/soc/intel/apollolake/memmap.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define TSEG 0xb8 + +#define __SIMPLE_DEVICE__ +#include <arch/io.h> +#include <cbmem.h> + +static uintptr_t smm_region_start(void) +{ + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & (~1); +} + +void *cbmem_top(void) +{ + return (void *)smm_region_start(); +} diff --git a/src/soc/intel/apollolake/placeholders.c b/src/soc/intel/apollolake/placeholders.c index cf0fe36..fc62d80 100644 --- a/src/soc/intel/apollolake/placeholders.c +++ b/src/soc/intel/apollolake/placeholders.c @@ -1,11 +1,6 @@ #include <cbmem.h> #include <cpu/x86/smm.h> -void *cbmem_top(void) -{ - return NULL; -} - void southbridge_smi_set_eos(void) { }

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coreboot-gerrit January 2016