coreboot-gerrit January 2016

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Patch set updated for coreboot: drivers/fsp2_0: Implements FspNotify API
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13358 -gerrit commit 06e95259c4074053357e4001be54e838b1ccc864 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 6 17:26:20 2015 -0800 drivers/fsp2_0: Implements FspNotify API This adds FspNotify implementation. Please note, FSP blobset assumes FspNotify is called after SiliconInit. As result, this implementation relies on this fact and assumes SiliconInit is called first. Change-Id: I75ede529403d54b78caeca0517e139c3d81090e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + src/drivers/intel/fsp2_0/include/fsp/api.h | 8 +++++- src/drivers/intel/fsp2_0/notify.c | 41 ++++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/silicon_init.c | 6 ++++- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index e7081a7..adb5a7d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += hand_off_block.c romstage-y += util.c romstage-y += memory_init.c +ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-y += util.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index f51174f..6d2efd8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -32,10 +32,16 @@ enum fsp_status { FSP_CRC_ERROR = 0x8000001b, }; +enum fsp_notify_phase { + AFTER_PCI_ENUM = 0x20, + READY_TO_BOOT = 0x40 +}; + + /* Main FSP stages */ enum fsp_status fsp_memory_init(void **hob_list); enum fsp_status fsp_silicon_init(void); -enum fsp_status fsp_notify(void); +enum fsp_status fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..6148bc4 --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +typedef struct fsp_notify_params { + enum fsp_notify_phase phase; +} NOTIFY_PHASE_PARAMS; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +struct fsp_header *fsps_hdr = NULL; + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify = NULL; + + if (!fsps_hdr) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr->image_base + + fsps_hdr->notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify((struct fsp_notify_params *) &phase); +} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index d600635..575c2eb 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -19,6 +19,7 @@ typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) (struct SILICON_INIT_UPD *upd); +extern struct fsp_header *fsps_hdr; static enum fsp_status do_silicon_init(struct fsp_header *hdr) { @@ -43,11 +44,14 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) enum fsp_status fsp_silicon_init(void) { - struct fsp_header hdr; + static struct fsp_header hdr; if (fsp_load_binary(&hdr, "blobs/fsp-s.bin") != CB_SUCCESS) return FSP_NOT_FOUND; + /* save the FSPS header, it will come in handy during notify */ + fsps_hdr = &hdr; + return do_silicon_init(&hdr); }

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Patch set updated for coreboot: soc/apollolake: Add lpc device driver
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13356 -gerrit commit a3b2746cea54650850c13bb73b328df46edc7b01 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Thu Nov 12 18:19:41 2015 -0800 soc/apollolake: Add lpc device driver A dedicated pci device driver required for LPC devices as the legacy IO range need to be included to avoid IO resource confilict. Blindly set to 0~0x1000 to also avoid the IO resource of COMA/COMB/LPT/FDD and LPC.Without this driver system will have assertion on load RTC DXE driver in UEFI payloads. Change-Id: Icc462c159c2cf39cc1030d55acee79e73a6bfb35 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/lpc.c | 52 +++++++++++++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7efb3ba..e9f1079 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -27,6 +27,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c ramstage-y += tsc_freq.c diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c new file mode 100644 index 0000000..8f0d2ad --- /dev/null +++ b/src/soc/intel/apollolake/lpc.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +static void soc_lpc_add_io_resources(device_t dev) +{ + struct resource *res; + + /* Add the default claimed legacy IO range for the LPC device. */ + res = new_resource(dev, 0); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void soc_lpc_read_resources(device_t dev) +{ + /* Get the PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* Add IO resources to LPC. */ + soc_lpc_add_io_resources(dev); +} + +static struct device_operations device_ops = { + .read_resources = &soc_lpc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, +}; + +static const unsigned short pci_device_ids[] = { + 0x5AE8, + 0 +}; + +static const struct pci_driver soc_lpc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: soc/apollolake: Place new romstage stack in CAR instead of RAM
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13357 -gerrit commit adb2482a9ffbbd84700a1d30655a251079f8c5c0 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Nov 13 17:15:03 2015 -0800 soc/apollolake: Place new romstage stack in CAR instead of RAM We can allocate a new romstage stack in CAR because we don't tear down CAR in romstage. This simple change improves ramstage loading time by about 30%. Change-Id: I5762c74cdc0ea8cb0aade3fdf8071cb86ec3fe0e Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 13 +------------ src/soc/intel/apollolake/romstage/entry.inc | 6 +++--- src/soc/intel/apollolake/romstage/romstage.c | 29 ++++++++++++---------------- 3 files changed, 16 insertions(+), 32 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index eb9bd79..1b60bcf 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -12,7 +12,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 # CPU specific options - select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select IOAPIC select SMP select SSE2 @@ -70,17 +69,7 @@ config DCACHE_RAM_BOOTBLOCK_STACK_SIZE default 0x800 help The amount of anticipated stack usage from the bootblock during - pre-romstage initialization. - -config ROMSTAGE_RAM_STACK_SIZE - hex - default 0x5000 - help - The size of the romstage stack after memory is available. Because CAR - space is very crowded, only a very limited part of CAR is available - for stack. More than that is needed to decompress ramstage. This - variable indicates how much RAM to reserve for the stack after - raminit. The stack is automatically switched after romstage_main(). + pre-romstage initialization.. config IFD_BIOS_START hex diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc index 8c0670c..2c6dfd6 100644 --- a/src/soc/intel/apollolake/romstage/entry.inc +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -21,9 +21,9 @@ apollolake_entry: call romstage_entry /* - * eax contains pointer to a region in RAM that we've been given the go - * ahead to use as stack. The old stack is empty at this point, so we - * don't have to relocate anything. + * eax contains pointer to a region that we've been given the go ahead + * to use as stack. The old stack is empty at this point, so we don't + * have to relocate anything. */ mov esp, eax diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index b7ffd3a..24fad92 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -54,23 +54,18 @@ static void soc_early_romstage_init(void) pci_write_config32(PCI_DEV(0, 13, 0), 0x60, 1<<7); } -static void *alloc_stack_in_ram(void) +/* + * Now that FSP is done consuming large amounts of CAR, we can use a much + * larger portion of CAR for the stack. The larger stack is needed for + * decompressing ramstage. It turns out that setting the stack pointer to top + * of CAR gives us the largest uninterrupted stack. + */ +static void *realloc_stack(void) { - uint8_t *ram_stack = cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK, - CONFIG_ROMSTAGE_RAM_STACK_SIZE); - - /* - * If cbmem fails to give us a memory window, try to get a stack at - * 2 MiB, and hope we can go forward. The 2 MiB address is arbitrary. - */ - if (ram_stack == NULL) { - printk(BIOS_ALERT, "Could not find place for stack\n"); - return (void *)(2 * MiB); - } - - /* The initial stack pointer should point at the top of the region */ - ram_stack += CONFIG_ROMSTAGE_RAM_STACK_SIZE - sizeof(size_t); - return ram_stack; + uintptr_t new_stack = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE; + new_stack -= sizeof(size_t); + printk(BIOS_DEBUG, "Placing new stack at 0x%lx\n", new_stack); + return (void *)new_stack; } asmlinkage void* romstage_entry(void) @@ -100,7 +95,7 @@ asmlinkage void* romstage_entry(void) if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request"); - return alloc_stack_in_ram(); + return realloc_stack(); } asmlinkage void romstage_after_raminit(void)

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Patch set updated for coreboot: drivers/intel/fsp2_0: Update FspUpdVpd header and adjust wrapper code
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13354 -gerrit commit a552a647f23f170d721d5d7f7525bfbcc4e3b6ab Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 11 13:02:18 2015 -0800 drivers/intel/fsp2_0: Update FspUpdVpd header and adjust wrapper code As of this writing, the FSP2.0 ABI is not fully defined, and this is why wrapper code needs to be adjusted with this header update. Change-Id: I47a1e36a4a0481162976800950bc856094f25711 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 361 +++++++++-------------- src/drivers/intel/fsp2_0/memory_init.c | 6 +- src/drivers/intel/fsp2_0/silicon_init.c | 5 +- 3 files changed, 142 insertions(+), 230 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h index bdd5999..b3e2b6b 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -110,338 +110,253 @@ struct BL_GPIO_PAD_INIT { +#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x4450555F54505346 /* 'FSPT_UPD' */ +#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +#define FSP_SILICON_INIT_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + struct TEMP_RAM_INIT_UPD { -/** Offset 0x0020 +/** Offset 0x0000 **/ uint64_t Signature; -/** Offset 0x0028 +/** Offset 0x0008 **/ uint8_t Revision; -/** Offset 0x0029 +/** Offset 0x0009 **/ - uint8_t UnusedUpdSpace0[83]; -/** Offset 0x007C + uint8_t UnusedUpdSpace0[67]; +/** Offset 0x004C **/ uint32_t ReservedTempRamInitUpd; } __attribute__((packed)); struct MEMORY_INIT_UPD { -/** Offset 0x0080 +/** Offset 0x0000 **/ uint64_t Signature; -/** Offset 0x0088 +/** Offset 0x0008 **/ uint8_t Revision; -/** Offset 0x0089 +/** Offset 0x0009 **/ - uint8_t UnusedUpdSpace1[7]; -/** Offset 0x0090 + uint8_t UnusedUpdSpace0[23]; +/** Offset 0x0020 Debug Serial Port Base - Debug serial port resource base address, either I/O or MMIO base. + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. **/ uint32_t SerialDebugPortAddress; -/** Offset 0x0094 +/** Offset 0x0024 Debug Serial Port Type - Debug serial port resource type. NONE means no serial port support. + 16550 compatible debug serial port resource type. NONE means no serial port support. **/ uint8_t SerialDebugPortType; -/** Offset 0x0095 +/** Offset 0x0025 Serial Port Debug Device - Select active serial port device. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. **/ uint8_t SerialDebugPortDevice; -/** Offset 0x0096 +/** Offset 0x0026 Debug Serial Port Stride Size - Debug serial port register map stride size. + Debug serial port register map stride size in bytes. **/ uint8_t SerialDebugPortStrideSize; -/** Offset 0x0097 +/** Offset 0x0027 **/ - uint8_t ReservedUpd1; -/** Offset 0x0098 - Memory FastBootSupport - MRC Fast Boot Support + uint8_t UnusedUpdSpace1; +/** Offset 0x0028 + Memory Fast Boot + Enable/Disable MRC fast boot support. **/ uint8_t MrcFastBoot; -/** Offset 0x0099 -**/ - uint8_t UnusedUpdSpace2[7]; -/** Offset 0x00A0 - Memory EccSupport - ECC Support -**/ - uint8_t EccSupport; -/** Offset 0x00A1 - Memory DdrFreqLimit - DDR Freq Limit -**/ - uint8_t DdrFreqLimit; -/** Offset 0x00A2 - Memory MaxTolud - MaxTolud -**/ - uint32_t MaxTolud; -/** Offset 0x00A6 - MrcDebugMsgLevel - Set MRC DebugMsg Level +/** Offset 0x0029 **/ - uint8_t MrcDebugMsgLevel; -/** Offset 0x00A7 + uint8_t UnusedUpdSpace2[103]; +/** Offset 0x0090 Integrated Graphics Device - Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Alwarys disable IGD + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. **/ uint8_t Igd; -/** Offset 0x00A8 +/** Offset 0x0091 DVMT Pre-Allocated - Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. **/ uint8_t IgdDvmt50PreAlloc; -/** Offset 0x00A9 +/** Offset 0x0092 Aperture Size - Select the Aperture Size. + Select the Aperture Size used by the Internal Graphics Device. **/ uint8_t IgdApertureSize; -/** Offset 0x00AA +/** Offset 0x0093 GTT Size - Select the GTT Size. + Select the GTT Size used by the Internal Graphics Device. **/ uint8_t GTTSize; -/** Offset 0x00AB +/** Offset 0x0094 Primary Display Select which of IGD/PCI Graphics device should be Primary Display. **/ uint8_t PrimaryVideoAdaptor; -/** Offset 0x00AC +/** Offset 0x0095 + GT PM Support + Enable/Disable GT power management support. **/ uint8_t PmSupport; -/** Offset 0x00AD +/** Offset 0x0096 + RC6(Render Standby) + Enable/Disable render standby support. **/ uint8_t EnableRenderStandby; -/** Offset 0x00AE +/** Offset 0x0097 + PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). **/ uint8_t PavpEnable; -/** Offset 0x00AF +/** Offset 0x0098 **/ - uint8_t SataEnable; -/** Offset 0x00B0 + uint8_t UnusedUpdSpace3[116]; +/** Offset 0x010C + OEM File Loading Address + Determine the memory base address to load a specified file from CSE file system after memory is available. +**/ + uint32_t ObbLoadingBase; +/** Offset 0x0110 + OEM file name to load + Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. +**/ + uint8_t ObbFileName[16]; +/** Offset 0x0120 +**/ + uint8_t UnusedUpdSpace4[48]; +/** Offset 0x0150 + GPIO Table Pointer + GPIO table pointer to a BL_GPIO_PAD_INIT structure. +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; +/** Offset 0x0154 +**/ + uint8_t UnusedUpdSpace5[56]; +/** Offset 0x018C +**/ + uint32_t ReservedMemoryInitUpd; +} __attribute__((packed)); + +struct SILICON_INIT_UPD { +/** Offset 0x0000 +**/ + uint64_t Signature; +/** Offset 0x0008 +**/ + uint8_t Revision; +/** Offset 0x0009 +**/ + uint8_t UnusedUpdSpace0[23]; +/** Offset 0x0020 + Enable SD controller + Enable/disable SD Card controller. +**/ + uint8_t SdcardEnabled; +/** Offset 0x0021 + Enable SDIO controller + Enable/disable SDIO controller. +**/ + uint8_t SdioEnabled; +/** Offset 0x0022 + Enable eMMC controller + Enable/disable eMMC controller. +**/ + uint8_t eMMCEnabled; +/** Offset 0x0023 +**/ + uint8_t UnusedUpdSpace1[93]; +/** Offset 0x0080 Enable SATA Enable/disable SATA controller. **/ uint8_t EnableSata; -/** Offset 0x00B1 +/** Offset 0x0081 SATA Mode Select SATA controller working mode. **/ uint8_t SataMode; -/** Offset 0x00B2 - Enable SATA - Enable/disable SATA controller. +/** Offset 0x0082 + Aggressive SATA LPM Support + Enable SOC to aggressively enter link power state for SATA. **/ uint8_t SataSalpSupport; -/** Offset 0x00B3 +/** Offset 0x0083 Enable SATA ports Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t SataPortsEnable[2]; -/** Offset 0x00B5 +/** Offset 0x0085 Enable SATA DEVSLP Feature Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t SataPortsDevSlp[2]; -/** Offset 0x00B7 +/** Offset 0x0087 Enable PCIE RP Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ uint8_t PcieRpEnable[6]; -/** Offset 0x00BD +/** Offset 0x008D Configure CLKREQ Number - Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in arrary can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. **/ uint8_t PcieRpClkReqNumber[6]; -/** Offset 0x00C3 +/** Offset 0x0093 Enable USB2 ports Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t PortUsb20Enable[8]; -/** Offset 0x00CB +/** Offset 0x009B Enable USB3 ports Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. **/ uint8_t PortUsb30Enable[6]; -/** Offset 0x00D1 +/** Offset 0x00A1 Enable XHCI SSIC Eanble Enable/disable XHCI SSIC port. **/ uint8_t SsicPortEnable; -/** Offset 0x00D2 +/** Offset 0x00A2 Enable SMBus Enable/disable SMBus controller. **/ uint8_t SmbusEnable; -/** Offset 0x00D3 +/** Offset 0x00A3 **/ - uint8_t UnusedUpdSpace3[13]; -/** Offset 0x00E0 + uint8_t UnusedUpdSpace2[13]; +/** Offset 0x00B0 + ISP Enable/Disable + Enable/Disable ISP Device. **/ uint8_t IspEn; -/** Offset 0x00E1 -**/ - uint8_t IspAcpiMode; -/** Offset 0x00E2 -**/ - uint32_t AdditionalFvBase; -/** Offset 0x00E6 -**/ - uint8_t UnusedUpdSpace4[122]; -/** Offset 0x0160 -**/ - uint32_t ObbLoadingBase; -/** Offset 0x0164 -**/ - uint32_t ObbFlashBase; -/** Offset 0x0168 -**/ - uint32_t ObbFlashSize; -/** Offset 0x016C -**/ - uint8_t UnusedUpdSpace5[20]; -/** Offset 0x0180 -**/ - uint8_t ObbFileName[16]; -/** Offset 0x0190 -**/ - uint8_t UnusedUpdSpace6[48]; -/** Offset 0x01C0 -**/ - struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x01C4 -**/ - uint8_t UnusedUpdSpace7[56]; -/** Offset 0x01FC -**/ - uint32_t ReservedMemoryInitUpd; -} __attribute__((packed)); - -struct SILICON_INIT_UPD { -/** Offset 0x0200 -**/ - uint64_t Signature; -/** Offset 0x0208 +/** Offset 0x00B1 **/ - uint8_t Revision; -/** Offset 0x0209 + uint8_t UnusedUpdSpace3[303]; +/** Offset 0x01E0 + BMP Logo Data Size + BMP logo data buffer size. **/ - uint8_t UnusedUpdSpace8[7]; -/** Offset 0x0210 - Logo Pointer - Points to PEI Display Logo Image + uint32_t LogoSize; +/** Offset 0x01E4 + BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. **/ uint32_t LogoPtr; -/** Offset 0x0214 - Logo Size - Size of PEI Display Logo Image -**/ - uint32_t LogoSize; -/** Offset 0x0218 - Graphics Configuration Ptr - Points to VBT +/** Offset 0x01E8 + Graphics Configuration Data Pointer + Graphics configuration data used for initialization. **/ uint32_t GraphicsConfigPtr; -/** Offset 0x021C - Enable HD Audio DSP - Enable/disable HD Audio DSP feature. -**/ - uint8_t DspEnable; -/** Offset 0x021D - Select HDAudio IoBuffer Ownership - Select HDAudio IoBuffer Ownership. -**/ - uint8_t IoBufferOwnership; -/** Offset 0x021E - BXT PlatformType - BXT PlatformType. -**/ - uint8_t PlatformType; -/** Offset 0x021F - DynSR - Enable/disable DynSR feature. -**/ - uint8_t DynSR; -/** Offset 0x0220 +/** Offset 0x01EC **/ - uint8_t UnusedUpdSpace9[20]; -/** Offset 0x0234 + uint8_t UnusedUpdSpace4[12]; +/** Offset 0x01F8 **/ - uint8_t ReservedSiliconInitUpd[292]; -} __attribute__((packed)); - -#define FSP_UPD_SIGNATURE 0x2444505554584224 /* '$BXTUPD$' */ -#define FSP_TEMP_RAM_INIT_UPD_SIGNATURE 0x24445055504D5424 /* '$TMPUPD$' */ -#define FSP_MEMORY_INIT_UPD_SIGNATURE 0x244450554D454D24 /* '$MEMUPD$' */ -#define FSP_SILICON_INIT_UPD_SIGNATURE 0x244450555F495324 /* '$SI_UPD$' */ - -struct UPD_DATA_REGION { -/** Offset 0x0000 -**/ - uint64_t Signature; -/** Offset 0x0008 -**/ - uint8_t Revision; -/** Offset 0x0009 -**/ - uint8_t ReservedUpd0[7]; -/** Offset 0x0010 -**/ - uint32_t TempRamInitUpdOffset; -/** Offset 0x0014 -**/ - uint32_t MemoryInitUpdOffset; -/** Offset 0x0018 -**/ - uint32_t SiliconInitUpdOffset; -/** Offset 0x001C -**/ - uint32_t ReservedUpd1; -/** Offset 0x0020 -**/ - struct TEMP_RAM_INIT_UPD TempRamInitUpd; -/** Offset 0x0080 -**/ - struct MEMORY_INIT_UPD MemoryInitUpd; -/** Offset 0x0200 -**/ - struct SILICON_INIT_UPD SiliconInitUpd; -/** Offset 0x0358 -**/ - uint8_t UnusedUpdSpace10[166]; -/** Offset 0x03FE -**/ - uint16_t RegionTerminator; + uint32_t ReservedSiliconInitUpd; } __attribute__((packed)); #define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ -#define FSP_IMAGE_REV 0x01010000 - -struct VPD_DATA_REGION { -/** Offset 0x0000 -**/ - uint64_t PcdVpdRegionSign; -/** Offset 0x0008 - PcdImageRevision -**/ - uint32_t PcdImageRevision; -/** Offset 0x000C -**/ - uint32_t PcdUpdRegionOffset; -/** Offset 0x0010 -**/ - uint32_t PcdUpdRegionSize; -/** Offset 0x0014 -**/ - uint64_t UnusedVpdSpace0; -/** Offset 0x001C -**/ - uint32_t PcdVpdReserved; -} __attribute__((packed)); +#define FSP_IMAGE_REV 0x00060000 #endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 92c30b4..4ac720d 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -41,7 +41,6 @@ typedef asmlinkage enum fsp_status (*fsp_memory_init_fn) static void fill_console_params(struct MEMORY_INIT_UPD *memupd) { - /* TODO: Check that FSP actually respects these flags */ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { memupd->SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; memupd->SerialDebugPortType = 2; @@ -65,12 +64,11 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, fsp_memory_init_fn fsp_raminit; struct fsp_memory_init_params raminit_params; struct fsp_init_rt_common_buffer rt_buffer; - struct MEMORY_INIT_UPD raminit_upd; - struct UPD_DATA_REGION *upd_region; + struct MEMORY_INIT_UPD raminit_upd, *upd_region; post_code(0x34); upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base); - memcpy(&raminit_upd, upd_region, sizeof(raminit_upd)); + raminit_upd = *upd_region; /* Zero fill RT Buffer data and start populating fields. */ memset(&rt_buffer, 0, sizeof(rt_buffer)); diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index a6011c9..d600635 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -22,15 +22,14 @@ typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) static enum fsp_status do_silicon_init(struct fsp_header *hdr) { - struct SILICON_INIT_UPD silicon_upd; + struct SILICON_INIT_UPD silicon_upd, *upd_region; fsp_silicon_init_fn silicon_init; - void *upd_region; enum fsp_status status; upd_region = (void*)(hdr->cfg_region_offset + hdr->image_base); /* populate upd with defaults */ - memcpy(&silicon_upd, upd_region, sizeof(silicon_upd)); + silicon_upd = *upd_region; silicon_init = (void *)(hdr->image_base + hdr->silicon_init_entry_offset);

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Patch set updated for coreboot: soc/apollolake: Add set_resources for the root device
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13355 -gerrit commit 1e76caeebdbafc12a8571f20102d161513d8e7b9 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Nov 11 19:00:46 2015 -0800 soc/apollolake: Add set_resources for the root device Change-Id: I4d494924d787569382b2f7c562354d94f911f857 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/chip.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 34d6d3a..52b8dd4 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,9 +16,14 @@ #include <device/pci.h> #include <fsp/api.h> +static void pci_domain_set_resources(device_t dev) +{ + assign_resources(dev->link_list); +} + static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, - .set_resources = DEVICE_NOOP, + .set_resources = pci_domain_set_resources, .enable_resources = NULL, .init = NULL, .scan_bus = pci_domain_scan_bus,

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Patch set updated for coreboot: soc/intel/apollolake: Fill ACPI FADT table
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13352 -gerrit commit 386d3a04e81aa1c0c81ebdb37e7321870de0f8e1 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Nov 10 19:00:18 2015 -0800 soc/intel/apollolake: Fill ACPI FADT table Fill the ACPI FADT table base on apollolake SOC definition. Change-Id: Ib7226a3b130f14810dc2af5ca484cef58f477063 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 73 ++++++++++++++++++++++++++++- src/soc/intel/apollolake/include/soc/acpi.h | 21 +++++++++ src/soc/intel/apollolake/include/soc/pm.h | 32 +++++++++++++ 3 files changed, 124 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4246f40..9be1705 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,12 +11,81 @@ */ #include <arch/acpi.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/iomap.h> +#include <soc/pm.h> + unsigned long acpi_fill_mcfg(unsigned long current) { - return 0; + return current; } + unsigned long acpi_fill_madt(unsigned long current) { - return 0; + return current; +} + +static int acpi_sci_irq(void) +{ + int sci_irq = 9; + return sci_irq; } +void soc_fill_common_fadt(acpi_fadt_t * fadt) +{ + const uint16_t pmbase = ACPI_PMIO_BASE; + + fadt->sci_int = acpi_sci_irq(); + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + + fadt->pm1a_evt_blk = pmbase + PM1_STS; + fadt->pm1a_cnt_blk = pmbase + PM1_CNT; + fadt->pm_tmr_blk = pmbase + PM1_TMR; + fadt->gpe0_blk = pmbase + GPE0_STS(0); + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm_tmr_len = 4; + /* There are 4 GPE0 STS/EN pairs each 32 bits wide. */ + fadt->gpe0_blk_len = 2 * GPE0_REG_MAX * sizeof(uint32_t); + fadt->p_lvl2_lat = 0x65; + fadt->p_lvl3_lat = 0x3E9; + fadt->flush_size = 0x400; + fadt->flush_stride = 0x10; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->century = 0x32; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_C2_MP_SUPPORTED | ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_value = 6; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.addrl = pmbase + PM1_STS; + + fadt->x_pm1b_evt_blk.space_id = 1; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.addrl = pmbase + PM1_CNT; + + fadt->x_pm1b_cnt_blk.space_id = 1; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.addrl = pmbase + PM1_TMR; + + fadt->x_gpe1_blk.space_id = 1; +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h new file mode 100644 index 0000000..7e112d7 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ACPI_H_ +#define _SOC_APOLLOLAKE_ACPI_H_ + +#include <arch/acpi.h> + +/* Zero value won't be programmed again in FADT table. */ +void soc_fill_common_fadt(acpi_fadt_t * fadt); + +#endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h new file mode 100644 index 0000000..5a3ac96 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PM_H_ +#define _SOC_APOLLOLAKE_PM_H_ + +/* ACPI_BASE_ADDRESS / PMBASE */ + +#define PM1_STS 0x00 +#define PM1_EN 0x02 +#define PM1_CNT 0x04 +#define PM1_TMR 0x08 +#define SMI_EN 0x40 +#define SMI_STS 0x44 +#define GPE_CNTL 0x50 +#define DEVACT_STS 0x4c + +#define GPE0_REG_MAX 4 +#define GPE0_REG_SIZE 32 +#define GPE0_STS(x) (0x20 + (x * 4)) +#define GPE0_EN(x) (0x30 + (x * 4)) + +#endif

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Patch set updated for coreboot: src/mainboard/intel/apollolake_rvp: Include FADT tables
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13353 -gerrit commit 4ad4bb610046f902a458902fb9b8987321950ca9 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Wed Nov 11 15:14:29 2015 -0800 src/mainboard/intel/apollolake_rvp: Include FADT tables Include SOC specific FADT tables to current mainboard. Change-Id: Id4099528657304e9f7675c839e7666c58f189004 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/acpi_tables.c | 28 ++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c index d21b743..c4910ea 100644 --- a/src/mainboard/intel/apollolake_rvp/acpi_tables.c +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -10,9 +10,33 @@ * (at your option) any later version. */ -#include <arch/acpi.h> +#include <string.h> +#include <soc/acpi.h> void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) { -} + acpi_header_t *header = &(fadt->header); + + memset(fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 5; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (uintptr_t)facs; + fadt->dsdt = (uintptr_t)dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + fadt->x_firmware_ctl_l = (uintptr_t)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (uintptr_t)dsdt; + fadt->x_dsdt_h = 0; + + soc_fill_common_fadt(fadt); + + header->checksum = acpi_checksum((void *)fadt, header->length); +}

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Patch set updated for coreboot: soc/apollolake: Add skelton ACPI entry
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit 3eb7e0acb59c9ce779ee9e5ff2466d7e23efb0f9 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skelton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 18 +++++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/acpi.c | 22 ++++++++++++++++++ 5 files changed, 71 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 5e6c4f0..ec71e96 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..d21b743 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} + diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..1736cea --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 59d13e3..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += romstage/romstage.c romstage-y += tsc_freq.c romstage-y += uart_early.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gpio.c diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..4246f40 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +} +

1 0

Patch set updated for coreboot: intel/strago: Enable native mode on sd card cd line
by Hannah Williams 26 Jan '16

26 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741 -gerrit commit 73de0027896781ef693d9468af640f77c5510420 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Nov 4 14:25:15 2015 -0800 intel/strago: Enable native mode on sd card cd line Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index ab8c120..a0a0b29 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,8 +74,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */

1 0

New patch to review for coreboot: util/crossgcc: Add option to bootstrap a host gcc
by Nico Huber 26 Jan '16

26 Jan '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13473 -gerrit commit e8f4269e2d322174dbd769ae27bdd6b5141ddffc Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Jan 26 16:10:17 2016 +0100 util/crossgcc: Add option to bootstrap a host gcc Bootstrapping gcc is the recommended way if your host gcc's version doesn't match the gcc version you're going to build. While a build with an outdated host gcc usually succeeds, an outdated gnat seems to be a bigger issue. Change-Id: Icb47d3e9dbafc55737fbc3ce62a084fb9d5f359a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/Makefile | 3 ++- util/crossgcc/buildgcc | 38 +++++++++++++++++++++++++++++++++++--- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 79e0c3c..4f5d919 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -25,7 +25,8 @@ build_tools: build_gcc build_iasl build_gdb build_gcc: bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) \ - $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) + $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) \ + $(if $(BUILD_BOOTSTRAP),-b) \ build_gdb: ifeq ($(SKIP_GDB),) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 5b7c45a..03007ae 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -19,7 +19,7 @@ cd $(dirname $0) CROSSGCC_DATE="January 26th, 2016" -CROSSGCC_VERSION="1.35" +CROSSGCC_VERSION="1.36" # default settings PACKAGE=GCC @@ -30,6 +30,7 @@ DESTDIR= CLEANHOST=0 SAVETEMPS=0 SKIPPYTHON=1 +BOOTSTRAP=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -361,6 +362,8 @@ myhelp() printf " [-P|--package <package>] Build a specific package: GCC, CLANG, IASL, GDB\n" printf " (defaults to $PACKAGE)\n" printf "GCC specific options:\n" + printf " [-b|--bootstrap] bootstrap the host compiler before building\n" + printf " the cross compiler\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-l|--languages <languages>] comma separated list of target languages\n" @@ -461,8 +464,24 @@ build_BINUTILS() { $MAKE install DESTDIR=$DESTDIR || touch .failed } +build_host_GCC() { + CC="$CC" CFLAGS_FOR_TARGET="-O2" BOOT_CFLAGS="-O2" \ + ../gcc-${GCC_VERSION}/configure \ + --prefix=$2 --libexecdir=$2/lib \ + --enable-bootstrap \ + --disable-werror --disable-nls \ + --disable-libssp --disable-libquadmath \ + ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ + --with-gmp=$DESTDIR$2 --with-mpfr=$DESTDIR$2 \ + --with-mpc=$DESTDIR$2 --with-libelf=$DESTDIR$2 \ + --with-pkgversion="coreboot toolchain host bootstrap v$CROSSGCC_VERSION $CROSSGCC_DATE" \ + && \ + $MAKE $JOBS CFLAGS_FOR_BUILD="-O2" BOOT_CFLAGS="-O2" bootstrap && \ + $MAKE install DESTDIR=$DESTDIR && \ + ln -s gcc $DESTDIR$2/bin/cc || touch .failed +} -build_GCC() { +build_target_GCC() { # GCC does not honor HOSTCFLAGS at all. CFLAGS are used for # both target and host object files. # There's a work-around called CFLAGS_FOR_BUILD and CFLAGS_FOR_TARGET @@ -489,6 +508,14 @@ build_GCC() { fi } +build_GCC() { + if echo $1 | grep -q '^host-' >/dev/null 2>&1; then + build_host_GCC $@ + else + build_target_GCC $@ + fi +} + build_EXPAT() { CC="$CC" CFLAGS="$HOSTCFLAGS" ../${EXPAT_DIR}/configure --disable-shared \ --prefix=$2 --target=${TARGETARCH} || touch .failed @@ -605,6 +632,7 @@ while true ; do -r|--cleanhost) shift; CLEANHOST=1;; -t|--savetemps) shift; SAVETEMPS=1;; -d|--directory) shift; TARGETDIR="$1"; shift;; + -b|--bootstrap) shift; BOOTSTRAP=1;; -p|--platform) shift; TARGETARCH="$1"; shift;; -l|--languages) shift; LANGUAGES="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; @@ -647,7 +675,11 @@ case "$PACKAGE" in GCC|gcc) echo "Target architecture is now $TARGETARCH" NAME="${TARGETARCH} cross GCC" - PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF BINUTILS GCC" + if [ $BOOTSTRAP -eq 1 ]; then + PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF host-GCC BINUTILS GCC" + else + PACKAGES="host-GMP host-MPFR host-MPC host-LIBELF BINUTILS GCC" + fi ;; GDB|gdb) NAME="${TARGETARCH} cross GDB"

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coreboot-gerrit January 2016