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Patch set updated for coreboot: drivers/intel/fsp2_0: Upgrade UPD/VPD definition for FSP
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13366 -gerrit commit c5120645a572da2f5ff719efac87a74c572f4880 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Nov 24 12:49:01 2015 -0800 drivers/intel/fsp2_0: Upgrade UPD/VPD definition for FSP New FSP update include extra entry for DRAM Config Data, which is required for MRC.If coreboot do not provide those data, MRC will dead loop on CP code 0x0. Change-Id: I8fa709b8478a8eeb38a9ec32784b77af07b2c90d Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 290 ++++++++++++++++++----- 1 file changed, 232 insertions(+), 58 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h index b3e2b6b..23ae434 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -33,38 +33,9 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPDVPD_H__ #define __FSPUPDVPD_H__ -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 -struct DIMM_INFO { - uint8_t DimmId; - uint32_t SizeInMb; -} __attribute__((packed)); - -struct CHANNEL_INFO { - uint8_t ChannelId; - uint8_t DimmCount; - struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} __attribute__((packed)); - -struct FSP_SMBIOS_MEMORY_INFO { - uint8_t Revision; - uint16_t DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - uint8_t MemoryType; - uint16_t MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - uint8_t ErrorCorrectionType; - uint8_t ChannelCount; - struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} __attribute__((packed)); - -typedef union{ - uint32_t padCnf0; +typedef union { + uint32_t PadCnf0; struct { uint32_t GPIOTxState:1; ///< 0 GPIO TX State uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO @@ -84,8 +55,8 @@ typedef union{ } r; } BL_CONF_PAD0; -typedef union{ - uint32_t padCnf1; +typedef union { + uint32_t PadCnf1; struct { uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO uint32_t Reserved:1; ///< 7 Reserved. @@ -99,13 +70,13 @@ typedef union{ } BL_CONF_PAD1; struct BL_GPIO_PAD_INIT { - BL_CONF_PAD0 padConfg0; - BL_CONF_PAD1 padConfg1; + BL_CONF_PAD0 PadConfg0; + BL_CONF_PAD1 PadConfg1; uint8_t Community; - uint16_t MMIO_ADDRESS; + uint16_t MmioAddress; bool HostSw; - bool WakeEnabled; ///< Wake enable for direct IRQ pin - wchar_t *pad_name; ///< GPIO Pin Name for debug purpose + bool WakeEnabled; + wchar_t *PadName; } __attribute__((packed)); @@ -114,6 +85,212 @@ struct BL_GPIO_PAD_INIT { #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ #define FSP_SILICON_INIT_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +struct DRAM_CONFIG { +/** Offset 0x0000 + Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. +**/ + uint8_t Package; +/** Offset 0x0001 + Profile + Profile list +**/ + uint8_t Profile; +/** Offset 0x0002 + MemoryDown + Memory Down. +**/ + uint8_t MemoryDown; +/** Offset 0x0003 + DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. +**/ + uint8_t DDR3LPageSize; +/** Offset 0x0004 + DDR3LASR + NOTE: Only for memory down. +**/ + uint8_t DDR3LASR; +/** Offset 0x0005 + ScramblerSupport + Scrambler Support. +**/ + uint8_t ScramblerSupport; +/** Offset 0x0006 + ChannelHashMask + Channel Hash Mask. +**/ + uint16_t ChannelHashMask; +/** Offset 0x0008 + SliceHashMask + Slice Hash Mask. +**/ + uint16_t SliceHashMask; +/** Offset 0x000A + InterleavedMode + Interleaved Mode. +**/ + uint8_t InterleavedMode; +/** Offset 0x000B + ChannelsSlicesEnable + Channels Slices Enable. +**/ + uint8_t ChannelsSlicesEnable; +/** Offset 0x000C + MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. +**/ + uint8_t MinRefRate2xEnable; +/** Offset 0x000D + DualRankSupportEnable + Dual Rank Support Enable. +**/ + uint8_t DualRankSupportEnable; +/** Offset 0x000E + DisableFastBoot + 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. +**/ + uint8_t DisableFastBoot; +/** Offset 0x000F + RmtMode + Rank Margin Tool Mode. +**/ + uint8_t RmtMode; +/** Offset 0x0010 + MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t MemorySizeLimit; +/** Offset 0x0012 + LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t LowMemoryMaxValue; +/** Offset 0x0014 + HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t HighMemoryMaxValue; +/** Offset 0x0016 + DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM0SPDAddress; +/** Offset 0x0017 + DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM1SPDAddress; +/** Offset 0x0018 + Ch0_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; +/** Offset 0x0019 + Ch0_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch0_DeviceWidth; +/** Offset 0x001A + Ch0_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch0_DramDensity; +/** Offset 0x001B + Ch0_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_Option; +/** Offset 0x001C + Ch1_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; +/** Offset 0x001D + Ch1_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch1_DeviceWidth; +/** Offset 0x001E + Ch1_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch1_DramDensity; +/** Offset 0x001F + Ch1_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch1_Option; +/** Offset 0x0020 + Ch2_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; +/** Offset 0x0021 + Ch2_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch2_DeviceWidth; +/** Offset 0x0022 + Ch2_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch2_DramDensity; +/** Offset 0x0023 + Ch2_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch2_Option; +/** Offset 0x0024 + Ch3_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; +/** Offset 0x0025 + Ch3_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch3_DeviceWidth; +/** Offset 0x0026 + Ch3_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch3_DramDensity; +/** Offset 0x0027 + Ch3_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch3_Option; +/** Offset 0x0028 + Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch0_Bit_swizzling[32]; +/** Offset 0x0048 + Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; +/** Offset 0x0068 + Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; +/** Offset 0x0088 + Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; +/** Offset 0x00A8 +**/ + uint8_t DramReserved; +} __attribute__((packed)); + +#define FSP_IMAGE_ID 0x245053464C504124 /* '$APLFSP$' */ +#define FSP_IMAGE_REV 0x00060000 + + + struct TEMP_RAM_INIT_UPD { /** Offset 0x0000 **/ @@ -212,29 +389,29 @@ struct MEMORY_INIT_UPD { uint8_t PavpEnable; /** Offset 0x0098 **/ - uint8_t UnusedUpdSpace3[116]; -/** Offset 0x010C + uint64_t UnusedUpdSpace3; +/** Offset 0x0000 +**/ + struct DRAM_CONFIG DramConfig; +/** Offset 0x01B9 +**/ + uint8_t UnusedUpdSpace6[35]; +/** Offset 0x01DC OEM File Loading Address Determine the memory base address to load a specified file from CSE file system after memory is available. **/ - uint32_t ObbLoadingBase; -/** Offset 0x0110 - OEM file name to load + uint32_t OemLoadingBase; +/** Offset 0x01E0 + OEM File Name to Load Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. **/ - uint8_t ObbFileName[16]; -/** Offset 0x0120 -**/ - uint8_t UnusedUpdSpace4[48]; -/** Offset 0x0150 + uint8_t OemFileName[16]; +/** Offset 0x01F0 GPIO Table Pointer GPIO table pointer to a BL_GPIO_PAD_INIT structure. **/ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0154 -**/ - uint8_t UnusedUpdSpace5[56]; -/** Offset 0x018C +/** Offset 0x01F4 **/ uint32_t ReservedMemoryInitUpd; } __attribute__((packed)); @@ -326,10 +503,10 @@ struct SILICON_INIT_UPD { **/ uint8_t UnusedUpdSpace2[13]; /** Offset 0x00B0 - ISP Enable/Disable - Enable/Disable ISP Device. + IPU Enable/Disable + Enable/Disable IPU Device. **/ - uint8_t IspEn; + uint8_t IpuEn; /** Offset 0x00B1 **/ uint8_t UnusedUpdSpace3[303]; @@ -356,7 +533,4 @@ struct SILICON_INIT_UPD { uint32_t ReservedSiliconInitUpd; } __attribute__((packed)); -#define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ -#define FSP_IMAGE_REV 0x00060000 - #endif

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Patch set updated for coreboot: soc/intel/apollolake/romstage: Add callback for update UPD
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13367 -gerrit commit 75202643b3c85515521a019ee558a945c7b65bad Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Nov 24 13:59:23 2015 -0800 soc/intel/apollolake/romstage: Add callback for update UPD Add callback for mainboard to update necessary UPD before FSP memory init started. Change-Id: I797463248d198fa0bf16a9dd7ac6efb7bccb39c1 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/include/soc/romstage.h | 3 +++ src/soc/intel/apollolake/romstage/romstage.c | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index eb69558..948a52e 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -14,8 +14,11 @@ #define _SOC_APOLLOLAKE_ROMSTAGE_H_ #include <arch/cpu.h> +#include <fsp/api.h> asmlinkage void *romstage_entry(void); asmlinkage void romstage_after_raminit(void); +void mainboard_memory_init_params(struct MEMORY_INIT_UPD *memupd); + #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 24fad92..b1595e8 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -102,3 +102,14 @@ asmlinkage void romstage_after_raminit(void) { run_ramstage(); } + +void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd) +{ + mainboard_memory_init_params(memupd); +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct MEMORY_INIT_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Upgrade UPD/VPD definition for FSP
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13366 -gerrit commit 639207455eebaaa7f9c8541e625dddb963ada7b8 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Nov 24 12:49:01 2015 -0800 drivers/intel/fsp2_0: Upgrade UPD/VPD definition for FSP New FSP update include extra entry for DRAM Config Data, which is required for MRC.If coreboot do not provide those data, MRC will dead loop on CP code 0x0. Change-Id: I8fa709b8478a8eeb38a9ec32784b77af07b2c90d Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h | 290 ++++++++++++++++++----- 1 file changed, 232 insertions(+), 58 deletions(-) diff --git a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h index b3e2b6b..6d96e1c 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h +++ b/src/drivers/intel/fsp2_0/include/fsp/FspUpdVpd.h @@ -33,38 +33,9 @@ are permitted provided that the following conditions are met: #ifndef __FSPUPDVPD_H__ #define __FSPUPDVPD_H__ -#define MAX_CHANNELS_NUM 2 -#define MAX_DIMMS_NUM 2 -struct DIMM_INFO { - uint8_t DimmId; - uint32_t SizeInMb; -} __attribute__((packed)); - -struct CHANNEL_INFO { - uint8_t ChannelId; - uint8_t DimmCount; - struct DIMM_INFO DimmInfo[MAX_DIMMS_NUM]; -} __attribute__((packed)); - -struct FSP_SMBIOS_MEMORY_INFO { - uint8_t Revision; - uint16_t DataWidth; - /** As defined in SMBIOS 3.0 spec - Section 7.18.2 and Table 75 - **/ - uint8_t MemoryType; - uint16_t MemoryFrequencyInMHz; - /** As defined in SMBIOS 3.0 spec - Section 7.17.3 and Table 72 - **/ - uint8_t ErrorCorrectionType; - uint8_t ChannelCount; - struct CHANNEL_INFO ChannelInfo[MAX_CHANNELS_NUM]; -} __attribute__((packed)); - -typedef union{ - uint32_t padCnf0; +typedef union { + uint32_t PadCnf0; struct { uint32_t GPIOTxState:1; ///< 0 GPIO TX State uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO @@ -84,8 +55,8 @@ typedef union{ } r; } BL_CONF_PAD0; -typedef union{ - uint32_t padCnf1; +typedef union { + uint32_t PadCnf1; struct { uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO uint32_t Reserved:1; ///< 7 Reserved. @@ -99,13 +70,13 @@ typedef union{ } BL_CONF_PAD1; struct BL_GPIO_PAD_INIT { - BL_CONF_PAD0 padConfg0; - BL_CONF_PAD1 padConfg1; + BL_CONF_PAD0 PadConfg0; + BL_CONF_PAD1 PadConfg1; uint8_t Community; - uint16_t MMIO_ADDRESS; + uint16_t MmioAddress; bool HostSw; - bool WakeEnabled; ///< Wake enable for direct IRQ pin - wchar_t *pad_name; ///< GPIO Pin Name for debug purpose + bool WakeEnabled; + wchar_t *PadName; } __attribute__((packed)); @@ -114,6 +85,212 @@ struct BL_GPIO_PAD_INIT { #define FSP_MEMORY_INIT_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ #define FSP_SILICON_INIT_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +struct DRAM_CONFIG { +/** Offset 0x0000 + Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. +**/ + uint8_t Package; +/** Offset 0x0001 + Profile + Profile list +**/ + uint8_t Profile; +/** Offset 0x0002 + MemoryDown + Memory Down. +**/ + uint8_t MemoryDown; +/** Offset 0x0003 + DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. +**/ + uint8_t DDR3LPageSize; +/** Offset 0x0004 + DDR3LASR + NOTE: Only for memory down. +**/ + uint8_t DDR3LASR; +/** Offset 0x0005 + ScramblerSupport + Scrambler Support. +**/ + uint8_t ScramblerSupport; +/** Offset 0x0006 + ChannelHashMask + Channel Hash Mask. +**/ + uint16_t ChannelHashMask; +/** Offset 0x0008 + SliceHashMask + Slice Hash Mask. +**/ + uint16_t SliceHashMask; +/** Offset 0x000A + InterleavedMode + Interleaved Mode. +**/ + uint8_t InterleavedMode; +/** Offset 0x000B + ChannelsSlicesEnable + Channels Slices Enable. +**/ + uint8_t ChannelsSlicesEnable; +/** Offset 0x000C + MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. +**/ + uint8_t MinRefRate2xEnable; +/** Offset 0x000D + DualRankSupportEnable + Dual Rank Support Enable. +**/ + uint8_t DualRankSupportEnable; +/** Offset 0x000E + DisableFastBoot + 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. +**/ + uint8_t DisableFastBoot; +/** Offset 0x000F + RmtMode + Rank Margin Tool Mode. +**/ + uint8_t RmtMode; +/** Offset 0x0010 + MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t MemorySizeLimit; +/** Offset 0x0012 + LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t LowMemoryMaxValue; +/** Offset 0x0014 + HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t HighMemoryMaxValue; +/** Offset 0x0016 + DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM0SPDAddress; +/** Offset 0x0017 + DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM1SPDAddress; +/** Offset 0x0018 + Ch0_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; +/** Offset 0x0019 + Ch0_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch0_DeviceWidth; +/** Offset 0x001A + Ch0_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch0_DramDensity; +/** Offset 0x001B + Ch0_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_Option; +/** Offset 0x001C + Ch1_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; +/** Offset 0x001D + Ch1_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch1_DeviceWidth; +/** Offset 0x001E + Ch1_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch1_DramDensity; +/** Offset 0x001F + Ch1_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch1_Option; +/** Offset 0x0020 + Ch2_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; +/** Offset 0x0021 + Ch2_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch2_DeviceWidth; +/** Offset 0x0022 + Ch2_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch2_DramDensity; +/** Offset 0x0023 + Ch2_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch2_Option; +/** Offset 0x0024 + Ch3_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; +/** Offset 0x0025 + Ch3_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. +**/ + uint8_t Ch3_DeviceWidth; +/** Offset 0x0026 + Ch3_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. +**/ + uint8_t Ch3_DramDensity; +/** Offset 0x0027 + Ch3_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch3_Option; +/** Offset 0x0028 + Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch0_Bit_swizzling[32]; +/** Offset 0x0048 + Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; +/** Offset 0x0068 + Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; +/** Offset 0x0088 + Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; +/** Offset 0x00A8 +**/ + uint8_t DramReserved; +} __attribute__((packed)); + +#define FSP_IMAGE_ID 0x245053464C504124 /* '$APLFSP$' */ +#define FSP_IMAGE_REV 0x00060000 + + + struct TEMP_RAM_INIT_UPD { /** Offset 0x0000 **/ @@ -212,29 +389,29 @@ struct MEMORY_INIT_UPD { uint8_t PavpEnable; /** Offset 0x0098 **/ - uint8_t UnusedUpdSpace3[116]; -/** Offset 0x010C + uint64_t UnusedUpdSpace3; +/** Offset 0x0000 +**/ + struct DRAM_CONFIG DramConfig; +/** Offset 0x01B9 +**/ + uint8_t UnusedUpdSpace6[35]; +/** Offset 0x01DC OEM File Loading Address Determine the memory base address to load a specified file from CSE file system after memory is available. **/ - uint32_t ObbLoadingBase; -/** Offset 0x0110 - OEM file name to load + uint32_t OemLoadingBase; +/** Offset 0x01E0 + OEM File Name to Load Specify a file name to load from CSE file system after memory is available. Empty indicates no file needs to be loaded. **/ - uint8_t ObbFileName[16]; -/** Offset 0x0120 -**/ - uint8_t UnusedUpdSpace4[48]; -/** Offset 0x0150 + uint8_t OemFileName[16]; +/** Offset 0x01F0 GPIO Table Pointer GPIO table pointer to a BL_GPIO_PAD_INIT structure. **/ struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; -/** Offset 0x0154 -**/ - uint8_t UnusedUpdSpace5[56]; -/** Offset 0x018C +/** Offset 0x01F4 **/ uint32_t ReservedMemoryInitUpd; } __attribute__((packed)); @@ -326,10 +503,10 @@ struct SILICON_INIT_UPD { **/ uint8_t UnusedUpdSpace2[13]; /** Offset 0x00B0 - ISP Enable/Disable - Enable/Disable ISP Device. + IPU Enable/Disable + Enable/Disable IPU Device. **/ - uint8_t IspEn; + uint8_t IpuEn; /** Offset 0x00B1 **/ uint8_t UnusedUpdSpace3[303]; @@ -356,7 +533,4 @@ struct SILICON_INIT_UPD { uint32_t ReservedSiliconInitUpd; } __attribute__((packed)); -#define FSP_IMAGE_ID 0x2450534654584224 /* '$BXTFSP$' */ -#define FSP_IMAGE_REV 0x00060000 - #endif

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Patch set updated for coreboot: soc/apollolake: Call MTRR setup and allocation in CPU init
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13365 -gerrit commit e2e466cad54a1433dff433932a3f2db7f5b3075d Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Nov 13 16:43:36 2015 -0800 soc/apollolake: Call MTRR setup and allocation in CPU init Change-Id: Ie64073c1c28f28f6b7f6fd465470d84511bf3744 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/cpu.c | 7 +++++++ 2 files changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index bdcacf2..bedbf07 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -2,6 +2,7 @@ ifeq ($(CONFIG_SOC_INTEL_APOLLOLAKE),y) subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/cache subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 8f3ccb3..de1e3cd 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -11,12 +11,19 @@ */ #include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> #include <device/pci.h> #include <soc/cpu.h> static void cpu_core_init(device_t cpu) { + /* Turn on cache */ + x86_enable_cache(); + /* Set up Memory Type Range Registers */ + x86_setup_mtrrs(); + x86_mtrr_check(); } static struct device_operations cpu_dev_ops = {

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit 833b1785033aacce72063e8c0626885a6e03e2e9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Nov 13 16:42:10 2015 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issues in a way designed to minimize boot time. Teardown currently takes about 7 ms, but that time can be cut to half a millisecond by excluding the fsp reserved memory range from the flushed ranges. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/car_teardown.c | 146 ++++++++++++++++++++++++++++++++ 2 files changed, 147 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 23a2151..bdcacf2 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -24,6 +24,7 @@ romstage-y += tsc_freq.c romstage-y += uart_early.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-y += car_teardown.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gpio.c diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..75c2e18 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,146 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <symbols.h> + +#define EVICT_CTL_MSR 0x2e0 + +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +struct mem_region { + uintptr_t start; + uintptr_t end; +}; + +/* Returns true if two memory regions overlap, or one contains the other */ +static bool mem_regions_overlap(const struct mem_region *a, + const struct mem_region *b) +{ + if ((a->end < b->start) || (b->end < a->start)) + return false; + + return true; +} + +/* Merge two regions into one. Assumes regions overlap */ +static void merge_regions(struct mem_region *a, struct mem_region *b) +{ + /* Merge second region into first */ + a->start = MIN(a->start, b->start); + a->end = MAX(a->end, b->end); + + /* Disable the second region */ + b->start = b->end = 0; +} + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, 64); + + for (start = ALIGN_DOWN(start, 64); start < end; start += 64) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + size_t cbmem_size; + struct mem_region ramstage, cbmem; + + /* Figure out where ramstage and cbmem reside */ + ramstage.start = (uintptr_t)&_program; + ramstage.end = (uintptr_t)&_eprogram; + + cbmem_region_used(&cbmem.start, &cbmem_size); + cbmem.end = cbmem.start + cbmem_size; + + if (mem_regions_overlap(&cbmem, &ramstage)) + merge_regions(&cbmem, &ramstage); + + /* TODO: Carve FSP reserved mem region out of flushable ranges */ + + /* Flush ramstage code and stack */ + clflush_mem_range(cbmem.start, cbmem.end); + clflush_mem_range(ramstage.start, ramstage.end); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(EVICT_CTL_MSR); + msr.lo &= ~2; + wrmsr(EVICT_CTL_MSR, msr); + + msr.lo &= ~1; + wrmsr(EVICT_CTL_MSR, msr); + + /* Re-enable remaining MSRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL);

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Patch set updated for coreboot: cbmem: Add utility to get memory region occupied by cbmem
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13363 -gerrit commit 0db7359853102957a084ab655fb67ba2e81cb706 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Mon Nov 16 13:26:33 2015 -0800 cbmem: Add utility to get memory region occupied by cbmem Change-Id: I8e57c23565f173afc0f4d450579b8bfb35aeb964 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/include/cbmem.h | 2 ++ src/lib/imd_cbmem.c | 7 +++++++ 2 files changed, 9 insertions(+) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index efaa44f..2e947a1 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -109,6 +109,8 @@ int cbmem_recovery(int s3resume); void *cbmem_add(u32 id, u64 size); /* Find a cbmem entry of a given id. These return NULL on failure. */ void *cbmem_find(u32 id); +/* Get location and size of CBMEM region in memory */ +void cbmem_region_used(uintptr_t *base, size_t *size); /* Indicate to each hook if cbmem is being recovered or not. */ typedef void (* const cbmem_init_hook_t)(int is_recovery); diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index 49faad9..4b07959 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -263,6 +263,13 @@ void *cbmem_entry_start(const struct cbmem_entry *entry) return imd_entry_at(imd, cbmem_to_imd(entry)); } +void cbmem_region_used(uintptr_t *base, size_t *size) +{ + void *baseptr; + imd_region_used(cbmem_get_imd(), &baseptr, size); + *base = (uintptr_t)baseptr; +} + void cbmem_add_bootmem(void) { void *base = NULL;

1 0

Patch set updated for coreboot: soc/apollolake: Properly mask northbridge base address registers
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13362 -gerrit commit b2f6bb47d1a61807fe3ed0faeeae50ba9318ec02 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 18 17:25:57 2015 -0800 soc/apollolake: Properly mask northbridge base address registers BDSM, BGSM, TOLUD, and TSEG registers only use bits [31:20] for the address, and the other bits are reserved. They should be masked off. Change-Id: Idb5b4e4a8b0711c19438cefe01191a00c4af5e5c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/memmap.c | 2 +- src/soc/intel/apollolake/northbridge.c | 31 +++++++++++++------------------ 2 files changed, 14 insertions(+), 19 deletions(-) diff --git a/src/soc/intel/apollolake/memmap.c b/src/soc/intel/apollolake/memmap.c index 7de6217..6cfd8ae 100644 --- a/src/soc/intel/apollolake/memmap.c +++ b/src/soc/intel/apollolake/memmap.c @@ -18,7 +18,7 @@ static uintptr_t smm_region_start(void) { - return pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & (~1); + return pci_read_config32(PCI_DEV(0, 0, 0), TSEG) & 0xfff00000; } void *cbmem_top(void) diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index fefc947..70355d0 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -3,6 +3,7 @@ * * Copyright (C) 2015 Intel Corp. * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -52,48 +53,42 @@ static int mc_add_fixed_mmio_resources(device_t dev, int index) static int mc_add_dram_resources(device_t dev, int index) { unsigned long base_k, size_k; + uint32_t bgsm, bdsm, tolud, tseg; struct resource *resource; - struct reserved_ram { - uint32_t bgsm; - uint32_t bdsm; - uint32_t tolud; - uint32_t tseg; - } aplk_reserved_ram; - - aplk_reserved_ram.bgsm = pci_read_config32(dev, BGSM); - aplk_reserved_ram.bdsm = pci_read_config32(dev, BDSM); - aplk_reserved_ram.tolud = pci_read_config32(dev, TOLUD); - aplk_reserved_ram.tseg = pci_read_config32(dev, TSEG); + bgsm = pci_read_config32(dev, BGSM) & 0xfff00000; + bdsm = pci_read_config32(dev, BDSM) & 0xfff00000; + tolud = pci_read_config32(dev, TOLUD) & 0xfff00000; + tseg = pci_read_config32(dev, TSEG) & 0xfff00000; /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ ram_resource(dev, index++, 0, 640); /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ base_k = 768; - size_k = (aplk_reserved_ram.tseg >> 10) - base_k; + size_k = (tseg >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); /* TSEG -> BGSM */ resource = new_resource(dev, index++); - resource->base = aplk_reserved_ram.tseg; - resource->size = aplk_reserved_ram.bgsm - resource->base; + resource->base = tseg; + resource->size = bgsm - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; /* BGSM -> BDSM */ resource = new_resource(dev, index++); - resource->base = aplk_reserved_ram.bgsm; - resource->size = aplk_reserved_ram.bdsm - resource->base; + resource->base = bgsm; + resource->size = bdsm - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; /* BDSM -> TOLUD */ resource = new_resource(dev, index++); - resource->base = aplk_reserved_ram.bdsm; - resource->size = aplk_reserved_ram.tolud - resource->base; + resource->base = bdsm; + resource->size = tolud - resource->base; resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED;

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Patch set updated for coreboot: soc/apollolake/uart: Keep track of console UART base address
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13361 -gerrit commit 78a0dab27e65370cc51fde56479dcfa8ff6bf359 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Nov 12 11:01:31 2015 -0800 soc/apollolake/uart: Keep track of console UART base address After the MMIO region for the console UART is relocated, uart_platform_base() no longer returns the updated location. The new base address is now tracked and updated before set_resources(), so that console remains operational. Change-Id: I136959391798b9c3b376b1173d6b7b78063bd013 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/uart.c | 44 ++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index 00bc45f..ec4b68c 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -11,14 +11,20 @@ */ #include <console/uart.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> /* - * TODO: We need a mechanism to return the new BAR once the resource allocator - * gives us a new location. + * Shadow BAR for console UART: + * This allows us to keep track of the actual MMIO region without needing to + * pci_dev_locate()/pci_read_config32() on every uart_platform_base() call. */ +static uintptr_t uart_bar = CONFIG_CONSOLE_UART_BASE_ADDRESS; + uintptr_t uart_platform_base(int idx) { - return (CONFIG_CONSOLE_UART_BASE_ADDRESS); + return uart_bar; } unsigned int uart_platform_refclk(void) @@ -26,3 +32,35 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static void update_uart_bar(struct device *dev) +{ + uart_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; +} + +static void uart_set_resources(struct device *dev) +{ + if (dev->path.pci.devfn == PCI_DEVFN(0x18, CONFIG_UART_FOR_CONSOLE)) + update_uart_bar(dev); + + pci_dev_set_resources(dev); +} + +static struct device_operations uart_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = uart_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable = DEVICE_NOOP +}; + +static const unsigned short uart_ids[] = { + 0x5abc, 0x5abe, 0x5ac0, 0x5aee, + 0 +}; + +static const struct pci_driver uart_driver __pci_driver = { + .ops = &uart_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = uart_ids +};

1 0

Patch set updated for coreboot: soc/apollolake: Add memory and reserve MMIO resources
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13360 -gerrit commit d07bb9289f35f14ced946be4048b41f9aca148cf Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Nov 10 13:52:29 2015 -0800 soc/apollolake: Add memory and reserve MMIO resources This adds most important MMIO reserved memory resources, real DRAM memory resources, and some DRAM resources that can not be used as RAM for whatever reason. Change-Id: Id5a80cf18d67ace991e8046fa46c4b7ed47c626a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/iomap.h | 1 + src/soc/intel/apollolake/include/soc/northbridge.h | 30 +++++ src/soc/intel/apollolake/northbridge.c | 141 +++++++++++++++++++++ 4 files changed, 173 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index e9f1079..23a2151 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -30,6 +30,7 @@ ramstage-y += gpio.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += northbridge.c ramstage-y += tsc_freq.c ramstage-y += uart.c diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 09ae67d..d12eb19 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -15,6 +15,7 @@ #define P2SB_BAR 0xd0000000 #define MCH_BASE_ADDR 0xfed10000 +#define MCH_BASE_SIZE (32 * KiB) #define ACPI_PMIO_BASE 0x400 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/include/soc/northbridge.h b/src/soc/intel/apollolake/include/soc/northbridge.h new file mode 100644 index 0000000..583e117 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/northbridge.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_NORTHBRIDGE_H_ +#define _SOC_APOLLOLAKE_NORTHBRIDGE_H_ + +#include <soc/iomap.h> + +#define MCHBAR 0x48 +#define PCIEXBAR 0x60 +#define PCIEX_SIZE (256 * MiB) + +#define BDSM 0xb0 /* Base Data Stolen Memory */ +#define BGSM 0xb4 /* Base GTT Stolen Memory */ +#define TSEG 0xb8 /* TSEG base */ +#define TOLUD 0xbc /* Top of Low Used Memory */ +#define TOUUD 0xa8 /* Top of Upper Usable DRAM */ + +#define MCH_APOLLOLAKE_ID 0x5af0 + +#endif /* _SOC_APOLLOLAKE_NORTHBRIDGE_H_ */ diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c new file mode 100644 index 0000000..fefc947 --- /dev/null +++ b/src/soc/intel/apollolake/northbridge.c @@ -0,0 +1,141 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <soc/iomap.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/northbridge.h> + +static uint32_t get_bar(device_t dev, unsigned int index) +{ + uint32_t bar; + + bar = pci_read_config32(dev, index); + + /* If not enabled return 0 else strip enabled bit */ + return (bar & 1) ? (bar & ~1) : 0; +} + +static int mc_add_fixed_mmio_resources(device_t dev, int index) +{ + struct resource *res; + + /* PCI extended config region */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* only last 4 bits encode BAR */ + res->base = get_bar(dev, PCIEXBAR) & 0xf0000000; + res->size = PCIEX_SIZE; + + /* Memory Controller HUB */ + res = new_resource(dev, index++); + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | + IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; + /* BITS 31:15 encode BAR */ + res->base = get_bar(dev, MCHBAR) & 0xffff8000; + res->size = MCH_BASE_SIZE; + return index; +} + + +static int mc_add_dram_resources(device_t dev, int index) +{ + unsigned long base_k, size_k; + struct resource *resource; + + struct reserved_ram { + uint32_t bgsm; + uint32_t bdsm; + uint32_t tolud; + uint32_t tseg; + } aplk_reserved_ram; + + aplk_reserved_ram.bgsm = pci_read_config32(dev, BGSM); + aplk_reserved_ram.bdsm = pci_read_config32(dev, BDSM); + aplk_reserved_ram.tolud = pci_read_config32(dev, TOLUD); + aplk_reserved_ram.tseg = pci_read_config32(dev, TSEG); + + /* 0 - > 0xa0000: 640kb of DOS memory. Not enough for anybody nowadays */ + ram_resource(dev, index++, 0, 640); + + /* 0xc0000 -> top_of_ram, skipping the legacy VGA region */ + base_k = 768; + size_k = (aplk_reserved_ram.tseg >> 10) - base_k; + ram_resource(dev, index++, base_k, size_k); + + /* TSEG -> BGSM */ + resource = new_resource(dev, index++); + resource->base = aplk_reserved_ram.tseg; + resource->size = aplk_reserved_ram.bgsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; + + /* BGSM -> BDSM */ + resource = new_resource(dev, index++); + resource->base = aplk_reserved_ram.bgsm; + resource->size = aplk_reserved_ram.bdsm - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* BDSM -> TOLUD */ + resource = new_resource(dev, index++); + resource->base = aplk_reserved_ram.bdsm; + resource->size = aplk_reserved_ram.tolud - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + + /* 0xa0000 - 0xbffff: legacy VGA */ + mmio_resource(dev, index++, 640, 128); + + /* 0xe0000 - 0xfffff: PAM area */ + reserved_ram_resource(dev, index++, 768, 256); + + return index; +} + +static void northbridge_read_resources(device_t dev) +{ + + int index = 0; + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + /* Add all fixed MMIO resources. */ + index = mc_add_fixed_mmio_resources(dev, index); + + /* Calculate and add DRAM resources. */ + mc_add_dram_resources(dev, index); +} + +static struct device_operations northbridge_ops = { + .read_resources = northbridge_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = DEVICE_NOOP, + .enable = DEVICE_NOOP +}; + +static const unsigned short northbridge_ids[] = { + MCH_APOLLOLAKE_ID, + 0 +}; + +static const struct pci_driver northbridge_driver __pci_driver = { + .ops = &northbridge_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = northbridge_ids +};

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Patch set updated for coreboot: drivers/fsp2_0: Implement FspNotify API
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13358 -gerrit commit b7ee3e34e0bf8baefe6bc305fc9392d195aafaa4 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Nov 6 17:26:20 2015 -0800 drivers/fsp2_0: Implement FspNotify API This adds FspNotify implementation. Please note, FSP blobset assumes FspNotify is called after SiliconInit. As result, this implementation relies on this fact and assumes SiliconInit is called first. Change-Id: I75ede529403d54b78caeca0517e139c3d81090e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + src/drivers/intel/fsp2_0/include/fsp/api.h | 8 +++++- src/drivers/intel/fsp2_0/notify.c | 41 ++++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/silicon_init.c | 6 ++++- 4 files changed, 54 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index e7081a7..adb5a7d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += hand_off_block.c romstage-y += util.c romstage-y += memory_init.c +ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-y += util.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index f51174f..6d2efd8 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -32,10 +32,16 @@ enum fsp_status { FSP_CRC_ERROR = 0x8000001b, }; +enum fsp_notify_phase { + AFTER_PCI_ENUM = 0x20, + READY_TO_BOOT = 0x40 +}; + + /* Main FSP stages */ enum fsp_status fsp_memory_init(void **hob_list); enum fsp_status fsp_silicon_init(void); -enum fsp_status fsp_notify(void); +enum fsp_status fsp_notify(enum fsp_notify_phase phase); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd); diff --git a/src/drivers/intel/fsp2_0/notify.c b/src/drivers/intel/fsp2_0/notify.c new file mode 100644 index 0000000..c5f06db --- /dev/null +++ b/src/drivers/intel/fsp2_0/notify.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <string.h> + +typedef struct fsp_notify_params { + enum fsp_notify_phase phase; +} NOTIFY_PHASE_PARAMS; + +typedef asmlinkage enum fsp_status (*fsp_notify_fn) + (struct fsp_notify_params *); + +struct fsp_header *fsps_hdr = NULL; + +enum fsp_status fsp_notify(enum fsp_notify_phase phase) +{ + fsp_notify_fn fspnotify = NULL; + + if (!fsps_hdr) + return FSP_NOT_FOUND; + + fspnotify = (void*) (fsps_hdr->image_base + + fsps_hdr->notify_phase_entry_offset); + + printk(BIOS_DEBUG, "FspNotify %x\n", (uint32_t) phase); + + return fspnotify((struct fsp_notify_params *) &phase); +} diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index d600635..575c2eb 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -19,6 +19,7 @@ typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) (struct SILICON_INIT_UPD *upd); +extern struct fsp_header *fsps_hdr; static enum fsp_status do_silicon_init(struct fsp_header *hdr) { @@ -43,11 +44,14 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) enum fsp_status fsp_silicon_init(void) { - struct fsp_header hdr; + static struct fsp_header hdr; if (fsp_load_binary(&hdr, "blobs/fsp-s.bin") != CB_SUCCESS) return FSP_NOT_FOUND; + /* save the FSPS header, it will come in handy during notify */ + fsps_hdr = &hdr; + return do_silicon_init(&hdr); }

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coreboot-gerrit January 2016