coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add missing IRQ route to mptable
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13163 -gerrit commit 2f47bca5d639e0d5d1c9e1bededfef588e857f8a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:00 2015 -0600 mainboard/asus/kgpe-d16: Add missing IRQ route to mptable The IOMMU/HT device was not routed correctly; add the proper APIC mappting to the mptable generation code. Also clarify comments surrounding the pin mappings. Change-Id: I72ceb0f22dabdfa71a1f6231ccb841face08ff7a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/mptable.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/mptable.c b/src/mainboard/asus/kgpe-d16/mptable.c index a6ed5c9..c869d31 100644 --- a/src/mainboard/asus/kgpe-d16/mptable.c +++ b/src/mainboard/asus/kgpe-d16/mptable.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 Raptor Engineering * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -47,7 +47,10 @@ static void *smp_write_config_table(void *v) get_bus_conf(); - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; mptable_write_buses(mc, NULL, &bus_isa); @@ -122,13 +125,14 @@ static void *smp_write_config_table(void *v) mptable_add_isa_interrupts(mc, bus_isa, apicid_sp5100, 0); /* SR5650 devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG) */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((0)<<2)|(2)), apicid_sr5650, 31); /* Device 0 Function 2 (LNKA, APIC pin 31) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((2)<<2)|(0)), apicid_sr5650, 28); /* Device 2 (LNKE, APIC pin 28) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((4)<<2)|(0)), apicid_sr5650, 28); /* Device 4 (LNKF, APIC pin 28) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((9)<<2)|(0)), apicid_sr5650, 29); /* Device 9 (LNKG, APIC pin 29) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((10)<<2)|(0)), apicid_sr5650, 30); /* Device 10 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((11)<<2)|(0)), apicid_sr5650, 30); /* Device 11 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((12)<<2)|(0)), apicid_sr5650, 30); /* Device 12 (LNKG, APIC pin 30) */ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0, (((13)<<2)|(0)), apicid_sr5650, 30); /* Device 13 (LNKG, APIC pin 30)) */ dev = dev_find_slot(0, PCI_DEVFN(0x2, 0)); if (dev && dev->enabled) {

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Patch set updated for coreboot: superio/winbond/w83667hg-a: Add support for W83667HG-A
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13156 -gerrit commit 7b9ad25e7c4eb2ee64de5c8cd504791dc9b042b7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:57 2015 -0600 superio/winbond/w83667hg-a: Add support for W83667HG-A The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While the Nuvoton NCT5572D is effectively the same core, and a close enough match to get things working initially, the W83667HG-A has a different LDN mapping and several extra features that require a separate support driver. Clone the Nuvoton NCT5572D and modify according to the W83667HG-A datasheet, version 1.4. Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/superio/winbond/Kconfig | 4 + src/superio/winbond/Makefile.inc | 1 + src/superio/winbond/w83667hg-a/Makefile.inc | 19 +++++ src/superio/winbond/w83667hg-a/superio.c | 110 ++++++++++++++++++++++++++++ src/superio/winbond/w83667hg-a/w83667hg-a.h | 47 ++++++++++++ 5 files changed, 181 insertions(+) diff --git a/src/superio/winbond/Kconfig b/src/superio/winbond/Kconfig index ba9f479..1731a7f 100644 --- a/src/superio/winbond/Kconfig +++ b/src/superio/winbond/Kconfig @@ -39,6 +39,10 @@ config SUPERIO_WINBOND_W83627UHG bool select SUPERIO_WINBOND_COMMON_ROMSTAGE +config SUPERIO_WINBOND_W83667HG_A + bool + select SUPERIO_WINBOND_COMMON_ROMSTAGE + config SUPERIO_WINBOND_W83697HF bool select SUPERIO_WINBOND_COMMON_ROMSTAGE diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index 67927dc..ae4b283 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -21,6 +21,7 @@ subdirs-y += w83627ehg subdirs-y += w83627hf subdirs-y += w83627thg subdirs-y += w83627uhg +subdirs-y += w83667hg-a subdirs-y += w83697hf subdirs-y += w83977tf subdirs-y += wpcd376i diff --git a/src/superio/winbond/w83667hg-a/Makefile.inc b/src/superio/winbond/w83667hg-a/Makefile.inc new file mode 100644 index 0000000..7665046 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +## Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> +## Copyright (C) 2015 Raptor Engineering +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_WINBOND_W83667HG_A) += superio.c diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c new file mode 100644 index 0000000..96eddd7 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -0,0 +1,110 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Copyright (C) 2015 - 2016 Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <pc80/keyboard.h> +#include <pc80/mc146818rtc.h> +#include <stdlib.h> +#include <superio/conf_mode.h> + +#include "w83667hg-a.h" + +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 + +#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL +#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON +#endif + +static void w83667hg_a_init(struct device *dev) +{ + uint8_t byte; + uint8_t power_status; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case W83667HG_A_KBC: + pc_keyboard_init(); + break; + case W83667HG_A_ACPI: + /* Set power state after power fail */ + power_status = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL; + get_option(&power_status, "power_on_after_fail"); + pnp_enter_conf_mode_8787(dev); + pnp_set_logical_device(dev); + byte = pnp_read_config(dev, 0xe4); + byte &= ~0x60; + if (power_status == 1) + byte |= (0x1 << 5); /* Force power on */ + else if (power_status == 2) + byte |= (0x2 << 5); /* Use last power state */ + pnp_write_config(dev, 0xe4, byte); + pnp_exit_conf_mode_aa(dev); + printk(BIOS_INFO, "set power %s after power fail\n", power_status ? "on" : "off"); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = w83667hg_a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, W83667HG_A_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, W83667HG_A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, W83667HG_A_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83667HG_A_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83667HG_A_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, W83667HG_A_SPI, PNP_IO1, {0x0ff8, 0}}, + { &ops, W83667HG_A_WDT1}, + { &ops, W83667HG_A_ACPI}, + { &ops, W83667HG_A_HWM_TSI, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, }, + { &ops, W83667HG_A_PECI}, + { &ops, W83667HG_A_VID_BUSSEL}, + { &ops, W83667HG_A_GPIO_PP_OD}, + { &ops, W83667HG_A_GPIO1}, + { &ops, W83667HG_A_GPIO2}, + { &ops, W83667HG_A_GPIO3}, + { &ops, W83667HG_A_GPIO4}, + { &ops, W83667HG_A_GPIO5}, + { &ops, W83667HG_A_GPIO6}, + { &ops, W83667HG_A_GPIO7}, + { &ops, W83667HG_A_GPIO8}, + { &ops, W83667HG_A_GPIO9}, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_winbond_w83667hg_a_ops = { + CHIP_NAME("WINBOND W83667HG-A Super I/O") + .enable_dev = enable_dev, +}; diff --git a/src/superio/winbond/w83667hg-a/w83667hg-a.h b/src/superio/winbond/w83667hg-a/w83667hg-a.h new file mode 100644 index 0000000..efb77b8 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/w83667hg-a.h @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Felix Held <felix-coreboot(a)felixheld.de> + * Copyright (C) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_WINBOND_W83667HG_A +#define SUPERIO_WINBOND_W83667HG_A + +/* Logical Device Numbers (LDN). */ +#define W83667HG_A_FDC 0x00 +#define W83667HG_A_PP 0x01 +#define W83667HG_A_SP1 0x02 /* Com1 */ +#define W83667HG_A_SP2 0x03 /* Com2 */ +#define W83667HG_A_KBC 0x05 +#define W83667HG_A_SPI 0x06 +#define W83667HG_A_GPIO6789_V 0x07 +#define W83667HG_A_WDT1 0x08 +#define W83667HG_A_GPIO2345_V 0x09 +#define W83667HG_A_ACPI 0x0A +#define W83667HG_A_HWM_TSI 0x0B /* HW monitor/SB-TSI/deep S5 */ +#define W83667HG_A_PECI 0x0C +#define W83667HG_A_VID_BUSSEL 0x0D /* VID and BUSSEL */ +#define W83667HG_A_GPIO_PP_OD 0x0F /* GPIO Push-Pull/Open drain select */ + +/* virtual LDN for GPIO */ +#define W83667HG_A_GPIO2 ((0 << 8) | W83667HG_A_GPIO2345_V) +#define W83667HG_A_GPIO3 ((1 << 8) | W83667HG_A_GPIO2345_V) +#define W83667HG_A_GPIO4 ((2 << 8) | W83667HG_A_GPIO2345_V) +#define W83667HG_A_GPIO5 ((3 << 8) | W83667HG_A_GPIO2345_V) +#define W83667HG_A_GPIO6 ((1 << 8) | W83667HG_A_GPIO6789_V) +#define W83667HG_A_GPIO7 ((2 << 8) | W83667HG_A_GPIO6789_V) +#define W83667HG_A_GPIO8 ((3 << 8) | W83667HG_A_GPIO6789_V) +#define W83667HG_A_GPIO9 ((4 << 8) | W83667HG_A_GPIO6789_V) + +#endif /* SUPERIO_WINBOND_W83667HG_A */

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13157 -gerrit commit baadf456057fe4f26a0a4b974cadfa17c2fe01c3 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:57 2015 -0600 mainboard/asus/kgpe-d16: Use W83667HG-A SuperIO instead of NCT5572D Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/Kconfig | 2 +- src/mainboard/asus/kgpe-d16/devicetree.cb | 16 +++++++++------- src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++---- 3 files changed, 14 insertions(+), 12 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index f394ca9..23c91f0 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -12,7 +12,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_SB700 select SOUTHBRIDGE_AMD_SB700_DISABLE_ISA_DMA select SOUTHBRIDGE_AMD_SUBTYPE_SP5100 - select SUPERIO_NUVOTON_NCT5572D + select SUPERIO_WINBOND_W83667HG_A select PARALLEL_CPU_INIT select HAVE_ROMSTAGE_CONSOLE_SPINLOCK select HAVE_ROMSTAGE_NVRAM_CBFS_SPINLOCK diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 96372f9..8d64ac7 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -177,24 +177,27 @@ chip northbridge/amd/amdfam10/root_complex # Root complex device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) - chip superio/nuvoton/nct5572d # Super I/O + chip superio/winbond/w83667hg-a # Super I/O device pnp 2e.0 off end # FDC; Not available on the KGPE-D16 device pnp 2e.1 off end # LPT1; Not available on the KGPE-D16 device pnp 2e.2 on # Com1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.3 off end # IR: Not available on the KGPE-D16 + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end device pnp 2e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR: Not available on the KGPE-D16 - device pnp 2e.7 off end # GIPO689 + device pnp 2e.6 off end # SPI: Not available on the KGPE-D16 + device pnp 2e.7 off end # GIPO6789 device pnp 2e.8 off end # WDT - device pnp 2e.9 off end # GPIO235 + device pnp 2e.9 off end # GPIO2345 device pnp 2e.a on end # ACPI device pnp 2e.b on # HW Monitor io 0x60 = 0x290 @@ -202,8 +205,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex irq 0x70 = 5 end device pnp 2e.c off end # PECI - device pnp 2e.d off end # SUSLED - device pnp 2e.e off end # CIRWKUP + device pnp 2e.d off end # VID_BUSSEL device pnp 2e.f off end # GPIO_PP_OD end end diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index 13af96f..89183cc 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -35,8 +35,8 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdfam10/reset_test.c" -#include <superio/nuvoton/common/nuvoton.h> -#include <superio/nuvoton/nct5572d/nct5572d.h> +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <cpu/x86/bist.h> #include <smp/spinlock.h> // #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -46,7 +46,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, NCT5572D_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) static void activate_spd_rom(const struct mem_controller *ctrl); @@ -393,7 +393,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_pci_port80(); /* Initialize early serial */ - nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Disable LPC legacy DMA support to prevent lockup */

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Patch set updated for coreboot: cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabled
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13158 -gerrit commit 0d760df309e101e033ed7ebea8393403557e3b6c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 cpu/amd/fam10h-15h: Fix Family 15h boot hang when BSP lift enabled The existing code did not allow for the second core of the BSP to reside on an APIC ID other than 1, leading to a boot hang on Family 15h processors when APIC_ID_OFFSET was set to anything other than 0. Furthermore, insufficient AP stack space was allocated for AP start. Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/Kconfig | 2 +- src/cpu/amd/family_10h-family_15h/init_cpus.c | 8 +++++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index bfb6751..2f3dfc0 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -48,7 +48,7 @@ config DCACHE_BSP_STACK_SLUSH config DCACHE_AP_STACK_SIZE hex - default 0x400 + default 0x500 config UDELAY_IO bool diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 5a67601..e8e81d2 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -356,6 +356,7 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) uint32_t dword; uint8_t set_mtrrs; uint8_t node_count; + uint8_t fam15_bsp_core1_apicid; struct node_core_id id; /* Please refer to the calculations and explaination in cache_as_ram.inc before modifying these values */ @@ -483,7 +484,12 @@ static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) if (is_fam15h()) { /* core 1 on node 0 is special; to avoid corrupting the * BSP do not alter MTRRs on that core */ - if (apicid == 1) + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1; + else + fam15_bsp_core1_apicid = 1; + + if (apicid == fam15_bsp_core1_apicid) set_mtrrs = 0; else set_mtrrs = !!(apicid & 0x1);

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Patch set updated for coreboot: southbridge/amd/sb700: Set HPET min tick value to RPR recommendation
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13159 -gerrit commit 4e1bc68a33b8573f1b015201da31331e235989ea Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:58 2015 -0600 southbridge/amd/sb700: Set HPET min tick value to RPR recommendation Change-Id: I766eca6369b60a79a6823bc744934e3f1fbc17b2 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/southbridge/amd/sb700/Kconfig b/src/southbridge/amd/sb700/Kconfig index 9a0ddb2..9a988a9 100644 --- a/src/southbridge/amd/sb700/Kconfig +++ b/src/southbridge/amd/sb700/Kconfig @@ -50,4 +50,8 @@ config EHCI_BAR hex default 0xfef00000 +config HPET_MIN_TICKS + hex + default 0x14 + endif # SOUTHBRIDGE_AMD_SB700

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable ASUS MIO audio option
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13152 -gerrit commit 5dc0dda0cd07ed2da7de314124a23889e04ee3ee Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:55 2015 -0600 mainboard/asus/kgpe-d16: Enable ASUS MIO audio option The KGPE-D16 supports an optional MIO audio card, which connects to the on-board HDA interface of the SP5100. Enable the HDA interface for use with the MIO card. Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 014a35f..96372f9 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -175,7 +175,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex end end device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) + device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) chip superio/nuvoton/nct5572d # Super I/O device pnp 2e.0 off end # FDC; Not available on the KGPE-D16

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13153 -gerrit commit 3aceda700efb2482c404fa131662762c5e11f865 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:55 2015 -0600 mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 43 +++--------------------------------- 1 file changed, 3 insertions(+), 40 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 8445eb3..44b6a98 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -92,8 +92,8 @@ DefinitionBlock ( /* Keyboard controller PME# */ Method(_L08) { /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } @@ -490,44 +490,7 @@ DefinitionBlock ( Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, EisaId ("PNP030B")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F03")) - Name (_CID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - + #include "../../../drivers/pc80/ps2_controller.asl" /* UART 1 */ Device (URT1)

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Patch set updated for coreboot: southbridge/amd/sb700: Add missing DMA setup step from AMD RRG
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13154 -gerrit commit 0b40a4007ca50e687364dcc25cfc1159d551d9fb Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:56 2015 -0600 southbridge/amd/sb700: Add missing DMA setup step from AMD RRG Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 3733314..76855fb 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -420,6 +420,11 @@ static void sb700_devices_por_init(void) /* Legacy DMA Prefetch Enhancement, CIM masked it. */ /* pci_write_config8(dev, 0x43, 0x1); */ + /* Enable DMA verify bugfix */ + byte = pci_read_config8(dev, 0x67); + byte |= 0x1 << 1; + pci_write_config8(dev, 0x67, byte); + /* Disabling Legacy USB Fast SMI# */ byte = pci_read_config8(dev, 0x62); byte |= 0x24;

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Patch set updated for coreboot: southbridge/amd/sb700: Add CMOS option to disable legacy USB support
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13155 -gerrit commit 7017e7e8f07102773fdb2070c8d4b1a13ba1d373 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:56 2015 -0600 southbridge/amd/sb700: Add CMOS option to disable legacy USB support Change-Id: I136c259136ce66a0c319a965ae0ee27f66dce1b3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sm.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 7c9c004..5f6d20e 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -66,6 +66,7 @@ static void sm_init(device_t dev) u32 dword; void *ioapic_base; uint32_t power_state; + uint32_t enable_legacy_usb; u32 nmi_option; printk(BIOS_INFO, "sm_init().\n"); @@ -75,10 +76,23 @@ static void sm_init(device_t dev) ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ + enable_legacy_usb = 1; + get_option(&enable_legacy_usb, "enable_legacy_usb"); + /* 2.10 Interrupt Routing/Filtering */ - dword = pci_read_config8(dev, 0x62); - dword |= 3; - pci_write_config8(dev, 0x62, dword); + byte = pci_read_config8(dev, 0x62); + if (enable_legacy_usb) + byte |= 0x3; + else + byte &= ~0x3; + pci_write_config8(dev, 0x62, byte); + + byte = pci_read_config8(dev, 0x67); + if (enable_legacy_usb) + byte |= 0x1 << 7; + else + byte &= ~(0x1 << 7); + pci_write_config8(dev, 0x67, byte); /* Delay back to back interrupts to the CPU. */ dword = pci_read_config16(dev, 0x64);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Move memory test before IMD setup
by Timothy Pearson 26 Jan '16

26 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13151 -gerrit commit 9177bbca852766ed46e17a8bf859615fb02042f2 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:54 2015 -0600 mainboard/asus/kgpe-d16: Move memory test before IMD setup Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index c29ac5f..13af96f 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -541,6 +541,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); +#ifdef TEST_MEMORY + execute_memory_test(); +#endif + #if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) if (s3resume) cbmem_initialize(); @@ -565,10 +569,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_add_now(TS_END_ROMSTAGE); -#ifdef TEST_MEMORY - execute_memory_test(); -#endif - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }

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coreboot-gerrit January 2016