coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

1 participants
2471 discussions

Patch set updated for coreboot: mainboard/apollolake_rvp: Configure backlight control GPIOs
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13379 -gerrit commit a4030115f87d379811d21d628ff0456cc0103ff6 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Dec 9 16:52:35 2015 -0800 mainboard/apollolake_rvp: Configure backlight control GPIOs It is unclear whether FSP expects the backlight control pads to be pre-configured, or whether it configures them itself. We explicitly configure them for several reasons: * document the GPIO configuration of the board * to be consistent with other peripherals (eg. UART) * future-proof against FSP updates which expect pre-configured pads Change-Id: Ie4f9be8b35fa1396fdf4fc438a22e1fbc1dac40c Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/mainboard.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index 3ed3d8f..e82f4a5 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -17,6 +17,9 @@ static const struct pad_config aplk_rvp_gpios[] = { PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ + PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */ + PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */ + PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */ }; static void mainboard_enable(struct device *dev)

1 0

Patch set updated for coreboot: mainboard/apollolake_rvp: Configure GPIOs earlier, in .init
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13380 -gerrit commit 8f5baf80dbd5dc9169ef162423d07cfa1bdf2370 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Dec 9 16:54:41 2015 -0800 mainboard/apollolake_rvp: Configure GPIOs earlier, in .init The .init function gets called very early on, as opposed to .enable_dev, which will get called after resource allocation. Moving GPIO configuration to mainboard .init gives it precedence over the SOC .init, and therefore is called before fsp_silicon_init(). Change-Id: I7cc62d11f8c49c9eb77f75a307fe47374744e3eb Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index e82f4a5..b437f74 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -22,11 +22,11 @@ static const struct pad_config aplk_rvp_gpios[] = { PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */ }; -static void mainboard_enable(struct device *dev) +static void mainboard_init(void *chip_info) { gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .init = mainboard_init, };

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Link hand-off-block utilities in ramstage
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13381 -gerrit commit 7c3740bb1e67e3097deaacebb1ff0076a72fcd0b Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 12:53:01 2015 -0800 drivers/intel/fsp2_0: Link hand-off-block utilities in ramstage This will be needed later to, for example, parse the graphics info hand-off-block. Change-Id: I2438de68daf491113cc53e6e0ea765c2b7c876bd Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index adb5a7d..ffb3c4c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += hand_off_block.c romstage-y += util.c romstage-y += memory_init.c +ramstage-y += hand_off_block.c ramstage-y += notify.c ramstage-y += silicon_init.c ramstage-y += util.c

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add utility to get extension handoff-blocks
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13382 -gerrit commit 8ff4ae8b6f3a2f7d903714e719db4109789f1a30 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 12:55:56 2015 -0800 drivers/intel/fsp2_0: Add utility to get extension handoff-blocks Some handoff blocks(HOB) contain useful information (e.g. framebuffer). Since every extension HOB has a uuid, the utility uses this to uniquely identify a HOB. Change-Id: Ic1f35cb14be37a213749bfdca301d88b6025e310 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 36 +++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + 2 files changed, 37 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 8529b58..7e47525 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -123,6 +123,19 @@ static const void *hob_header_to_struct(const struct hob_header *hob) return hob_walker.hob_descr; } +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + static const struct hob_resource *hob_header_to_resource(const struct hob_header *hob) { @@ -228,3 +241,26 @@ void fsp_print_memory_resource_hobs(const void *hob_list) print_resource_descriptor(hob); } } + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 0e3f412..4c47987 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -22,6 +22,7 @@ */ void fsp_save_hob_list(void *hob_list_ptr); const void *fsp_get_hob_list(void); +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); /* * Hand-off-block utilities which do not depend on CBMEM, but need to be passed * the HOB list explicitly.

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0/Kconfig: Use "depends on" instead of "if"
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13383 -gerrit commit 4e629983f55465a9130cc5871882f9b9c274d7a4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 14:55:29 2015 -0800 drivers/intel/fsp2_0/Kconfig: Use "depends on" instead of "if" When FSP_M_FILE and FSP_S_FILE are depended with "depends on" instead of being stuffed in an "if" block, they appear indented under the ADD_FSP_BINARIES option, at least with xconfig. This makes configuration easier to understand. Change-Id: Ib28261a84bc5f0184ad36dfef5a19f6c844acf91 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 0103921..3c81eb9 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -13,19 +13,18 @@ config ADD_FSP_BINARIES Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not use the FSP-T binary, so that will not be included. -if ADD_FSP_BINARIES - config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE string "Intel FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES help The path and filename of the Intel FSP-S binary for this platform. -endif # ADD_FSP_BINARIES config FIT_CAR_ADDR hex

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Load and pass Video Bios Table to FSP
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13384 -gerrit commit 9023c8f897e0779f4e50fc6633ae2dbbcfe4829f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 14:55:01 2015 -0800 drivers/intel/fsp2_0: Load and pass Video Bios Table to FSP The Video Bios Table is needed by FSP to initialize the display. Change-Id: Ieae32811d371c10b8c81a5eabe12ee2cb2b2b2f8 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 13 +++++++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 4 ++++ src/drivers/intel/fsp2_0/silicon_init.c | 14 ++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3c81eb9..b367b78 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -26,6 +26,19 @@ config FSP_S_FILE The path and filename of the Intel FSP-S binary for this platform. +config ADD_VBT_DATA_FILE + bool "Add a Video Bios Table (VBT) binary to CBFS" + help + Add a VBT file data file to CBFS. The VBT describes the integrated + GPU and connections, and is needed by FSP in order to initialize the + display. + +config VBT_FILE + string "VBT binary path and filename" + depends on ADD_VBT_DATA_FILE + help + The path and filename of the VBT binary for this platform. + config FIT_CAR_ADDR hex default 0xfef27c00 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index ffb3c4c..d210c21 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -17,3 +17,7 @@ blobs/fsp-m.bin-type := raw cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += blobs/fsp-s.bin blobs/fsp-s.bin-file := $(call strip_quotes,$(CONFIG_FSP_S_FILE)) blobs/fsp-s.bin-type := raw + +cbfs-files-$(CONFIG_ADD_VBT_DATA_FILE) += vbt.bin +vbt.bin-file := $(call strip_quotes,$(CONFIG_VBT_FILE)) +vbt.bin-type := raw diff --git a/src/drivers/intel/fsp2_0/silicon_init.c b/src/drivers/intel/fsp2_0/silicon_init.c index 575c2eb..8730845 100644 --- a/src/drivers/intel/fsp2_0/silicon_init.c +++ b/src/drivers/intel/fsp2_0/silicon_init.c @@ -11,6 +11,7 @@ */ #include <arch/cpu.h> +#include <cbfs.h> #include <console/console.h> #include <fsp/api.h> #include <fsp/util.h> @@ -21,6 +22,17 @@ typedef asmlinkage enum fsp_status (*fsp_silicon_init_fn) extern struct fsp_header *fsps_hdr; +static uintptr_t load_vbt(void) +{ + void *vbt; + + vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); + if (!vbt) + printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + + return (uintptr_t)vbt; +} + static enum fsp_status do_silicon_init(struct fsp_header *hdr) { struct SILICON_INIT_UPD silicon_upd, *upd_region; @@ -34,6 +46,8 @@ static enum fsp_status do_silicon_init(struct fsp_header *hdr) silicon_init = (void *)(hdr->image_base + hdr->silicon_init_entry_offset); + /* Load VBT first, in case platform callback wishes to patch it */ + silicon_upd.GraphicsConfigPtr = load_vbt(); /* give a chance to populate entries */ platform_fsp_silicon_init_params_cb(&silicon_upd);

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: Add utility to parse framebuffer info
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13385 -gerrit commit eb2026aecc6e3de1038cb397eb475d193974cc4d Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 15:26:10 2015 -0800 drivers/intel/fsp2_0: Add utility to parse framebuffer info If graphics initialization was succesful, FSP silicon_init will add a hand-off block containing the description of the framebuffer. Add a utility to parse this block to a struct lb_framebuffer entry. Change-Id: I9efcd9f6e0b867cd23b9c9772604411872754c63 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Makefile.inc | 1 + src/drivers/intel/fsp2_0/graphics.c | 93 +++++++++++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 2 + 3 files changed, 96 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d210c21..404f251 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -3,6 +3,7 @@ romstage-y += hand_off_block.c romstage-y += util.c romstage-y += memory_init.c +ramstage-y += graphics.c ramstage-y += hand_off_block.c ramstage-y += notify.c ramstage-y += silicon_init.c diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c new file mode 100644 index 0000000..e7e918b --- /dev/null +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +enum pixel_format { + pixel_rgbx_8bpc = 0, + pixel_bgrx_8bpc = 1, + pixel_bitmask = 2, /* defined by <rgb>_mask values */ +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +struct hob_graphics_info { + uint64_t framebuffer_base; + uint32_t framebuffer_size; + uint32_t version; + uint32_t horizontal_resolution; + uint32_t vertical_resolution; + uint32_t pixel_format; /* See enum pixel_format */ + uint32_t red_mask; + uint32_t green_mask; + uint32_t blue_mask; + uint32_t reserved_mask; + uint32_t pixels_per_scanline; +} __attribute__((packed)); + +struct pixel { + uint8_t pos; + uint8_t size; +}; + +static const struct fsp_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} fsp_framebuffer_format_map[] = { + [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + size_t size; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; + + ginfo = fsp_find_extension_hob_by_uuid(uuid_graphics_info, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return CB_ERR; + } + + if (ginfo->pixel_format > ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return CB_ERR; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + framebuffer->physical_address = ginfo->framebuffer_base; + framebuffer->x_resolution = ginfo->horizontal_resolution; + framebuffer->y_resolution = ginfo->vertical_resolution; + framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; + framebuffer->bits_per_pixel = 32; + framebuffer->red_mask_pos = fbinfo->red.pos; + framebuffer->red_mask_size = fbinfo->red.size; + framebuffer->green_mask_pos = fbinfo->green.pos; + framebuffer->green_mask_size = fbinfo->green.size; + framebuffer->blue_mask_pos = fbinfo->blue.pos; + framebuffer->blue_mask_size = fbinfo->blue.size; + framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; + framebuffer->reserved_mask_size = fbinfo->rsvd.pos; + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + return CB_SUCCESS; +} diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 4c47987..cdade32 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -13,6 +13,7 @@ #ifndef _FSP2_0_UTIL_H_ #define _FSP2_0_UTIL_H_ +#include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <device/resource.h> @@ -23,6 +24,7 @@ void fsp_save_hob_list(void *hob_list_ptr); const void *fsp_get_hob_list(void); const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); /* * Hand-off-block utilities which do not depend on CBMEM, but need to be passed * the HOB list explicitly.

1 0

Patch set updated for coreboot: soc/intel/apollolake/romstage: Save hand-off block list in CBMEM
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13386 -gerrit commit 35f29b97cce5da2002a5bafb69c133638f72b1dd Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 15:55:35 2015 -0800 soc/intel/apollolake/romstage: Save hand-off block list in CBMEM This list is needed by ramstage, and the FSP wrapper expects that it is saved by the platform code. Change-Id: Iab9b64958027f53d0146fa91b6ffd8219711dfd4 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/romstage/romstage.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 2a4b2ff..0c89094 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -95,6 +95,9 @@ asmlinkage void* romstage_entry(void) if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) die("Failed to accommodate FSP reserved memory request"); + /* Now that CBMEM is up, save the list so ramstage can use it */ + fsp_save_hob_list(hob_list_ptr); + return realloc_stack(); }

1 0

Patch set updated for coreboot: soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13387 -gerrit commit d4c30135fb7c605ee6894227d22f4c972a14a8f4 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 15 16:06:15 2015 -0800 soc/intel/apollolake: Write LB_FRAMEBUFFER table when appropriate FSP does not itself write the LB_FRAMEBUFFER entry, so that needs to be done in platform code. Change-Id: Ie678249fb0620e776b07a3aa2d4bcde25171cbde Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/graphics.c | 25 +++++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index bedbf07..af0bd56 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -29,6 +29,7 @@ ramstage-y += car_teardown.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += gpio.c +ramstage-y += graphics.c ramstage-y += lpc.c ramstage-y += memmap.c ramstage-y += mmap_boot.c diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c new file mode 100644 index 0000000..7b9a75c --- /dev/null +++ b/src/soc/intel/apollolake/graphics.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <console/console.h> +#include <fsp/util.h> + +void lb_framebuffer(struct lb_header *header) +{ + enum cb_err ret; + struct lb_framebuffer *framebuffer; + + framebuffer = (void *)lb_new_record(header); + ret = fsp_fill_lb_framebuffer(framebuffer); + if (ret != CB_SUCCESS) + printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); +}

1 0

Patch set updated for coreboot: soc/apollolake: Consolidate PCI IDs into one include file
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13388 -gerrit commit fb98553bba7bc8ef8c7059646def14c5301d0bfa Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Dec 23 11:53:01 2015 -0800 soc/apollolake: Consolidate PCI IDs into one include file Change-Id: I31d7a8886b74b4406cbb8fec56cb648f76c76207 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/include/soc/pci_ids.h | 39 ++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 8 ++---- src/soc/intel/apollolake/northbridge.c | 8 ++---- src/soc/intel/apollolake/uart.c | 4 ++- 4 files changed, 46 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h new file mode 100644 index 0000000..4ef7e11 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -0,0 +1,39 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_PCI_IDS_H_ +#define _SOC_APOLLOLAKE_PCI_IDS_H_ + +#define PCI_DEV_ID_APOLLOLAKE_NB 0x5af0 /* 00:00.0 */ +#define PCI_DEV_ID_APOLLOLAKE_IGD 0x5a84 /* 00:02.0 */ +#define PCI_DEV_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ +#define PCI_DEV_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ +#define PCI_DEV_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ +#define PCI_DEV_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C3 0x5ab2 /* 00:16.3 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C4 0x5ab4 /* 00:17.0 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C5 0x5ab6 /* 00:17.1 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C6 0x5ab8 /* 00:17.2 */ +#define PCI_DEV_ID_APOLLOLAKE_I2C7 0x5aba /* 00:17.3 */ +#define PCI_DEV_ID_APOLLOLAKE_UART0 0x5abc /* 00:18.0 */ +#define PCI_DEV_ID_APOLLOLAKE_UART1 0x5abe /* 00:18.0 */ +#define PCI_DEV_ID_APOLLOLAKE_UART2 0x5ac0 /* 00:18.0 */ +#define PCI_DEV_ID_APOLLOLAKE_UART3 0x5aee /* 00:18.0 */ +#define PCI_DEV_ID_APOLLOLAKE_SPI0 0x5ac2 /* 00:19.0 */ +#define PCI_DEV_ID_APOLLOLAKE_SPI1 0x5ac4 /* 00:19.1 */ +#define PCI_DEV_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ +#define PCI_DEV_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ + +#endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6d2e8ca..120b0e9 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -14,6 +14,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> +#include <soc/pci_ids.h> static void soc_lpc_add_io_resources(device_t dev) { @@ -42,13 +43,8 @@ static struct device_operations device_ops = { .write_acpi_tables = southbridge_write_acpi_tables, }; -static const unsigned short pci_device_ids[] = { - 0x5AE8, - 0 -}; - static const struct pci_driver soc_lpc __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, + .device = PCI_DEV_ID_APOLLOLAKE_LPC, }; diff --git a/src/soc/intel/apollolake/northbridge.c b/src/soc/intel/apollolake/northbridge.c index 70355d0..eccfe23 100644 --- a/src/soc/intel/apollolake/northbridge.c +++ b/src/soc/intel/apollolake/northbridge.c @@ -16,6 +16,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <soc/northbridge.h> +#include <soc/pci_ids.h> static uint32_t get_bar(device_t dev, unsigned int index) { @@ -124,13 +125,8 @@ static struct device_operations northbridge_ops = { .enable = DEVICE_NOOP }; -static const unsigned short northbridge_ids[] = { - MCH_APOLLOLAKE_ID, - 0 -}; - static const struct pci_driver northbridge_driver __pci_driver = { .ops = &northbridge_ops, .vendor = PCI_VENDOR_ID_INTEL, - .devices = northbridge_ids + .device = PCI_DEV_ID_APOLLOLAKE_NB }; diff --git a/src/soc/intel/apollolake/uart.c b/src/soc/intel/apollolake/uart.c index ec4b68c..4d7e747 100644 --- a/src/soc/intel/apollolake/uart.c +++ b/src/soc/intel/apollolake/uart.c @@ -14,6 +14,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/pci_ids.h> /* * Shadow BAR for console UART: @@ -55,7 +56,8 @@ static struct device_operations uart_ops = { }; static const unsigned short uart_ids[] = { - 0x5abc, 0x5abe, 0x5ac0, 0x5aee, + PCI_DEV_ID_APOLLOLAKE_UART0, PCI_DEV_ID_APOLLOLAKE_UART1, + PCI_DEV_ID_APOLLOLAKE_UART2, PCI_DEV_ID_APOLLOLAKE_UART3, 0 };

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2016