coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake/romstage: Add callback for update UPD
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13367 -gerrit commit 00087f7e03ef5040ac8cb72f45ca1447ca4cc885 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Nov 24 13:59:23 2015 -0800 soc/intel/apollolake/romstage: Add callback for update UPD Add callback for mainboard to update necessary UPD before FSP memory init started. Change-Id: I797463248d198fa0bf16a9dd7ac6efb7bccb39c1 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/include/soc/romstage.h | 3 +++ src/soc/intel/apollolake/romstage/romstage.c | 11 +++++++++++ 2 files changed, 14 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h index eb69558..948a52e 100644 --- a/src/soc/intel/apollolake/include/soc/romstage.h +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -14,8 +14,11 @@ #define _SOC_APOLLOLAKE_ROMSTAGE_H_ #include <arch/cpu.h> +#include <fsp/api.h> asmlinkage void *romstage_entry(void); asmlinkage void romstage_after_raminit(void); +void mainboard_memory_init_params(struct MEMORY_INIT_UPD *memupd); + #endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c index 24fad92..b1595e8 100644 --- a/src/soc/intel/apollolake/romstage/romstage.c +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -102,3 +102,14 @@ asmlinkage void romstage_after_raminit(void) { run_ramstage(); } + +void platform_fsp_memory_init_params_cb(struct MEMORY_INIT_UPD *memupd) +{ + mainboard_memory_init_params(memupd); +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct MEMORY_INIT_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

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Patch set updated for coreboot: soc/intel/apollolake: Add northbridge ACPI _CRS
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13376 -gerrit commit 86721daebf78aa2a5d979322ed330ebeea13eadc Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Dec 3 22:49:59 2015 -0800 soc/intel/apollolake: Add northbridge ACPI _CRS DSDT table must report resources used by northbridge thourgh _CRS table in northbridge.asl file. The MMIO resource usage defination from apollolake address map HAS. Without the _CRS for northbridge, kernel will report error message about not able to locate memory window. Change-Id: Icb2d0e2e14ccaeda7b26fdc1e4321ea32d57d84d Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index ca6b143..d818fee 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -15,5 +15,86 @@ Name(_ADR, 0) Name(_BBN, 0) +Device (MCHC) +{ + Name (_ADR, 0x00000000) /*Dev0 Func0 */ + + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } +} + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ + Name (MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* PCI MMIO Region (TOLUD - 0xcfffffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0xa0000000, 0xcfffffff, 0x00000000, + 0x30000000,,, PM01) + }) + + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, PM01._MIN, PMIN) + CreateDwordField (MCRS, PM01._MAX, PMAX) + CreateDwordField (MCRS, PM01._LEN, PLEN) + + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, STOM._MIN, GMIN) + CreateDwordField(MCRS, STOM._MAX, GMAX) + CreateDwordField(MCRS, STOM._LEN, GLEN) + + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) + + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + + Add(Subtract(GMAX, GMIN), 1, GLEN) + + Return (MCRS) +} + /* PCI IRQ assignment */ #include "pci_irqs.asl"

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Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI MCFG table
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13375 -gerrit commit 2b7b47b8c735e91b4ddb7a31dc3ad2ccac98d7aa Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:13:23 2015 -0800 soc/apollolake/acpi: Fill ACPI MCFG table ACPI MCFG table is required for OS to support Enhanced Configuration Space Access.Apollolake will only support 1 PCI Segment Group, so all the pci bus number from 0 to 0xff will belong to that group. Change-Id: I3a680eb9c83290cd531159d7e796382a132cd283 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 16acd0f..9939408 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -20,6 +20,10 @@ unsigned long acpi_fill_mcfg(unsigned long current) { + /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ + current += acpi_create_mcfg_mmconfig((void *) current, + CONFIG_MMCONF_BASE_ADDRESS, 0, 0, + 255); return current; }

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Patch set updated for coreboot: soc/apollolake/acpi: Fill ACPI HPET table
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13374 -gerrit commit d91e9697ade4150af5a50e2ec41efd3f372c312d Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Dec 1 09:14:20 2015 -0800 soc/apollolake/acpi: Fill ACPI HPET table HPET table is required to report integrated HPET timer to kernel.Without HPET table insert,current kernel will panic in Timer driver. Change-Id: I7368bc29f4e03d5882dcfc4a770fa7bfbc6c26a0 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 7 +++++++ src/soc/intel/apollolake/include/soc/acpi.h | 3 +++ src/soc/intel/apollolake/lpc.c | 2 ++ 3 files changed, 12 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 0161294..16acd0f 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -111,3 +111,10 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt) fadt->x_gpe1_blk.space_id = 1; } + +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, + struct acpi_rsdp *rsdp) +{ + return acpi_write_hpet(device, current, rsdp); +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 7e112d7..bb655eb 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -18,4 +18,7 @@ /* Zero value won't be programmed again in FADT table. */ void soc_fill_common_fadt(acpi_fadt_t * fadt); +unsigned long southbridge_write_acpi_tables(device_t device, + unsigned long current, struct acpi_rsdp *rsdp); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 8f0d2ad..6d2e8ca 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -13,6 +13,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <soc/acpi.h> static void soc_lpc_add_io_resources(device_t dev) { @@ -38,6 +39,7 @@ static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .write_acpi_tables = southbridge_write_acpi_tables, }; static const unsigned short pci_device_ids[] = {

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Patch set updated for coreboot: soc/apollolake/acpi: Fill in ACPI MADT table
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13373 -gerrit commit a9fed8fcf0803c6c0153c18fbc2b394550b420c7 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 16 18:33:21 2015 -0800 soc/apollolake/acpi: Fill in ACPI MADT table ACPI MADT tables required to describe the multiprocess interrupt routing. Apollolake SOC also have the interrupt override table like other x86 silicons. Change-Id: I85976e227963c950aad4476d68581b96e1090559 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 9be1705..0161294 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,6 +11,8 @@ */ #include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> @@ -21,11 +23,31 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } -unsigned long acpi_fill_madt(unsigned long current) +static unsigned long acpi_madt_irq_overrides(unsigned long current) { + uint16_t flags = MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW;; + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((void *)current, 0, 0, 2, 0); + + /* SCI */ + current += acpi_create_madt_irqoverride((void *)current, 0, 9, 9, flags); + return current; } +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((void *) current, + 2, IO_APIC_ADDR, 0); + + return acpi_madt_irq_overrides(current); +} + static int acpi_sci_irq(void) { int sci_irq = 9;

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Include SOC ASL
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13372 -gerrit commit 7ff63c78a8811698b3a231ceb82271aeca1aad48 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 17:06:54 2015 -0800 mainboard/intel/apollolake_rvp: Include SOC ASL Include northbridge ASL file into board DSDT table. Change-Id: I33903a9c281e4981bd0f226c22553e22f98075bc Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/dsdt.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl index 1736cea..b219caa 100644 --- a/src/mainboard/intel/apollolake_rvp/dsdt.asl +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -22,7 +22,7 @@ DefinitionBlock( Scope (\_SB) { Device (PCI0) { - Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + #include <soc/intel/apollolake/acpi/northbridge.asl> } }

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Patch set updated for coreboot: soc/intel/apollolake: Fill _PRT entry in DSDT
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13371 -gerrit commit 879e02438083a3107b00f8c2a0e6bef82bc93a60 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Dec 2 15:34:45 2015 -0800 soc/intel/apollolake: Fill _PRT entry in DSDT ACPI aware OF will need _PRT table to get desired interrupt resource assigned and make device driver working. The logical device within SOC got fixed interrupt line. Change-Id: I9595f9a12434fa423862836d19f7266d6023fc5a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 19 ++++++++++ src/soc/intel/apollolake/acpi/pci_irqs.asl | 51 +++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl new file mode 100644 index 0000000..ca6b143 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -0,0 +1,19 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + Name(_ADR, 0) + Name(_BBN, 0) + +/* PCI IRQ assignment */ +#include "pci_irqs.asl" diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl new file mode 100644 index 0000000..9a737e2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +Method(_PRT) +{ + Return(Package() { + + Package(){0x0000FFFF, 0, 0, 16}, /* NPK */ + Package(){0x0000FFFF, 1, 0, 24}, /* DPTF */ + Package(){0x0002FFFF, 0, 0, 19}, /* GEN */ + Package(){0x0003FFFF, 0, 0, 21}, /* IUNIT */ + Package(){0x000DFFFF, 1, 0, 40}, /* PMC */ + Package(){0x000EFFFF, 0, 0, 25}, /* Audio */ + Package(){0x000FFFFF, 0, 0, 20}, /* CSE */ + Package(){0x0011FFFF, 0, 0, 26}, /* ISH */ + Package(){0x0012FFFF, 0, 0, 19}, /* SATA */ + Package(){0x0013FFFF, 0, 0, 22}, /* PCIe-A 0 */ + Package(){0x0014FFFF, 0, 0, 22}, /* PCIe-B 0 */ + Package(){0x0015FFFF, 0, 0, 17}, /* xHCI */ + Package(){0x0015FFFF, 1, 0, 13}, /* xDCI */ + Package(){0x0016FFFF, 0, 0, 27}, /* I2C0 */ + Package(){0x0016FFFF, 1, 0, 28}, /* I2C1 */ + Package(){0x0016FFFF, 2, 0, 29}, /* I2C2 */ + Package(){0x0016FFFF, 3, 0, 30}, /* I2C3 */ + Package(){0x0017FFFF, 0, 0, 31}, /* I2C4 */ + Package(){0x0017FFFF, 1, 0, 32}, /* I2C5 */ + Package(){0x0017FFFF, 2, 0, 33}, /* I2C6 */ + Package(){0x0017FFFF, 3, 0, 34}, /* I2C7 */ + Package(){0x0018FFFF, 0, 0, 4}, /* UART0 */ + Package(){0x0018FFFF, 1, 0, 5}, /* UART1 */ + Package(){0x0018FFFF, 2, 0, 6}, /* UART2 */ + Package(){0x0018FFFF, 3, 0, 7}, /* UART3 */ + Package(){0x0019FFFF, 0, 0, 35}, /* SPI0 */ + Package(){0x0019FFFF, 1, 0, 36}, /* SPI1 */ + Package(){0x0019FFFF, 2, 0, 37}, /* SPI2 */ + Package(){0x001BFFFF, 0, 0, 3}, /* SDCard */ + Package(){0x001CFFFF, 0, 0, 39}, /* eMMC */ + Package(){0x001EFFFF, 0, 0, 42}, /* SDIO */ + Package(){0x001FFFFF, 0, 0, 20}, /* LPC */ + } + ) +}

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Patch set updated for coreboot: drivers/intel/fsp2_0: Print address of FspMemoryInit entry point
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13370 -gerrit commit 5252c1d7c36cd2500e42bd6322e257fb3055698b Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Tue Dec 1 16:41:02 2015 -0800 drivers/intel/fsp2_0: Print address of FspMemoryInit entry point Through an oversight, the address of fsp_memory_init was printed, which is a coreboot function. the intention is to print the address of the fsp_raminit pointer, which is the entry point into FSP memory init. Change-Id: I95904279fc148319033281d45b681ad427e03130 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/memory_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 4ac720d..e9d6e42 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -88,7 +88,7 @@ static enum fsp_status do_fsp_memory_init(void **hob_list_ptr, /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); - printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init); + printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_raminit); printk(BIOS_SPEW, "\t%p: nvs_buffer\n", raminit_params.nvs_buffer); printk(BIOS_SPEW, "\t%p: rt_buffer\n", raminit_params.rt_buffer); printk(BIOS_SPEW, "\t%p: hob_list\n", raminit_params.hob_list);

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Patch set updated for coreboot: intel/apollolake_rvp: Add GPIO configuration for UART2 pads
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13369 -gerrit commit 473c472b8ab01925814e9e37cb9744b2705966e8 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Nov 25 14:59:37 2015 -0800 intel/apollolake_rvp: Add GPIO configuration for UART2 pads UART2 is the main debugging interface. Older FSP versions configured the TX and RX pads, but that is no longer the case. We now need to configure the pads in coreboot. This fixes an issue where serial input would no longer work with newer FSP versions. Change-Id: I9c2354720bf428439b7262b32ce1ea5c9eddbdfb Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 2 +- src/mainboard/intel/apollolake_rvp/mainboard.c | 29 +++++++++++++++++++++++++ 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index a48936e..f3c87b2 100755 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +1 @@ -# Nothing yet here +ramstage-y += mainboard.c diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c new file mode 100644 index 0000000..3ed3d8f --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <device/device.h> +#include <soc/gpio.h> + +/* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ +static const struct pad_config aplk_rvp_gpios[] = { + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ +}; + +static void mainboard_enable(struct device *dev) +{ + gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +};

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: Fill mainboard mem UPD
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13368 -gerrit commit 4c2f403cbdb81c6146a3ecfc0462c649a915e9bf Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Nov 24 14:09:56 2015 -0800 mainboard/intel/apollolake_rvp: Fill mainboard mem UPD Add mainboard depended memory UPD value for apollolake RVP platform.Which is LPDDR3 for current RVP2 platform. Change-Id: Ie32eb1f103ec4fb41c2f6212b28c76ec207e81e4 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/romstage.c | 127 +++++++++++++++++++++++++- 1 file changed, 126 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/apollolake_rvp/romstage.c b/src/mainboard/intel/apollolake_rvp/romstage.c index c5d3ce1..c266fd2 100644 --- a/src/mainboard/intel/apollolake_rvp/romstage.c +++ b/src/mainboard/intel/apollolake_rvp/romstage.c @@ -1 +1,126 @@ -/* Nothing here yet, but this file is needed by the buildsystem */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <soc/romstage.h> +#include <string.h> +#include <fsp/api.h> + +static const uint8_t swizzling_rvp1[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, +}; + +static const uint8_t swizzling0_rvp2[] = { + 23, 21, 16, 17, 18, 19, 22, 20, 3, 5, 2, 4, 7, 0, 6, 1, + 24, 27, 26, 30, 28, 25, 29, 31, 13, 8, 12, 15, 10, 14, 11, 9, +}; + +static const uint8_t swizzling1_rvp2[] = { + 10, 14, 12, 13, 9, 11, 15, 8, 1, 6, 2, 5, 0, 7, 3, 4, + 21, 18, 19, 22, 20, 17, 16, 23, 29, 28, 24, 27, 31, 30, 26, 25, +}; + +static const uint8_t swizzling2_rvp2[] = { + 13, 15, 10, 14, 9, 12, 8, 11, 22, 19, 16, 23, 21, 17, 20, 18, + 26, 24, 28, 29, 31, 30, 27, 25, 4, 5, 1, 0, 3, 6, 7, 2, +}; + +static const uint8_t swizzling3_rvp2[] = { + 0, 3, 6, 7, 4, 5, 1, 2, 20, 17, 21, 16, 23, 18, 22, 19, + 15, 9, 11, 14, 12, 8, 13, 10, 26, 29, 24, 31, 25, 30, 27, 28, +}; + +static void rvp1_fill_memory_params(struct DRAM_CONFIG *cfg) +{ + cfg->Profile = 33; + cfg->DIMM0SPDAddress = 0xa0; + cfg->DIMM1SPDAddress = 0xa4; + cfg->Ch0_RankEnable = 0; + cfg->Ch0_DeviceWidth = 0; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 0; + cfg->Ch1_DeviceWidth = 0; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 0; + cfg->Ch2_DeviceWidth = 0; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 0; + cfg->Ch3_DeviceWidth = 0; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling_rvp1, sizeof(swizzling_rvp1)); +} + +static void rvp2_fill_memory_params(struct DRAM_CONFIG *cfg) +{ + cfg->Profile = 5; + cfg->DIMM0SPDAddress = 0; + cfg->DIMM1SPDAddress = 0; + cfg->Ch0_RankEnable = 3; + cfg->Ch0_DeviceWidth = 2; + cfg->Ch0_DramDensity = 0; + cfg->Ch0_Option = 3; + cfg->Ch1_RankEnable = 3; + cfg->Ch1_DeviceWidth = 2; + cfg->Ch1_DramDensity = 0; + cfg->Ch1_Option = 3; + cfg->Ch2_RankEnable = 3; + cfg->Ch2_DeviceWidth = 2; + cfg->Ch2_DramDensity = 0; + cfg->Ch2_Option = 3; + cfg->Ch3_RankEnable = 3; + cfg->Ch3_DeviceWidth = 2; + cfg->Ch3_DramDensity = 0; + cfg->Ch3_Option = 3; + memcpy(cfg->Ch0_Bit_swizzling, swizzling0_rvp2, + sizeof(swizzling0_rvp2)); + memcpy(cfg->Ch1_Bit_swizzling, swizzling1_rvp2, + sizeof(swizzling1_rvp2)); + memcpy(cfg->Ch2_Bit_swizzling, swizzling2_rvp2, + sizeof(swizzling2_rvp2)); + memcpy(cfg->Ch3_Bit_swizzling, swizzling3_rvp2, + sizeof(swizzling3_rvp2)); +} + +void mainboard_memory_init_params(struct MEMORY_INIT_UPD *memupd) +{ + struct DRAM_CONFIG *cfg = &memupd->DramConfig; + + cfg->Package = 0; + cfg->MemoryDown = 1; + cfg->DDR3LPageSize = 0; + cfg->DDR3LASR = 0; + cfg->ScramblerSupport = 1; + cfg->ChannelHashMask = 0; + cfg->SliceHashMask = 0; + cfg->InterleavedMode = 0; + cfg->ChannelsSlicesEnable = 0; + cfg->MinRefRate2xEnable = 0; + cfg->DualRankSupportEnable = 1; + cfg->DisableFastBoot = 0; + cfg->RmtMode = 0; + cfg->MemorySizeLimit = 0; + cfg->LowMemoryMaxValue = 0; + cfg->HighMemoryMaxValue = 0; + cfg->DramReserved = 0; + + if (IS_ENABLED(CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1)) + rvp1_fill_memory_params(cfg); + else + rvp2_fill_memory_params(cfg); +}

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coreboot-gerrit January 2016