coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13403 -gerrit commit 26ba08ded86812238b905f3a0a21081e59b7e7f9 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Jan 7 16:54:39 2016 -0800 soc/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required gnvs feature, the gnvs table stays in both CBMEM and acpi dsdt tables. Change-Id: Id91e351ca7af06da6a9c89d2b353028323cded3c Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ src/soc/intel/apollolake/acpi.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 26 ++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 7 +++++++ 5 files changed, 68 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 179eaad..a5884ae 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -16,11 +16,15 @@ config CPU_SPECIFIC_OPTIONS select SMP select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS + # Whatever bits we can salvage from intel/common + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_RESET # Misc options select C_ENVIRONMENT_BOOTBLOCK select COLLECT_TIMESTAMPS select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO # 8250 IO conflicts with 8250 MEM_32 + select HAVE_HARD_RESET select HAVE_INTEL_FIRMWARE select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3b622b8..940b81b 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -11,12 +11,24 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <vendorcode/google/chromeos/gnvs.h> + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -120,3 +132,20 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((unsigned long)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uint32_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index bb655eb..e629362 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -14,10 +14,12 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> /* Zero value won't be programmed again in FADT table. */ void soc_fill_common_fadt(acpi_fadt_t * fadt); +void southbridge_inject_dsdt(device_t device); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..af7b546 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 120b0e9..07ac3f6 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -10,11 +10,13 @@ * (at your option) any later version. */ +#include <cbmem.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <vendorcode/google/chromeos/chromeos.h> static void soc_lpc_add_io_resources(device_t dev) { @@ -29,17 +31,22 @@ static void soc_lpc_add_io_resources(device_t dev) static void soc_lpc_read_resources(device_t dev) { + struct global_nvs_t *gnvs; /* Get the PCI resources of this device. */ pci_dev_read_resources(dev); /* Add IO resources to LPC. */ soc_lpc_add_io_resources(dev); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } static struct device_operations device_ops = { .read_resources = &soc_lpc_read_resources, .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = southbridge_write_acpi_tables, };

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Patch set updated for coreboot: intel/apollolake_rvp: Write GPIO lb table for CHROMEOS builds
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13402 -gerrit commit 26c24dd4d1eb5bee9c0b02d8add89950557f74c8 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Wed Jan 13 14:30:03 2016 -0800 intel/apollolake_rvp: Write GPIO lb table for CHROMEOS builds Note that the table only defines the entries, but does not link them to real GPIOs. This is enough for the deptcharge payload to not crash during boot. Change-Id: Ib9d73d873b0a864bcb8ab7061514c0bab7af27bf Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 + .../intel/apollolake_rvp/chromeos_ramstage.c | 32 ++++++++++++++++++++++ 2 files changed, 33 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 52de59b..e30e19a 100755 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1,5 +1,6 @@ romstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos_ramstage.c ramstage-y += mainboard.c diff --git a/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c b/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c new file mode 100644 index 0000000..81866a8 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/chromeos_ramstage.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <boot/coreboot_tables.h> +#include <vendorcode/google/chromeos/chromeos.h> + +#define GPIO_COUNT 7 + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + struct lb_gpio *gpio; + + gpios->size = sizeof(*gpios) + (GPIO_COUNT * sizeof(struct lb_gpio)); + gpios->count = GPIO_COUNT; + + gpio = gpios->gpios; + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "recovery", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "developer", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "lid", 1); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "power", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "oprom", 0); + fill_lb_gpio(gpio++, -1, ACTIVE_HIGH, "write protect", 0); +}

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Patch set updated for coreboot: mainboard/apollolake: update flashmap offset for new master image
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13405 -gerrit commit 584ab43e9d8664fb1443934ce6ce973b12f9bb5f Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Thu Jan 14 13:19:37 2016 -0800 mainboard/apollolake: update flashmap offset for new master image The new master image has new fmap offset Change-Id: Ifd33a128979da783f978a86fced83c5f4d1dacc0 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 15 ++++++++++++--- src/mainboard/intel/apollolake_rvp/aplk.rvp.dts | 23 +++++++++++++++++++++++ 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index ec71e96..072ca49 100755 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES + select USE_BLOBS config MAINBOARD_DIR string @@ -18,9 +19,18 @@ config MAINBOARD_VENDOR string default "Intel" +config FMAP_FILE + string + default aplk.rvp + +config PREBUILT_SPI_IMAGE + string + default aplk.rvp1.bin.orig if BOARD_INTEL_APOLLOLAKE_RVP1 + default aplk.rvp2.bin.orig if BOARD_INTEL_APOLLOLAKE_RVP2 + config IFD_BIOS_END hex - default 0x700000 + default 0x6FF000 config IFD_BIOS_START hex @@ -28,7 +38,6 @@ config IFD_BIOS_START config FLASHMAP_OFFSET hex - default 0x3a3040 if BOARD_INTEL_APOLLOLAKE_RVP1 - default 0x3f10c0 if BOARD_INTEL_APOLLOLAKE_RVP2 + default 0x7e480 endif # BOARD_INTEL_APOLLOLAKE_RVP1 || BOARD_INTEL_APOLLOLAKE_RVP2 diff --git a/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts b/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts new file mode 100644 index 0000000..45f5dad --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/aplk.rvp.dts @@ -0,0 +1,23 @@ +firmware 8M { + + SI_HDR@0x0 4K { + SI_DESC 4K + } + + # IBBL is a 32 kb code block that is initially loaded by CSE firmware and + # is placed in shared SRAM. That SRAM area is mapped in 4G-32K area of + # the host CPU. Reset vector is set as usual. + IBBL @ 0x76480 32K + FMAP @ 0x7e480 2K + RW_SECTION_A @ 0x382000 { + VBLOCK_A 64K + FW_MAIN_A 768K + } + RW_SECTION_B @ 0x452000 { + VBLOCK_B 64K + FW_MAIN_B 768K + } + COREBOOT(CBFS) @ 0x522000 1456K + GBB @ 0x68e000 320K + } +

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Patch set updated for coreboot: soc/apollolake: Read PCIe CLKREQ pin mapping from devicetree
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13407 -gerrit commit 765140891a0a7d15a24846f014652058a52e704f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Jan 15 10:40:24 2016 -0800 soc/apollolake: Read PCIe CLKREQ pin mapping from devicetree The corect CLKREQ signal to PCIe root port mapping is needed in order for PCIe devices to enumerate. This mapping is board-specific, so get it from devicetree. Change-Id: I0a5057274b84c41ef529052c5967ea4321e5f450 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.c | 22 ++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 180cfc1..630df3e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -18,6 +18,8 @@ #include <device/pci.h> #include <fsp/api.h> +#include "chip.h" + static void pci_domain_set_resources(device_t dev) { assign_resources(dev->link_list); @@ -60,6 +62,26 @@ static void soc_init(void *data) fsp_silicon_init(); } +void platform_fsp_silicon_init_params_cb(struct SILICON_INIT_UPD *silupd) +{ + static struct soc_intel_apollolake_config *cfg; + + struct device *dev = dev_find_slot(0, 0); + if (!dev && !dev->chip_info) { + printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); + return; + } + + cfg = dev->chip_info; + + silupd->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; + silupd->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; + silupd->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; + silupd->PcieRpClkReqNumber[3] = cfg->pcie_rp3_clkreq_pin; + silupd->PcieRpClkReqNumber[4] = cfg->pcie_rp4_clkreq_pin; + silupd->PcieRpClkReqNumber[5] = cfg->pcie_rp5_clkreq_pin; +} + struct chip_operations soc_intel_apollolake_ops = { CHIP_NAME("Intel Apollolake SOC") .enable_dev = &enable_dev, diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h new file mode 100644 index 0000000..026fdda --- /dev/null +++ b/src/soc/intel/apollolake/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_CHIP_H_ +#define _SOC_APOLLOLAKE_CHIP_H_ + +#define CLKREQ_DISABLED 0xf + +struct soc_intel_apollolake_config { + /* + * Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has + * four CLKREQ inputs, but six root ports. Root ports without an + * associated CLKREQ signal must be marked with "CLKREQ_DISABLED" + */ + uint8_t pcie_rp0_clkreq_pin; + uint8_t pcie_rp1_clkreq_pin; + uint8_t pcie_rp2_clkreq_pin; + uint8_t pcie_rp3_clkreq_pin; + uint8_t pcie_rp4_clkreq_pin; + uint8_t pcie_rp5_clkreq_pin; +}; + +#endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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Patch set updated for coreboot: intel/apollolake_rvp: Configure CLKREQ pins for PCIe
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13406 -gerrit commit e5ca0d4ff4bc01afc4c0e829fe3591b11f6c4dbe Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Dec 17 14:12:01 2015 -0800 intel/apollolake_rvp: Configure CLKREQ pins for PCIe These pads function as CLKREQ inputs if configured as native function. Change-Id: Ia86b76fa441028cc2d4467faebdc499c5339b6ca Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/mainboard.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index 8a0ab2a..dc7bc1e 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -21,6 +21,10 @@ static const struct pad_config aplk_rvp_gpios[] = { PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */ PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */ PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */ + PAD_CFG_NF(GPIO_209, NATIVE, DEEP, NF1), /* PCIE_CLKREQ0_B */ + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* PCIE_CLKREQ1_B */ + PAD_CFG_NF(GPIO_211, NATIVE, DEEP, NF1), /* PCIE_CLKREQ2_B */ + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), /* PCIE_CLKREQ3_B */ }; static void mainboard_init(void *chip_info)

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Patch set updated for coreboot: soc/appollolake: Write correct framebuffer base in lb_framebuffer
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13393 -gerrit commit 7d886492b0a9e2dca0683aa2a4b87378397d7f71 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Dec 23 11:25:27 2015 -0800 soc/appollolake: Write correct framebuffer base in lb_framebuffer FSP returns a base address for the framebuffer, but that base address is actually a PCI BAR, which is moved during resource allocation. Instead of writing the FSP provided value to the lb_framebuffer, write the address the resource allocator has selected. Change-Id: I0c6bf4d65940aa2d64fbf7e7593bc339162faffe Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/graphics.c | 40 ++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/graphics.c b/src/soc/intel/apollolake/graphics.c index 7b9a75c..7186a28 100644 --- a/src/soc/intel/apollolake/graphics.c +++ b/src/soc/intel/apollolake/graphics.c @@ -12,6 +12,12 @@ #include <console/console.h> #include <fsp/util.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_ids.h> + +static uintptr_t framebuffer_bar = (uintptr_t)NULL; void lb_framebuffer(struct lb_header *header) { @@ -20,6 +26,38 @@ void lb_framebuffer(struct lb_header *header) framebuffer = (void *)lb_new_record(header); ret = fsp_fill_lb_framebuffer(framebuffer); - if (ret != CB_SUCCESS) + if (ret != CB_SUCCESS) { printk(BIOS_ALERT, "FSP did not return a valid framebuffer\n"); + return; + } + + /* Resource allocator can move the BAR around after FSP configures it */ + if (!framebuffer_bar) { + printk(BIOS_ALERT, "Framebuffer BAR invalid (00:02.0 BAR2)\n"); + return; + } + + framebuffer->physical_address = framebuffer_bar; + printk(BIOS_DEBUG, "Graphics framebuffer located at 0x%llx\n", + framebuffer->physical_address); +} + +static void igd_set_resources(struct device *dev) +{ + framebuffer_bar = find_resource(dev, PCI_BASE_ADDRESS_2)->base; + pci_dev_set_resources(dev); } + +static struct device_operations igd_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = igd_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable = DEVICE_NOOP +}; + +static const struct pci_driver uart_driver __pci_driver = { + .ops = &igd_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEV_ID_APOLLOLAKE_IGD, +};

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Patch set updated for coreboot: drivers/intel/fsp2_0: Print names of hand-off-block owner
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13392 -gerrit commit 39126980d20e481f372a351e0482bc64ce65d12f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Dec 11 10:41:56 2015 -0800 drivers/intel/fsp2_0: Print names of hand-off-block owner To help with debugging, also print the name of the owner of a hand-off-block (HOB), instead of just the UUID. Looking at an actual string instead of a list of hexadecimal character significantly speeds up debugging. Only UUIDs which are currently returned by FSP are added. All others are marked as "UNKNOWN" Change-Id: I2f3f7579722c8bd440f05c43243f33b3fca63d91 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 35 ++++++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c index 7e47525..4d061b5 100644 --- a/src/drivers/intel/fsp2_0/hand_off_block.c +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -73,15 +73,34 @@ enum hob_type { }; /* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + static const uint8_t uuid_owner_fsp[16] = { 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, }; +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + static const uint8_t empty_uuid[16] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + static const char *resource_name(enum resource_type type) { if (type >= ARRAY_SIZE(resource_names)) @@ -98,6 +117,19 @@ static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) return !memcmp(uuid1, uuid2, 16); } +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + static const struct hob_header *next_hob(const struct hob_header *parent) { union { @@ -211,7 +243,7 @@ static void print_guid(const void *base) mid[0] = read16(id + 4); mid[1] = read16(id + 6); - printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x\n", + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", big, mid[0], mid[1], id[8], id[9], id[10], id[11], id[12], id[13],id[14], id[15]); } @@ -228,6 +260,7 @@ static void print_resource_descriptor(const void *base) if (!uuid_compare(res->owner_guid, empty_uuid)) { printk(BIOS_DEBUG, "\tOwner GUID: "); print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); } }

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Patch set updated for coreboot: intel/apollolake_rvp: Enable power for SATA Direct Connect
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13395 -gerrit commit 0988a777f48897b891cc11672f5f1ae1c10c7f60 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Fri Jan 8 09:37:13 2016 -0800 intel/apollolake_rvp: Enable power for SATA Direct Connect The SATA Direct Connect is a 22-pin SATA connector that can accept an SSD or low-power HDD, providing 3.3V and 5V power rails. These power rails are gated with transistors, and are controlled by GPIO 22. Set GPIO 22 to output high to enable this SATA connector. Change-Id: Id6c48362b8d7ad11da4f53b5300b063d5efc9827 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/mainboard.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index a844145..8a0ab2a 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -15,6 +15,7 @@ /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config aplk_rvp_gpios[] = { + PAD_CFG_GPO(GPIO_22, 1, DEEP), /* SATA Direct power */ PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */

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Patch set updated for coreboot: intel/apollolake_rvp: Fix GPIO comment alignment in mainboard.c
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13394 -gerrit commit fc4180dbf150c80c8f7248c480c7ef920d1bfedf Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Jan 7 15:37:57 2016 -0800 intel/apollolake_rvp: Fix GPIO comment alignment in mainboard.c Change-Id: I8102d3d5abfc02bd9b55fadefbfbb237767cd72e Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/mainboard/intel/apollolake_rvp/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/mainboard.c b/src/mainboard/intel/apollolake_rvp/mainboard.c index b437f74..a844145 100644 --- a/src/mainboard/intel/apollolake_rvp/mainboard.c +++ b/src/mainboard/intel/apollolake_rvp/mainboard.c @@ -15,8 +15,8 @@ /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ static const struct pad_config aplk_rvp_gpios[] = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX*/ PAD_CFG_NF(GPIO_193, NATIVE, DEEP, NF1), /* PANEL0_VDDEN */ PAD_CFG_NF(GPIO_194, NATIVE, DEEP, NF1), /* PANEL0_BKLTEN */ PAD_CFG_NF(GPIO_195, NATIVE, DEEP, NF1), /* PANEL0_BKLTCTL */

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Patch set updated for coreboot: drivers/intel/fsp2_0: Change memory layout newer FSP version
by Alexandru Gagniuc 26 Jan '16

26 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13397 -gerrit commit 7a665f6336b4000f2d28dbf4de67ea41cd2907ec Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Thu Dec 10 17:35:25 2015 -0800 drivers/intel/fsp2_0: Change memory layout newer FSP version FSP memory layout changed. It now requires 1MiB of CAR versis 512 KiB it required before. FSP team promises that they are working to reduce CAR usage back to 512KiB. Change-Id: I936097a97598a84530d28981794e15693a361a89 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index b367b78..bfba51a 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -41,21 +41,23 @@ config VBT_FILE config FIT_CAR_ADDR hex - default 0xfef27c00 + default 0xfef2dc00 # Cache As RAM region layout: # -# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xfef80000] +# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE [0xff000000] +# | Unused | +# +-------------+ --------------------------------- [0xfefa0000] # | | # | FSP-M | # | code | # | | -# +-------------+ FSP-M [0xfef30000] +# +-------------+ FSP-M [0xfef50000] # | romstage | # | code | -# +-------------+ ROMSTAGE_CAR_ADDR [0xfef28000] +# +-------------+ ROMSTAGE_CAR_ADDR [0xfef2e000] # | FIT TABLE | -# +-------------+ FIT_CAR_ADDR [0xfef27c00] +# +-------------+ FIT_CAR_ADDR [0xfef2dc00] # | FSP-M | # | stack/data | # +-------------+ DCACHE_RAM_BASE + 0x4000 [0xfef04000]

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coreboot-gerrit January 2016