coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13129 -gerrit commit 0b97ee0c0ce36283ec20843391f46336bbb4bd2d Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:15:55 2016 +1100 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000 Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index 1892b37..1234569 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -30,7 +30,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xc0000000 + default 0xe0000000 config MAINBOARD_DIR string

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Patch set updated for coreboot: nb/intel/x4x: Tidy up northbridge
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13126 -gerrit commit 11158bc0ade944a4871ccd37856c36938f621fa7 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:05 2016 +1100 nb/intel/x4x: Tidy up northbridge - Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/early_init.c | 11 +++-------- src/northbridge/intel/x4x/x4x.h | 11 ++++++++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index b98c42e..b522293 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -22,8 +22,6 @@ void x4x_early_init(void) { - u16 reg16; - const device_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ @@ -36,12 +34,11 @@ void x4x_early_init(void) pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup PMBASE */ - pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); - reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4); - pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(d0f0, D0F0_PAM(0), 0x30); @@ -53,8 +50,6 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(6), 0x33); /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); pci_write_config16(d0f0, D0F0_GGC, 0x0170); - - reg16 = pci_read_config16(d0f0, D0F0_DEVEN); - pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c226950..e1ef745 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -27,11 +27,20 @@ #define D0F0_MCHBAR_HI 0x4c #define D0F0_GGC 0x52 #define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN) #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 #define D0F0_DMIBAR_LO 0x68 #define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 #define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ #define D0F0_REMAPBASE 0x98 #define D0F0_REMAPLIMIT 0x9a

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Patch set updated for coreboot: nb/intel/x4x: Tidy up raminit and fix msbpos() function
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13127 -gerrit commit b14e7bb21c76b955126f359009ae9d6ab9e7780e Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:44 2016 +1100 nb/intel/x4x: Tidy up raminit and fix msbpos() function - Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit_ddr2.c | 52 ++++++++++++++++++++++++++------ 1 file changed, 43 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d21924b..f343d8b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -45,14 +45,17 @@ static u32 ddr2mhz(u32 speed) return mhz[speed]; } -static u8 msbpos(u8 val) //Reverse +/* Find MSB bitfield location using bit scan reverse instruction */ +static u8 msbpos(u8 val) { - u8 i; - for (i = 7; i >= 0; i--) { - if ((val & (1 << i)) == 0) - break; - } - return i; + u8 pos; + + asm ("bsrl %1, %0" + :"=r"(pos) + :"r"(val) + ); + + return pos; } static void sdram_detect_smallest_params2(struct sysinfo *s) @@ -1614,7 +1617,9 @@ static void dradrb_ddr2(struct sysinfo *s) static void mmap_ddr2(struct sysinfo *s) { - u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + bool reclaim; + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; + u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; @@ -1626,13 +1631,34 @@ static void mmap_ddr2(struct sysinfo *s) mmiosize = 0x400; // 1GB MMIO tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); + + reclaim = false; + if ((tom - tolud) > 0x40) + reclaim = true; + + if (reclaim) { + tolud = tolud & ~0x3f; + tom = tom & ~0x3f; + reclaimbase = MAX(0x1000, tom); + reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; + } + touud = tom; + if (reclaim) + touud = reclaimlimit + 0x40; + gfxbase = tolud - gfxsize; gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + if (reclaim) { + pci_write_config16(PCI_DEV(0,0,0), 0x98, + (u16)(reclaimbase >> 6)); + pci_write_config16(PCI_DEV(0,0,0), 0x9a, + (u16)(reclaimlimit >> 6)); + } pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); @@ -1993,7 +2019,15 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + } + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + } + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); }

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Patch set updated for coreboot: nb/intel/x4x: Fix memory hole with both channels populated
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13125 -gerrit commit a646b6b48424bd3f57fb0ace75f0277573eef683 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 18:56:23 2016 +1100 nb/intel/x4x: Fix memory hole with both channels populated Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/northbridge.c | 61 +++++++++++++++----------------- src/northbridge/intel/x4x/raminit_ddr2.c | 53 ++++++++++++++++++--------- 2 files changed, 64 insertions(+), 50 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index c5a8968..b23f8e6 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -28,23 +28,21 @@ #include <arch/acpi.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> - -/* Reserve segments A and B: - * - * 0xa0000 - 0xbffff: legacy VGA - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 128; +#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { + u8 index; u64 tom, touud; - u32 tomk, tsegk, tolud, usable_tomk; + u32 tomk, tseg_sizek, tolud, usable_tomk; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; + const u32 top32memk = 4 * (GiB / KiB); + index = 3; + /* 1024KiB TSEG */ - tsegk = 1 << 10; + tseg_sizek = 1024; pci_domain_read_resources(dev); @@ -77,53 +75,52 @@ static void mch_domain_read_resources(device_t dev) const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); - uma_sizek = gms_sizek + gsm_sizek + tsegk; + uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; usable_tomk = tomk - uma_sizek; printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); + ram_resource(dev, index++, 0, 0xa0000 >> 10); + ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10))); /* * If >= 4GB installed then memory from TOLUD to 4GB * is remapped above TOM, TOUUD will account for both */ touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + if (touud > top32memk) { + ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud - top32memk) >> 10); } printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); - fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE); + "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, + IORESOURCE_RESERVE); - /* Some strange hole, reserve it */ - //fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE); + /* Reserve high memory where the NB BARs are up to 4GiB */ + fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, + (top32memk*KiB - DEFAULT_HECIBAR) >> 10, + IORESOURCE_RESERVE); if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, 7, pcie_config_base >> 10, + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } + + set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) { - struct resource *resource; - int i; - - for (i = 3; i < 8; ++i) { - /* Report read resources. */ - resource = probe_resource(dev, i); - if (resource) - report_resource_stored(dev, resource, ""); - } + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -141,10 +138,9 @@ static void mch_domain_init(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -160,7 +156,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d77c2c4..d21924b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -23,6 +23,8 @@ #include "iomap.h" #include "x4x.h" +#define ME_UMA_SIZEMB 0 + static inline void barrier(void) { asm volatile("mfence":::); @@ -1465,7 +1467,8 @@ static void dradrb_ddr2(struct sysinfo *s) u32 dra0; u32 dra1; u16 totalmemorymb; - u16 size, offset; + u32 size, offset; + u32 size0, size1; u8 dratab[2][2][2][4] = { { { @@ -1562,35 +1565,51 @@ static void dradrb_ddr2(struct sysinfo *s) MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; } - MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; - MCHBAR16(0x104) = 0; - size = s->channel_capacity[0] + s->channel_capacity[1]; - MCHBAR16(0x102) = size; + /* Populated channel sizes in MiB */ + size0 = s->channel_capacity[0]; + size1 = s->channel_capacity[1]; + + MCHBAR8(0x111) = MCHBAR8(0x111) & ~0x2; + MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4); + + /* Set ME UMA size in MiB */ + MCHBAR16(0x100) = ME_UMA_SIZEMB; + + /* Set ME UMA Present bit */ + MCHBAR32(0x111) = MCHBAR32(0x111) | 1; + + size = MIN(size0 - ME_UMA_SIZEMB, size1) * 2; + + MCHBAR16(0x104) = size; + MCHBAR16(0x102) = size0 + size1 - size; + map = 0; - if (s->channel_capacity[0] == 0) { + if (size0 == 0) { map = 0; - } else if (s->channel_capacity[1] == 0) { + } else if (size1 == 0) { map |= 0x20; } else { map |= 0x40; } - map |= 0x18; - if (s->channel_capacity[0] <= s->channel_capacity[1]) { - map |= 0x5; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + if (size == 0) { + map |= 0x18; + } + + if (size0 - ME_UMA_SIZEMB >= size1) { map |= 0x4; } MCHBAR8(0x110) = map; MCHBAR16(0x10e) = 0; - if (s->channel_capacity[1] != 0) { + + if (size1 != 0) { offset = 0; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { - offset = size; + } else if ((size0 > size1) && ((map & 0x7) == 0x4)) { + offset = size/2 + (size0 + size1 - size); } else { - offset = 0; + offset = size/2 + ME_UMA_SIZEMB; } MCHBAR16(0x108) = offset; - MCHBAR16(0x10a) = 0; + MCHBAR16(0x10a) = size/2; } static void mmap_ddr2(struct sysinfo *s) @@ -1605,7 +1624,7 @@ static void mmap_ddr2(struct sysinfo *s) gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; tsegsize = 1; // 1MB TSEG mmiosize = 0x400; // 1GB MMIO - tom = s->channel_capacity[0] + s->channel_capacity[1]; + tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); touud = tom; gfxbase = tolud - gfxsize;

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Patch set updated for coreboot: mainboard/cubieboard: use bootblock_mainboard_early_init
by Iru Cai 27 Jan '16

27 Jan '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13448 -gerrit commit 3c31f192159397c45557553093dd6cae2a26b407 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Tue Jan 26 10:25:51 2016 +0800 mainboard/cubieboard: use bootblock_mainboard_early_init since commit f1e321001d5954096f06f9a43138219a9a46536e, the UART init should be in bootblock_mainboard_early_init() which runs before console init. (see src/lib/bootblock.c) Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71 --- src/mainboard/cubietech/cubieboard/bootblock.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/cubietech/cubieboard/bootblock.c b/src/mainboard/cubietech/cubieboard/bootblock.c index e4a0313..1f6a77f 100644 --- a/src/mainboard/cubietech/cubieboard/bootblock.c +++ b/src/mainboard/cubietech/cubieboard/bootblock.c @@ -127,7 +127,7 @@ static void cubieboard_raminit(void) ////ram_check((u32)test_base, (u32)test_base + 0x1000); } -void bootblock_mainboard_init(void) +void bootblock_mainboard_early_init(void) { /* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very * early on to get udelay, which is used almost everywhere else. @@ -137,6 +137,9 @@ void bootblock_mainboard_init(void) cubieboard_setup_clocks(); cubieboard_setup_gpios(); cubieboard_enable_uart(); +} +void bootblock_mainboard_init(void) +{ cubieboard_raminit(); }

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New patch to review for coreboot: arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13485 -gerrit commit 05000e85df47324cb446bc627203a441ec152b6d Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Tue Jan 26 18:22:43 2016 -0800 arch/x86: Implement minimal bootblock for C_ENVIRONMENT_BOTOBLOCK Some newer x86 systems can boot from non-memory-mapped boot media (e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or other memory, similar to how most ARM chipsets work. In such cases, we may not have enough code space for romstage very early on. This means that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to be implemented within the limited amount memory of storage available. Since the reset vector has to be contained in this early code memory, the bootblock is the best place to implement loading of other stages. Implement a bootblock which does the minimal initialization, up to, and including switch to protected mode. This then transfers control to platform-specific code. No stack is needed, and control is transferred via a "jmp" such that no stack operations are involved. Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/bootblock_crt0.S | 56 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 57 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 6667731..9084b11 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -112,6 +112,7 @@ $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h ifeq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) +bootblock-y += bootblock_crt0.S bootblock-y += memlayout.ld ifeq ($(CONFIG_ARCH_BOOTBLOCK_X86_32),y) diff --git a/src/arch/x86/bootblock_crt0.S b/src/arch/x86/bootblock_crt0.S new file mode 100644 index 0000000..aee5075 --- /dev/null +++ b/src/arch/x86/bootblock_crt0.S @@ -0,0 +1,56 @@ +/* + * This is the modern bootblock. It is used by platforms which select + * C_ENVIRONMENT_BOOTBLOCK, and it prepares the system for C environment runtime + * setup. The actual setup is done by hardware-specific code. + * + * It provides a bootflow similar to other architectures, and thus is considered + * to be the modern approach. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#define CR0_MP (1 << 1) +#define CR0_EM (1 << 2) + +#define CR4_OSFXSR (1 << 9) +#define CR4_OSXMMEXCPT (1 << 10) + +/* + * Include the old code for reset vector and protected mode entry. That code has + * withstood the test of time. + */ +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +.intel_syntax noprefix + +bootblock_protected_mode_entry: + /* Save BIST result */ + movd mm0, eax + /* Save an early timestamp */ + rdtsc + movd mm1, eax + movd mm2, edx + +#if !IS_ENABLED(CONFIG_SSE) +enable_sse: + mov eax, cr0 + and ax, not CR0_EM /* Clear coprocessor emulation CR0.EM */ + or ax, CR0_MP /* Set coprocessor monitoring CR0.MP */ + mov cr0, eax + mov eax, cr4 + or ax, (CR4_OSFXSR | CR4_OSXMMEXCPT) + mov cr4, eax +#endif /* IS_ENABLED(CONFIG_SSE) */ + + /* We're done. Now it's up to platform-specific code */ + jmp bootblock_pre_c_entry

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Patch set updated for coreboot: arch/x86: Rename bootblock.S to bootblock_legacy.S
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11784 -gerrit commit 3764cf3ba424af701189eb1a8a9a18a30c837e92 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Oct 2 12:42:26 2015 -0700 arch/x86: Rename bootblock.S to bootblock_legacy.S bootblock.S was used strictly for setting up the system so that the assembly generated by ROMCC could be executed. Since the infrastructure now exists to run a bootblock wihtout ROMCC, rename this file accordingly. this is done to prevent any future confusion. Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/arch/x86/Makefile.inc | 7 ++---- src/arch/x86/bootblock.S | 40 ------------------------------- src/arch/x86/bootblock_romcc.S | 53 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 55 insertions(+), 45 deletions(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bc4a7d4..6667731 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -107,9 +107,6 @@ bootblock-y += memcpy.c bootblock-y += memset.c bootblock-y += mmap_boot.c -# Add the assembly file that pulls in the rest of the dependencies in -# the right order. Make sure the auto generated bootblock.inc is a proper -# dependency. Make the same true for the linker sript. bootblock-y += id.S $(obj)/arch/x86/id.bootblock.o: $(obj)/build.h @@ -132,9 +129,9 @@ else LDFLAGS_bootblock += -m elf_x86_64 --oformat elf64-x86-64 endif -bootblock-y += bootblock.S +bootblock-y += bootblock_romcc.S bootblock-y += walkcbfs.S -$(obj)/arch/x86/bootblock.bootblock.o: $(objgenerated)/bootblock.inc +$(obj)/arch/x86/bootblock_romcc.bootblock.o: $(objgenerated)/bootblock.inc bootblock-y += bootblock.ld $(obj)/arch/x86/bootblock.bootblock.ld: $(objgenerated)/bootblock.ld diff --git a/src/arch/x86/bootblock.S b/src/arch/x86/bootblock.S deleted file mode 100644 index 27a23eb..0000000 --- a/src/arch/x86/bootblock.S +++ /dev/null @@ -1,40 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2015 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This file assembles the bootblock program by the order of the includes. Thus, - * it's extremely important that one pays very careful attention to the order - * of the includes. */ - -#include <arch/x86/prologue.inc> -#include <cpu/x86/16bit/entry16.inc> -#include <cpu/x86/16bit/reset16.inc> -#include <cpu/x86/32bit/entry32.inc> - -#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE -#endif - -#if IS_ENABLED(CONFIG_SSE) -#include <cpu/x86/sse_enable.inc> -#endif - -/* - * This bootblock.inc file is generated by ROMCC. The above program flow - * falls through to this point. ROMCC assumes the last function it parsed - * is the main function and it places its instructions at the beginning of - * the generated file. Moreover, any library/common code needed in bootblock - * needs to come after bootblock.inc. - */ -#include <generated/bootblock.inc> diff --git a/src/arch/x86/bootblock_romcc.S b/src/arch/x86/bootblock_romcc.S new file mode 100644 index 0000000..6c1723a --- /dev/null +++ b/src/arch/x86/bootblock_romcc.S @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is the original bootblock used by coreboot on x86 systems. It contains + * a monolithic code flow, assembled from the following stages: + * - reset16.inc: the reset vector + * - entry16.inc: protected mode setup + * - entry32.inc: segment descriptor setup + * - CONFIG_CHIPSET_BOOTBLOCK_INCLUDE: chipset-specific initialization + * - generated/bootblock.inc: ROMCC part of the bootblock + * + * This is used on platforms which do not select C_ENVIRONMENT_BOOTBLOCK, and it + * tries to do the absolute minimum before walking CBFS and jumping to romstage. + * + * This file assembles the bootblock program by the order of the includes. Thus, + * it's extremely important that one pays very careful attention to the order + * of the includes. + */ + +#include <arch/x86/prologue.inc> +#include <cpu/x86/16bit/entry16.inc> +#include <cpu/x86/16bit/reset16.inc> +#include <cpu/x86/32bit/entry32.inc> + +#ifdef CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#include CONFIG_CHIPSET_BOOTBLOCK_INCLUDE +#endif + +#if IS_ENABLED(CONFIG_SSE) +#include <cpu/x86/sse_enable.inc> +#endif + +/* + * This bootblock.inc file is generated by ROMCC. The above program flow + * falls through to this point. ROMCC assumes the last function it parsed + * is the main function and it places its instructions at the beginning of + * the generated file. Moreover, any library/common code needed in bootblock + * needs to come after bootblock.inc. + */ +#include <generated/bootblock.inc>

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Patch set updated for coreboot: drivers/intel/fsp1_1: Remove extra include references
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13436 -gerrit commit 23532466754582109368c4c64dda96c1e00f0021 Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:09:50 2016 -0800 drivers/intel/fsp1_1: Remove extra include references Remove include references to the soc include directory which are not required to build the FSP driver. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/raminit.c | 5 ++--- src/drivers/intel/fsp1_1/romstage.c | 6 ++---- src/soc/intel/braswell/include/soc/pm.h | 2 ++ src/soc/intel/braswell/include/soc/romstage.h | 1 - src/soc/intel/skylake/include/soc/pm.h | 2 ++ src/soc/intel/skylake/include/soc/romstage.h | 2 -- 6 files changed, 8 insertions(+), 10 deletions(-) diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2ba77e3..e505b93 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2015 Intel Corporation + * Copyright (C) 2014-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +16,11 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/memmap.h> +#include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> #include <soc/intel/common/mma.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> #include <string.h> #include <timestamp.h> #include <bootmode.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..0353c0c 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,6 +28,7 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> +#include <fsp/romstage.h> #include <fsp/util.h> #include <memory_info.h> #include <reset.h> @@ -35,10 +36,7 @@ #include <smbios.h> #include <soc/intel/common/mrc_cache.h> #include <soc/intel/common/util.h> -#include <soc/pei_wrapper.h> #include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> #include <timestamp.h> #include <tpm.h> diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..79a6592 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -235,6 +235,8 @@ struct chipset_power_state { int prev_sleep_state; } __attribute__((packed)); +struct chipset_power_state *fill_power_state(void); + /* Power Management Utility Functions. */ uint16_t get_pmbase(void); uint32_t clear_smi_status(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index e70510b..262797d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -33,7 +33,6 @@ void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -struct chipset_power_state *fill_power_state(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 79861e9..31cf7b4 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -159,6 +159,8 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *fill_power_state(void); + /* PM1_CNT */ void enable_pm1_control(uint32_t mask); void disable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 5e73e1c..e65bce2 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,8 +19,6 @@ #include <fsp/romstage.h> -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void);

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Patch set updated for coreboot: soc/braswell/acpi: Fix CID1 offset in comment
by Hannah Williams 27 Jan '16

27 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13483 -gerrit commit 3e1c88650308c4224f65f065e6aaac0c1c60d42d Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Jan 26 15:40:24 2016 -0800 soc/braswell/acpi: Fix CID1 offset in comment Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 --- src/soc/intel/braswell/acpi/globalnvs.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index e7fb2ce..5c8a75f 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -51,7 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ GPEI, 32, /* 0x19 - GPE Wake Source */ BDID, 8, /* 0x1d - Board ID */ - CID1, 16, /* 0x1A - Wifi Domain Type */ + CID1, 16, /* 0x1e - Wifi Domain Type */ /* Device Config */ Offset (0x20),

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New patch to review for coreboot: intel/strago: Update DPTF parameters to higher temperature.
by Hannah Williams 27 Jan '16

27 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13484 -gerrit commit 02313b27c1ac9fe701e223f50c13d36ac314fbe2 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Tue Sep 29 15:01:58 2015 +0530 intel/strago: Update DPTF parameters to higher temperature. Fish bowl HTML5 graphics benchmark with 250 fish is not reaching 60 FPS. This change will update the DPTF parameters to accommodate this test. TEST=Run fish bowl benchmark with 250 fish and check for 60 FPS. Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5 Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/302208 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/strago/acpi/dptf.asl | 27 ++++++++------------------- src/mainboard/intel/strago/onboard.h | 3 +++ 2 files changed, 11 insertions(+), 19 deletions(-) diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index b875b93..2a95703 100755 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -16,19 +16,19 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 85 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 75 #define DPTF_ENABLE_CHARGER @@ -50,18 +50,7 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -69,7 +58,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 1600, /* PowerLimitMinimum */ + 2000, /* PowerLimitMinimum */ 6200, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 89c9b69..d93608b 100755 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -74,4 +74,7 @@ #define BCRD2_PMIC_I2C_BUS 0x01 +#define DPTF_CPU_PASSIVE 88 +#define DPTF_CPU_CRITICAL 90 + #endif

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coreboot-gerrit January 2016