coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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2471 discussions

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Enable ASUS MIO audio option
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13152 -gerrit commit b2cc5789db1791e5c3c9b12f04915c2ddcecef97 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:55 2015 -0600 mainboard/asus/kgpe-d16: Enable ASUS MIO audio option The KGPE-D16 supports an optional MIO audio card, which connects to the on-board HDA interface of the SP5100. Enable the HDA interface for use with the MIO card. Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/asus/kgpe-d16/devicetree.cb b/src/mainboard/asus/kgpe-d16/devicetree.cb index 014a35f..96372f9 100644 --- a/src/mainboard/asus/kgpe-d16/devicetree.cb +++ b/src/mainboard/asus/kgpe-d16/devicetree.cb @@ -175,7 +175,7 @@ chip northbridge/amd/amdfam10/root_complex # Root complex end end device pci 14.1 on end # IDE 0x439c - device pci 14.2 off end # HDA 0x4383 (KGPE-D16 omits audio option) + device pci 14.2 on end # HDA 0x4383 (ASUS MIO add-on card) device pci 14.3 on # LPC 0x439d (SMBUS primary controller) chip superio/nuvoton/nct5572d # Super I/O device pnp 2e.0 off end # FDC; Not available on the KGPE-D16

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13153 -gerrit commit 7427b85ffd1301fb4ad5b0d48988705564ef6d45 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:55 2015 -0600 mainboard/asus/kgpe-d16: Use stock PS/2 ACPI ASL file Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/dsdt.asl | 43 +++--------------------------------- 1 file changed, 3 insertions(+), 40 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/dsdt.asl b/src/mainboard/asus/kgpe-d16/dsdt.asl index 8445eb3..44b6a98 100644 --- a/src/mainboard/asus/kgpe-d16/dsdt.asl +++ b/src/mainboard/asus/kgpe-d16/dsdt.asl @@ -92,8 +92,8 @@ DefinitionBlock ( /* Keyboard controller PME# */ Method(_L08) { /* Level-Triggered GPE */ - Notify(\_SB.PCI0.LPC.KBD, 0x02) /* NOTIFY_DEVICE_WAKE */ - Notify(\_SB.PCI0.LPC.MOU, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.PS2K, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.LPC.PS2M, 0x02) /* NOTIFY_DEVICE_WAKE */ Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ } @@ -490,44 +490,7 @@ DefinitionBlock ( Name (_HID, EisaId ("PNP0A05")) Name (_ADR, 0x00140003) - /* PS/2 keyboard (seems to be important for WinXP install) */ - Device (KBD) - { - Name (_HID, EisaId ("PNP0303")) - Name (_CID, EisaId ("PNP030B")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) - IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) - IRQNoFlags () {1} - }) - Return (TMP) - } - } - - /* PS/2 mouse */ - Device (MOU) - { - Name (_HID, EisaId ("PNP0F03")) - Name (_CID, EisaId ("PNP0F13")) - Method (_STA, 0, NotSerialized) - { - Return (0x0f) - } - Method (_CRS, 0, Serialized) - { - Name (TMP, ResourceTemplate () { - IRQNoFlags () {12} - }) - Return (TMP) - } - } - + #include "../../../drivers/pc80/ps2_controller.asl" /* UART 1 */ Device (URT1)

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Patch set updated for coreboot: southbridge/amd/sb700: Add missing DMA setup step from AMD RRG
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13154 -gerrit commit a436fa86dd56b85aceadba13dcd6f7ea269b2ac5 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:56 2015 -0600 southbridge/amd/sb700: Add missing DMA setup step from AMD RRG Change-Id: I412a0e5f2e0686b10a295dd7c0e9b537dc1a0940 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/early_setup.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/southbridge/amd/sb700/early_setup.c b/src/southbridge/amd/sb700/early_setup.c index 3733314..76855fb 100644 --- a/src/southbridge/amd/sb700/early_setup.c +++ b/src/southbridge/amd/sb700/early_setup.c @@ -420,6 +420,11 @@ static void sb700_devices_por_init(void) /* Legacy DMA Prefetch Enhancement, CIM masked it. */ /* pci_write_config8(dev, 0x43, 0x1); */ + /* Enable DMA verify bugfix */ + byte = pci_read_config8(dev, 0x67); + byte |= 0x1 << 1; + pci_write_config8(dev, 0x67, byte); + /* Disabling Legacy USB Fast SMI# */ byte = pci_read_config8(dev, 0x62); byte |= 0x24;

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Patch set updated for coreboot: southbridge/amd/sb700: Add CMOS option to disable legacy USB support
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13155 -gerrit commit 28fcd88234216e55256cdce2090f7a49445198bf Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:56 2015 -0600 southbridge/amd/sb700: Add CMOS option to disable legacy USB support Change-Id: I136c259136ce66a0c319a965ae0ee27f66dce1b3 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/southbridge/amd/sb700/sm.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/sb700/sm.c b/src/southbridge/amd/sb700/sm.c index 7c9c004..5f6d20e 100644 --- a/src/southbridge/amd/sb700/sm.c +++ b/src/southbridge/amd/sb700/sm.c @@ -66,6 +66,7 @@ static void sm_init(device_t dev) u32 dword; void *ioapic_base; uint32_t power_state; + uint32_t enable_legacy_usb; u32 nmi_option; printk(BIOS_INFO, "sm_init().\n"); @@ -75,10 +76,23 @@ static void sm_init(device_t dev) ioapic_base = (void *)(pci_read_config32(dev, 0x74) & (0xffffffe0)); setup_ioapic(ioapic_base, 0); /* Don't rename IOAPIC ID. */ + enable_legacy_usb = 1; + get_option(&enable_legacy_usb, "enable_legacy_usb"); + /* 2.10 Interrupt Routing/Filtering */ - dword = pci_read_config8(dev, 0x62); - dword |= 3; - pci_write_config8(dev, 0x62, dword); + byte = pci_read_config8(dev, 0x62); + if (enable_legacy_usb) + byte |= 0x3; + else + byte &= ~0x3; + pci_write_config8(dev, 0x62, byte); + + byte = pci_read_config8(dev, 0x67); + if (enable_legacy_usb) + byte |= 0x1 << 7; + else + byte &= ~(0x1 << 7); + pci_write_config8(dev, 0x67, byte); /* Delay back to back interrupts to the CPU. */ dword = pci_read_config16(dev, 0x64);

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Move memory test before IMD setup
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13151 -gerrit commit 971b4c4ffc4785100c593d5929e3c6a789ff070b Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:54 2015 -0600 mainboard/asus/kgpe-d16: Move memory test before IMD setup Change-Id: Ic6fbf6688e4c2adc85e4eb9fa17e79d29dda58c0 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/romstage.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/romstage.c b/src/mainboard/asus/kgpe-d16/romstage.c index c29ac5f..13af96f 100644 --- a/src/mainboard/asus/kgpe-d16/romstage.c +++ b/src/mainboard/asus/kgpe-d16/romstage.c @@ -541,6 +541,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); timestamp_add_now(TS_AFTER_INITRAM); +#ifdef TEST_MEMORY + execute_memory_test(); +#endif + #if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) if (s3resume) cbmem_initialize(); @@ -565,10 +569,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) timestamp_add_now(TS_END_ROMSTAGE); -#ifdef TEST_MEMORY - execute_memory_test(); -#endif - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }

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Patch set updated for coreboot: nb/amdmct/mct_ddr3: Enable mainboard voltage set
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13150 -gerrit commit 0a8d15aa1b73960849139eb3e48e38023cd741de Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:53 2015 -0600 nb/amdmct/mct_ddr3: Enable mainboard voltage set The existing code used an incorrect macro name to check for mainboard DRAM voltage set support, and as a result no voltages were actually set. Furthermore, the existing code did not contain a centralized voltage assumption for boards that did not have a DIMM voltage set implementation. Use the correct macro name to test for boards with voltage set implementation, and provide a basic fallback to 1.5V operation for boards without a voltage set implementation. Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 9724008..e1c0d4f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -254,6 +254,10 @@ static uint8_t dct_ddr_voltage_index(struct DCTStatStruc *pDCTstat, uint8_t dct) uint8_t dimm; uint8_t ddr_voltage_index = 0; + /* If no DIMMs are present on this DCT, report 1.5V operation and skip checking the hardware */ + if (pDCTstat->DIMMValidDCT[dct] == 0) + return 0x1; + /* Find current DDR supply voltage for this DCT */ for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { if (pDCTstat->DIMMValidDCT[dct] & (1 << dimm)) @@ -2409,6 +2413,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, */ u8 Node, NodesWmem; u32 node_sys_base; + uint8_t dimm; uint8_t nvram; uint8_t enable_cc6; uint8_t allow_config_restore; @@ -2498,10 +2503,25 @@ restartinit: nvram = 0; set_option("allow_spd_nvram_cache_restore", &nvram); -#if IS_ENABLED(DIMM_VOLTAGE_SET_SUPPORT) +#if IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT) printk(BIOS_DEBUG, "%s: DIMMSetVoltage\n", __func__); DIMMSetVoltages(pMCTstat, pDCTstatA); /* Set the DIMM voltages (mainboard specific) */ #endif + if (!IS_ENABLED(CONFIG_DIMM_VOLTAGE_SET_SUPPORT)) { + /* Assume 1.5V operation */ + for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) { + struct DCTStatStruc *pDCTstat; + pDCTstat = pDCTstatA + Node; + + if (!pDCTstat->NodePresent) + continue; + + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + if (pDCTstat->DIMMValid & (1 << dimm)) + pDCTstat->DimmConfiguredVoltage[dimm] = 0x1; + } + } + } /* If DIMM configuration has not changed since last boot restore training values */ allow_config_restore = 1;

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13149 -gerrit commit 1b400c2198604f8c0f4676f7d7e9ea69f407e86c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:53 2015 -0600 cpu/amd/fam10h-fam15h: Correctly create APIC ID on single node systems The existing code generated an incorrect boot APIC ID from node and core number for single node packages, leading to a boot failure when the second node was installed. Properly generate the boot APIC ID from node and core number. Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 6 +++++- src/northbridge/amd/amdfam10/northbridge.c | 4 +++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index 1794072..5a67601 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -127,13 +127,17 @@ uint32_t get_boot_apic_id(uint8_t node, uint32_t core) { } } else { if (fam15h) { - ap_apicid = (node * (siblings + 1)) + core; + ap_apicid = 0; + ap_apicid |= (node & 0x7) << 4; /* Node ID */ + ap_apicid |= core & 0xf; /* Core ID */ } else { ap_apicid = node * (nb_cfg_54 ? (siblings + 1) : 1) + core * (nb_cfg_54 ? 1 : 64); } } + printk(BIOS_DEBUG, "%s: using %d as APIC ID for node %d, core %d\n", __func__, ap_apicid, node, core); + return ap_apicid; } diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 563f21b..3b747bd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1637,7 +1637,9 @@ static void cpu_bus_scan(device_t dev) } } else { if (fam15h) { - apic_id = (i * (siblings + 1)) + j; + apic_id = 0; + apic_id |= (i & 0x7) << 4; /* Node ID */ + apic_id |= j & 0xf; /* Core ID */ } else { apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:64); // ? }

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13148 -gerrit commit 0492e8abdb62bd9b7ce774f8ba47bdfc3380cc91 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:11:52 2015 -0600 nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h Certain registered DIMMs failed training due to an error likely introduced during historical rebase. Ensure that the SubMemclkRegDly bit is set according to BKDG recommendations on Family 15 processors. Change-Id: I24c95265dada9eabf4df280b6f2b4a1eb9cecaf1 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c index cf13b40..fc62afb 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c @@ -66,6 +66,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat, misc2 |= ((cs_mux_67 & 0x1) << 27); misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */ misc2 |= ((cs_mux_45 & 0x1) << 26); + + if (pDCTstat->Status & (1 << SB_Registered)) + misc2 |= 1 << SubMemclkRegDly; } else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) { if (pDCTstat->Status & (1 << SB_Registered)) { misc2 |= 1 << SubMemclkRegDly;

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Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add CPB control CMOS option
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13173 -gerrit commit 4af6a0d77cbd933a0c10e2835cfd95418dd8b623 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 mainboard/asus/kgpe-d16: Add CPB control CMOS option Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/cmos.default | 1 + src/mainboard/asus/kgpe-d16/cmos.layout | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default index a05b9c3..0e7afb3 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.default +++ b/src/mainboard/asus/kgpe-d16/cmos.default @@ -17,6 +17,7 @@ interleave_nodes = Disable interleave_memory_channels = Enable cpu_c_states = Enable cpu_cc6_state = Enable +cpu_core_boost = Enable sata_ahci_mode = Enable sata_alpm = Disable maximum_p_state_limit = 0xf diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index d1c0702..075388e 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -48,8 +48,9 @@ entries 476 1 e 1 l3_cache_partitioning 477 1 e 1 ieee1394_controller 478 1 e 1 iommu -479 1 e 1 experimental_memory_speed_boost -480 1 r 0 allow_spd_nvram_cache_restore +479 1 e 1 cpu_core_boost +480 1 e 1 experimental_memory_speed_boost +481 1 r 0 allow_spd_nvram_cache_restore 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers

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Patch set updated for coreboot: cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost)
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13172 -gerrit commit e426fb7d5d720665a67001df59c8ff34d13f1609 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:07 2015 -0600 cpu/amd/fam10h-fam15h: Add CMOS option to disable CPB (core boost) On certain systems and CPUs Core Performance Boost (CPB) may cause sporadic system lockups. This issue is also somewhat known on the various proprietary BIOSes, therefore it seems to be a hardware incompatibility when present. Allow the user to disable CBP if needed. Change-Id: Id6395d067d48963f6c084ad0bf79e23419af24d8 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/cpu/amd/family_10h-family_15h/init_cpus.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/cpu/amd/family_10h-family_15h/init_cpus.c b/src/cpu/amd/family_10h-family_15h/init_cpus.c index e2a1bf3..c1ff240 100644 --- a/src/cpu/amd/family_10h-family_15h/init_cpus.c +++ b/src/cpu/amd/family_10h-family_15h/init_cpus.c @@ -987,6 +987,7 @@ void cpuSetAMDMSR(uint8_t node_id) u32 platform; uint64_t revision; uint8_t enable_c_states; + uint8_t enable_cpb; printk(BIOS_DEBUG, "cpuSetAMDMSR "); @@ -1078,6 +1079,19 @@ void cpuSetAMDMSR(uint8_t node_id) enable_c_states = 0; #endif + if (revision & AMD_FAM15_ALL) { + enable_cpb = 1; + if (get_option(&nvram, "cpu_core_boost") == CB_SUCCESS) + enable_cpb = !!nvram; + + if (!enable_cpb) { + /* Disable Core Performance Boost */ + msr = rdmsr(0xc0010015); + msr.lo |= (0x1 << 25); /* CpbDis = 1 */ + wrmsr(0xc0010015, msr); + } + } + printk(BIOS_DEBUG, " done\n"); }

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coreboot-gerrit January 2016