coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/x4x: Move to early cbmem
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13131 -gerrit commit b6b5c013f6583bca4e5f89c479c8ce8fdb9fcfad Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 22:12:30 2016 +1100 nb/intel/x4x: Move to early cbmem Previously with errors in the ram init, early cbmem was disabled. Now that the ram is working correctly, set as early cbmem platform and update all (1) boards to use it. Tested on GA-G41M-ES2L Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 1 + src/northbridge/intel/x4x/Kconfig | 2 +- src/northbridge/intel/x4x/northbridge.c | 3 --- src/northbridge/intel/x4x/ram_calc.c | 7 +++++++ 4 files changed, 9 insertions(+), 4 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 6bae128..ca8ca5c 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -159,5 +159,6 @@ void main(unsigned long bist) printk(BIOS_DEBUG, "Initializing memory\n"); sdram_initialize(0, spd_addrmap); quick_ram_check(); + cbmem_initialize_empty(); printk(BIOS_DEBUG, "Memory initialized\n"); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index c330fd5..f643bb2 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,7 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT config BOOTBLOCK_NORTHBRIDGE_INIT string diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index 9704b82..8c71026 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -29,7 +29,6 @@ #include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> -#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { @@ -112,8 +111,6 @@ static void mch_domain_read_resources(device_t dev) fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } - - set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index f11b19a..27562ea 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -17,6 +17,7 @@ #define __SIMPLE_DEVICE__ +#include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> #include <arch/io.h> @@ -86,3 +87,9 @@ u8 decode_pciebar(u32 *const base, u32 *const len) *len = max_buses << 20; return 1; } + +void *cbmem_top(void) +{ + u32 ramtop = pci_read_config32(PCI_DEV(0,0,0), D0F0_TSEG); + return (void*)(ramtop); +}

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13465 -gerrit commit 67e34bb9a84b8139032dee738f4f23ce0fceef39 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:17:27 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove copy-pasted cstates Change-Id: I5b6edbd97d4e6ed8b03f2f319a338022647e26ea Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/cstates.c | 13 +------------ src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 3 --- 2 files changed, 1 insertion(+), 15 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c index dbac2ed..4d9f4ab 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cstates.c @@ -17,18 +17,7 @@ #include <device/device.h> #include <southbridge/intel/i82801gx/i82801gx.h> -static acpi_cstate_t cst_entries[] = { - { - /* acpi C1 / cpu C1 */ - 1, 0x01, 1000, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0, 0 } - }, - { - /* acpi C2 / cpu C2 */ - 2, 0x01, 500, - { ACPI_ADDRESS_SPACE_FIXED, 1, 2, { 1 }, 0x10, 0 } - }, -}; +static acpi_cstate_t cst_entries[] = {}; int get_cst_entries(acpi_cstate_t **entries) { diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index e6b691c..3965538 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -21,9 +21,6 @@ chip northbridge/intel/x4x # Northbridge end chip cpu/intel/model_1067x # CPU device lapic 0xACAC off end - register "slfm" = "1" - register "c5" = "1" - register "c6" = "1" end end device domain 0 on # PCI domain

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Patch set updated for coreboot: nb/intel/x4x: Cleanup gma.c
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13128 -gerrit commit 501da4dc800267cd0b7fd0776578004717d13321 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:13:18 2016 +1100 nb/intel/x4x: Cleanup gma.c Tidy up the code and move vga_textmode_init() later Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/gma.c | 81 ++++++++++++----------------------------- 1 file changed, 24 insertions(+), 57 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 7891229..2679026 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -35,27 +35,14 @@ #include <pc80/vga.h> #include <pc80/vga_io.h> -static struct resource *gtt_res = NULL; - -void gtt_write(u32 reg, u32 data) -{ - write32(res2mmio(gtt_res, reg, 0), data); -} - static void intel_gma_init(const struct northbridge_intel_x4x_config *info, - u8 *mmio, u32 physbase, u16 piobase, u32 lfb) + u8 *mmio) { int i; u32 hactive, vactive; - vga_gr_write(0x18, 0); - /* Setup GTT. */ - for (i = 0; i < 0x2000; i++) - { - outl((i << 2) | 1, piobase); - outl(physbase + (i << 12) + 1, piobase + 4); - } + vga_gr_write(0x18, 0); write32(mmio + VGA0, 0x31108); write32(mmio + VGA1, 0x31406); @@ -92,8 +79,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, hactive = 640; vactive = 400; - vga_textmode_init(); - mdelay(1); write32(mmio + FP0(0), 0x31108); write32(mmio + DPLL(0), @@ -152,7 +137,8 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + 0x000f000c, 0x00002050); write32(mmio + 0x00060100, 0x00044000); mdelay(1); - write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); + write32(mmio + PIPECONF(0), PIPECONF_ENABLE + | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + VGACNTRL, 0x0); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); @@ -168,7 +154,7 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, | ADPA_DPMS_ON ); - write32(mmio + PP_CONTROL, PANEL_POWER_ON); + vga_textmode_init(); /* Enable screen memory. */ vga_sr_write(1, vga_sr_read(1) & ~0x20); @@ -178,6 +164,22 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, write32(mmio + SDEIIR, 0xffffffff); } +static void native_init(struct device *dev) +{ + struct resource *gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); + struct northbridge_intel_x4x_config *conf = dev->chip_info; + + if (gtt_res && gtt_res->base) { + printk(BIOS_SPEW, + "Initializing VGA without OPROM. MMIO 0x%llx\n", + gtt_res->base); + intel_gma_init(conf, res2mmio(gtt_res, 0, 0)); + } + + /* Linux relies on VBT for panel info. */ + generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); +} + static void gma_func0_init(struct device *dev) { u32 reg32; @@ -187,43 +189,10 @@ static void gma_func0_init(struct device *dev) reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; pci_write_config32(dev, PCI_COMMAND, reg32); - /* Init graphics power management */ - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - - struct northbridge_intel_x4x_config *conf = dev->chip_info; - - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); - } else { - u32 physbase; - struct resource *lfb_res; - struct resource *pio_res; - - lfb_res = find_resource(dev, PCI_BASE_ADDRESS_2); - pio_res = find_resource(dev, PCI_BASE_ADDRESS_4); - - physbase = pci_read_config32(dev, 0x5c) & ~0xf; - - if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base - && lfb_res && lfb_res->base) { - printk(BIOS_SPEW, "Initializing VGA without OPROM. MMIO 0x%llx\n", - gtt_res->base); - intel_gma_init(conf, res2mmio(gtt_res, 0, 0), physbase, - pio_res->base, lfb_res->base); - } - - /* Linux relies on VBT for panel info. */ - generate_fake_intel_oprom(&conf->gfx, dev, "$VBT EAGLELAKE "); - } - - /* Post VBIOS init */ - /* Enable Backlight */ - gtt_write(BLC_PWM_CTL2, (1 << 31)); - if (conf->gfx.backlight == 0) - gtt_write(BLC_PWM_CTL, 0x06100610); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) + native_init(dev); else - gtt_write(BLC_PWM_CTL, conf->gfx.backlight); + pci_dev_init(dev); } static void gma_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -269,8 +238,6 @@ static struct device_operations gma_func0_ops = { .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = gma_ssdt, .init = gma_func0_init, - .scan_bus = 0, - .enable = 0, .ops_pci = &gma_pci_ops, };

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code.
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13466 -gerrit commit 11d62486525a91fbe77bd871ed5502562c516700 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:24:48 2016 +1100 mb/gigabyte/ga-g41m-es2l: Remove PMBASE settings and commented code. Fixed incorrect comment regarding port 80 LPC route. Change-Id: Ifbb73753d5a0737418b869085f2329a02504e5dc Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index ca8ca5c..bff481f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -58,21 +58,6 @@ static void mb_gpio_init(void) outl(0x000000f0, DEFAULT_GPIOBASE + 0x34); outl(0x00000083, DEFAULT_GPIOBASE + 0x38); - /* Set default power management registers */ - pci_write_config32(dev, PMBASE, DEFAULT_PMBASE | 1); - outw(0x0011, DEFAULT_PMBASE + 0x00); - outw(0x0120, DEFAULT_PMBASE + 0x02); - outl(0x00001c01, DEFAULT_PMBASE + 0x04); - outl(0x00bb29d2, DEFAULT_PMBASE + 0x08); - outl(0x000000a0, DEFAULT_PMBASE + 0x10); - outl(0xc5000000, DEFAULT_PMBASE + 0x28); - outl(0x00000040, DEFAULT_PMBASE + 0x2c); - outw(0x13e0, DEFAULT_PMBASE + 0x44); - outw(0x003f, DEFAULT_PMBASE + 0x60); - outw(0x0800, DEFAULT_PMBASE + 0x68); - outw(0x0008, DEFAULT_PMBASE + 0x6a); - outw(0x003f, DEFAULT_PMBASE + 0x72); - /* Set default GPIOs on superio */ ite_reg_write(GPIO_DEV, 0x25, 0x00); ite_reg_write(GPIO_DEV, 0x26, 0xc7); @@ -137,8 +122,8 @@ void main(unsigned long bist) // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - /* Disable watchdog timer and route port 80 to LPC */ - RCBA32(0x3410) = (RCBA32(0x3410) | 0x20);// & ~0x4; + /* Disable watchdog timer */ + RCBA32(0x3410) = RCBA32(0x3410) | 0x20; /* Set southbridge and Super I/O GPIOs. */ mb_gpio_init();

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Patch set updated for coreboot: mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13129 -gerrit commit f1aa8f02e36a290a2df50cc6bf178ba9afa78297 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Jan 26 17:15:55 2016 +1100 mb/gigabyte/ga-g41m-es2l: Move MMCONF base address to 0xe0000000 Change-Id: I3873d92069cc1d113a8092d609d1768ff45cbd45 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/gigabyte/ga-g41m-es2l/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig index cf1077b..0a26f83 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Kconfig @@ -29,7 +29,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xc0000000 + default 0xe0000000 config MAINBOARD_DIR string

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Patch set updated for coreboot: nb/intel/x4x: Tidy up northbridge
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13126 -gerrit commit e4f4147cd8c631a61164069d62074dd878f250d6 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:05 2016 +1100 nb/intel/x4x: Tidy up northbridge - Add device enable macros - Set the PMBASE correctly through southbridge device Change-Id: I1b8cc3de96b1ecaf01e31bad8fba1fada8671c2d Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/early_init.c | 11 +++-------- src/northbridge/intel/x4x/x4x.h | 11 ++++++++++- 2 files changed, 13 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index b98c42e..b522293 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -22,8 +22,6 @@ void x4x_early_init(void) { - u16 reg16; - const device_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ @@ -36,12 +34,11 @@ void x4x_early_init(void) pci_write_config32(d0f0, D0F0_EPBAR_LO, DEFAULT_EPBAR | 1); /* Setup PMBASE */ - pci_write_config32(d0f0, D0F0_PMBASE, DEFAULT_PMBASE | 1); + pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x44 /* ACPI_CNTL */ , 0x80); /* Setup HECIBAR */ pci_write_config32(PCI_DEV(0,3,0), 0x10, DEFAULT_HECIBAR); - reg16 = pci_read_config16(PCI_DEV(0,3,0), 0x4); - pci_write_config16(PCI_DEV(0,3,0), 0x4, reg16 | 0x6); /* Set C0000-FFFFF to access RAM on both reads and writes */ pci_write_config8(d0f0, D0F0_PAM(0), 0x30); @@ -53,8 +50,6 @@ void x4x_early_init(void) pci_write_config8(d0f0, D0F0_PAM(6), 0x33); /* Enable internal GFX */ + pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); pci_write_config16(d0f0, D0F0_GGC, 0x0170); - - reg16 = pci_read_config16(d0f0, D0F0_DEVEN); - pci_write_config16(d0f0, D0F0_DEVEN, reg16 | 0x8); } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index c226950..e1ef745 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -27,11 +27,20 @@ #define D0F0_MCHBAR_HI 0x4c #define D0F0_GGC 0x52 #define D0F0_DEVEN 0x54 +#define D0EN (1 << 0) +#define D1EN (1 << 1) +#define IGD0EN (1 << 3) +#define IGD1EN (1 << 4) +#define D3F0EN (1 << 6) +#define D3F1EN (1 << 7) +#define D3F2EN (1 << 8) +#define D3F3EN (1 << 9) +#define PEG1EN (1 << 13) +#define BOARD_DEVEN (D0EN | D1EN | IGD0EN | IGD1EN) #define D0F0_PCIEXBAR_LO 0x60 #define D0F0_PCIEXBAR_HI 0x64 #define D0F0_DMIBAR_LO 0x68 #define D0F0_DMIBAR_HI 0x6c -#define D0F0_PMBASE 0x78 #define D0F0_PAM(x) (0x90+(x)) /* 0-6*/ #define D0F0_REMAPBASE 0x98 #define D0F0_REMAPLIMIT 0x9a

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Patch set updated for coreboot: nb/intel/x4x: Tidy up raminit and fix msbpos() function
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13127 -gerrit commit d1de33d6d3b43b72b93190544d2a96da533256d1 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 19:11:44 2016 +1100 nb/intel/x4x: Tidy up raminit and fix msbpos() function - Fix bug with msbpos, it was not returning the correct result due to typo in logic, and unsigned value needed to be negative. - Add reclaim above 4GiB - Fix to ME related registers near the end of raminit Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit_ddr2.c | 55 +++++++++++++++++++++++++++----- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d21924b..3dd00fb 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -45,14 +45,22 @@ static u32 ddr2mhz(u32 speed) return mhz[speed]; } -static u8 msbpos(u8 val) //Reverse +/* Find MSB bitfield location using bit scan reverse instruction */ +static u8 msbpos(u32 val) { - u8 i; - for (i = 7; i >= 0; i--) { - if ((val & (1 << i)) == 0) - break; + u32 pos; + + if (val == 0) { + printk(BIOS_WARNING, "WARNING: Input to BSR is zero\n"); + return 0; } - return i; + + asm ("bsrl %1, %0" + :"=r"(pos) + :"r"(val) + ); + + return (u8)(pos & 0xff); } static void sdram_detect_smallest_params2(struct sysinfo *s) @@ -1614,7 +1622,9 @@ static void dradrb_ddr2(struct sysinfo *s) static void mmap_ddr2(struct sysinfo *s) { - u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; + bool reclaim; + u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud; + u32 gfxbase, gttbase, tsegbase, reclaimbase, reclaimlimit; u16 ggc; u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; @@ -1626,13 +1636,34 @@ static void mmap_ddr2(struct sysinfo *s) mmiosize = 0x400; // 1GB MMIO tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); + + reclaim = false; + if ((tom - tolud) > 0x40) + reclaim = true; + + if (reclaim) { + tolud = tolud & ~0x3f; + tom = tom & ~0x3f; + reclaimbase = MAX(0x1000, tom); + reclaimlimit = reclaimbase + (MIN(0x1000, tom) - tolud) - 0x40; + } + touud = tom; + if (reclaim) + touud = reclaimlimit + 0x40; + gfxbase = tolud - gfxsize; gttbase = gfxbase - gttsize; tsegbase = gttbase - tsegsize; pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); + if (reclaim) { + pci_write_config16(PCI_DEV(0,0,0), 0x98, + (u16)(reclaimbase >> 6)); + pci_write_config16(PCI_DEV(0,0,0), 0x9a, + (u16)(reclaimlimit >> 6)); + } pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); @@ -1993,7 +2024,15 @@ void raminit_ddr2(struct sysinfo *s) printk(BIOS_DEBUG, "Done power settings\n"); // ME related - //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); + if (RANK_IS_POPULATED(s->dimms, 0, 0) + || RANK_IS_POPULATED(s->dimms, 1, 0)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0); + } + if (RANK_IS_POPULATED(s->dimms, 0, 1) + || RANK_IS_POPULATED(s->dimms, 1, 1)) { + MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1); + } + MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); }

1 0

Patch set updated for coreboot: nb/intel/x4x: Fix memory hole with both channels populated
by Damien Zammit 27 Jan '16

27 Jan '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13125 -gerrit commit 2ab70d635e03ff7d12e5d737d17751426468531e Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jan 22 18:56:23 2016 +1100 nb/intel/x4x: Fix memory hole with both channels populated Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/northbridge.c | 62 +++++++++++++++----------------- src/northbridge/intel/x4x/raminit_ddr2.c | 53 ++++++++++++++++++--------- 2 files changed, 65 insertions(+), 50 deletions(-) diff --git a/src/northbridge/intel/x4x/northbridge.c b/src/northbridge/intel/x4x/northbridge.c index c5a8968..9704b82 100644 --- a/src/northbridge/intel/x4x/northbridge.c +++ b/src/northbridge/intel/x4x/northbridge.c @@ -26,25 +26,24 @@ #include <cpu/cpu.h> #include <boot/tables.h> #include <arch/acpi.h> +#include <northbridge/intel/x4x/iomap.h> #include <northbridge/intel/x4x/chip.h> #include <northbridge/intel/x4x/x4x.h> - -/* Reserve segments A and B: - * - * 0xa0000 - 0xbffff: legacy VGA - */ -static const int legacy_hole_base_k = 0xa0000 / 1024; -static const int legacy_hole_size_k = 128; +#include <cbmem.h> static void mch_domain_read_resources(device_t dev) { + u8 index; u64 tom, touud; - u32 tomk, tsegk, tolud, usable_tomk; + u32 tomk, tseg_sizek, tolud, usable_tomk; u32 pcie_config_base, pcie_config_size; u32 uma_sizek = 0; + const u32 top32memk = 4 * (GiB / KiB); + index = 3; + /* 1024KiB TSEG */ - tsegk = 1 << 10; + tseg_sizek = 1024; pci_domain_read_resources(dev); @@ -77,53 +76,52 @@ static void mch_domain_read_resources(device_t dev) const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf); printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10); - uma_sizek = gms_sizek + gsm_sizek + tsegk; + uma_sizek = gms_sizek + gsm_sizek + tseg_sizek; usable_tomk = tomk - uma_sizek; printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10); /* Report the memory regions */ - ram_resource(dev, 3, 0, legacy_hole_base_k); - ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k, - (usable_tomk - (legacy_hole_base_k + legacy_hole_size_k))); + ram_resource(dev, index++, 0, 0xa0000 >> 10); + ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10))); /* * If >= 4GB installed then memory from TOLUD to 4GB * is remapped above TOM, TOUUD will account for both */ touud >>= 10; /* Convert to KB */ - if (touud > 4096 * 1024) { - ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024)); + if (touud > top32memk) { + ram_resource(dev, index++, top32memk, touud - top32memk); printk(BIOS_INFO, "Available memory above 4GB: %lluM\n", - (touud >> 10) - 4096); + (touud - top32memk) >> 10); } printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x " - "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); - fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE); + "size=0x%08x\n", usable_tomk << 10, uma_sizek << 10); + fixed_mem_resource(dev, index++, usable_tomk, uma_sizek, + IORESOURCE_RESERVE); - /* Some strange hole, reserve it */ - //fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE); + /* Reserve high memory where the NB BARs are up to 4GiB */ + fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10, + (top32memk*KiB - DEFAULT_HECIBAR) >> 10, + IORESOURCE_RESERVE); if (decode_pciebar(&pcie_config_base, &pcie_config_size)) { printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " "size=0x%x\n", pcie_config_base, pcie_config_size); - fixed_mem_resource(dev, 7, pcie_config_base >> 10, + fixed_mem_resource(dev, index++, pcie_config_base >> 10, pcie_config_size >> 10, IORESOURCE_RESERVE); } + + set_top_of_ram(usable_tomk * 1024); } static void mch_domain_set_resources(device_t dev) { - struct resource *resource; - int i; - - for (i = 3; i < 8; ++i) { - /* Report read resources. */ - resource = probe_resource(dev, i); - if (resource) - report_resource_stored(dev, resource, ""); - } + struct resource *res; + + for (res = dev->resource_list; res; res = res->next) + report_resource_stored(dev, res, ""); assign_resources(dev->link_list); } @@ -141,10 +139,9 @@ static void mch_domain_init(device_t dev) static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, - .enable_resources = NULL, .init = mch_domain_init, .scan_bus = pci_domain_scan_bus, - .ops_pci_bus = pci_bus_default_ops, + .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, }; @@ -160,7 +157,6 @@ static struct device_operations cpu_bus_ops = { .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, .init = cpu_bus_init, - .scan_bus = 0, }; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index d77c2c4..d21924b 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -23,6 +23,8 @@ #include "iomap.h" #include "x4x.h" +#define ME_UMA_SIZEMB 0 + static inline void barrier(void) { asm volatile("mfence":::); @@ -1465,7 +1467,8 @@ static void dradrb_ddr2(struct sysinfo *s) u32 dra0; u32 dra1; u16 totalmemorymb; - u16 size, offset; + u32 size, offset; + u32 size0, size1; u8 dratab[2][2][2][4] = { { { @@ -1562,35 +1565,51 @@ static void dradrb_ddr2(struct sysinfo *s) MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; } - MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; - MCHBAR16(0x104) = 0; - size = s->channel_capacity[0] + s->channel_capacity[1]; - MCHBAR16(0x102) = size; + /* Populated channel sizes in MiB */ + size0 = s->channel_capacity[0]; + size1 = s->channel_capacity[1]; + + MCHBAR8(0x111) = MCHBAR8(0x111) & ~0x2; + MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4); + + /* Set ME UMA size in MiB */ + MCHBAR16(0x100) = ME_UMA_SIZEMB; + + /* Set ME UMA Present bit */ + MCHBAR32(0x111) = MCHBAR32(0x111) | 1; + + size = MIN(size0 - ME_UMA_SIZEMB, size1) * 2; + + MCHBAR16(0x104) = size; + MCHBAR16(0x102) = size0 + size1 - size; + map = 0; - if (s->channel_capacity[0] == 0) { + if (size0 == 0) { map = 0; - } else if (s->channel_capacity[1] == 0) { + } else if (size1 == 0) { map |= 0x20; } else { map |= 0x40; } - map |= 0x18; - if (s->channel_capacity[0] <= s->channel_capacity[1]) { - map |= 0x5; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { + if (size == 0) { + map |= 0x18; + } + + if (size0 - ME_UMA_SIZEMB >= size1) { map |= 0x4; } MCHBAR8(0x110) = map; MCHBAR16(0x10e) = 0; - if (s->channel_capacity[1] != 0) { + + if (size1 != 0) { offset = 0; - } else if (s->channel_capacity[0] > s->channel_capacity[1]) { - offset = size; + } else if ((size0 > size1) && ((map & 0x7) == 0x4)) { + offset = size/2 + (size0 + size1 - size); } else { - offset = 0; + offset = size/2 + ME_UMA_SIZEMB; } MCHBAR16(0x108) = offset; - MCHBAR16(0x10a) = 0; + MCHBAR16(0x10a) = size/2; } static void mmap_ddr2(struct sysinfo *s) @@ -1605,7 +1624,7 @@ static void mmap_ddr2(struct sysinfo *s) gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; tsegsize = 1; // 1MB TSEG mmiosize = 0x400; // 1GB MMIO - tom = s->channel_capacity[0] + s->channel_capacity[1]; + tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB; tolud = MIN(0x1000 - mmiosize, tom); touud = tom; gfxbase = tolud - gfxsize;

1 0

Patch set updated for coreboot: mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13164 -gerrit commit 8faf3d9ecf11feb59a70373214a8a1df10330ed6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 mainboard/asus/kgpe-d16: Add support for lifted BSP APIC IDs Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/mainboard/asus/kgpe-d16/acpi_tables.c | 19 ++++++++++--------- 1 file changed, 10 insertions(+), 9 deletions(-) diff --git a/src/mainboard/asus/kgpe-d16/acpi_tables.c b/src/mainboard/asus/kgpe-d16/acpi_tables.c index 24c1724..f20e837 100644 --- a/src/mainboard/asus/kgpe-d16/acpi_tables.c +++ b/src/mainboard/asus/kgpe-d16/acpi_tables.c @@ -36,7 +36,10 @@ unsigned long acpi_fill_madt(unsigned long current) /* create all subtables for processors */ current = acpi_create_madt_lapics(current); - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Write SB700 IOAPIC, only one */ @@ -56,15 +59,10 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 0, 2, 0); current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, 0xF); - /* 0: mean bus 0--->ISA */ - /* 0: PIC 0 */ - /* 2: APIC 2 */ - /* 5 mean: 0101 --> Edge-triggered, Active high */ + current, 0, 9, 9, 0xf); /* create all subtables for processors */ - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0, 5, 1); - current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 1, 5, 1); + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 0, 1); /* 1: LINT1 connect to NMI */ return current; @@ -77,7 +75,10 @@ unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t* ivrs, unsigned long current) uint32_t apicid_sp5100; uint32_t apicid_sr5650; - apicid_sp5100 = 0x20; + if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0)) + apicid_sp5100 = 0x0; + else + apicid_sp5100 = 0x20; apicid_sr5650 = apicid_sp5100 + 1; /* Describe NB IOAPIC */

1 0

Patch set updated for coreboot: drivers/pc80: Add PS/2 mouse presence detect
by Timothy Pearson 27 Jan '16

27 Jan '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13165 -gerrit commit af94e4adbeb8835daba281620399d0d1bdea24e7 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Tue Nov 24 14:12:01 2015 -0600 drivers/pc80: Add PS/2 mouse presence detect On certain Winbond SuperIO devices, when a PS/2 mouse is not present on the auxiliary channel both channels will cease to function if the auxiliary channel is probed while the primary channel is active. Therefore, knowledge of mouse presence must be gathered by coreboot during early boot, and used to enable or disable the auxiliary PS/2 port before control is passed to the operating system. Add auxiliary channel PS/2 device presence detect, and update the Winbond W83667HG-A driver to flag the auxiliary channel as disabled if no device was detected. Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/pc80/keyboard.c | 101 +++++++++++++++++----- src/ec/compal/ene932/ec.c | 2 +- src/ec/google/chromeec/ec_lpc.c | 2 +- src/ec/lenovo/h8/h8.c | 2 +- src/ec/quanta/ene_kb3940q/ec.c | 2 +- src/ec/quanta/it8518/ec.c | 2 +- src/include/pc80/keyboard.h | 5 +- src/mainboard/emulation/qemu-i440fx/mainboard.c | 2 +- src/mainboard/emulation/qemu-q35/mainboard.c | 2 +- src/mainboard/packardbell/ms2290/mainboard.c | 2 +- src/mainboard/roda/rk9/mainboard.c | 2 +- src/northbridge/via/cx700/lpc.c | 2 +- src/northbridge/via/vx800/lpc.c | 2 +- src/southbridge/dmp/vortex86ex/southbridge.c | 2 +- src/southbridge/sis/sis966/lpc.c | 2 +- src/southbridge/via/vt8237r/lpc.c | 2 +- src/superio/fintek/f71863fg/superio.c | 2 +- src/superio/fintek/f71869ad/superio.c | 2 +- src/superio/fintek/f71872/superio.c | 2 +- src/superio/fintek/f81865f/superio.c | 2 +- src/superio/fintek/f81866d/superio.c | 2 +- src/superio/ite/it8671f/superio.c | 2 +- src/superio/ite/it8712f/superio.c | 2 +- src/superio/ite/it8716f/superio.c | 2 +- src/superio/ite/it8718f/superio.c | 2 +- src/superio/ite/it8721f/superio.c | 2 +- src/superio/ite/it8728f/superio.c | 2 +- src/superio/ite/it8772f/superio.c | 2 +- src/superio/nsc/pc87309/superio.c | 2 +- src/superio/nsc/pc87360/superio.c | 2 +- src/superio/nsc/pc87366/superio.c | 2 +- src/superio/nsc/pc87417/superio.c | 2 +- src/superio/nsc/pc97317/superio.c | 2 +- src/superio/nuvoton/nct5572d/superio.c | 2 +- src/superio/nuvoton/nct6779d/superio.c | 2 +- src/superio/nuvoton/wpcm450/superio.c | 2 +- src/superio/renesas/m3885x/superio.c | 2 +- src/superio/smsc/dme1737/superio.c | 2 +- src/superio/smsc/fdc37n972/fdc37n972.c | 2 +- src/superio/smsc/kbc1100/superio.c | 2 +- src/superio/smsc/lpc47b272/superio.c | 2 +- src/superio/smsc/lpc47b397/superio.c | 2 +- src/superio/smsc/lpc47m10x/superio.c | 2 +- src/superio/smsc/lpc47m15x/superio.c | 2 +- src/superio/smsc/lpc47n227/superio.c | 2 +- src/superio/smsc/mec1308/superio.c | 2 +- src/superio/smsc/sch4037/superio.c | 2 +- src/superio/smsc/sio10n268/sio10n268.c | 2 +- src/superio/smsc/smscsuperio/superio.c | 2 +- src/superio/winbond/w83627dhg/superio.c | 2 +- src/superio/winbond/w83627ehg/superio.c | 2 +- src/superio/winbond/w83627hf/superio.c | 2 +- src/superio/winbond/w83627thg/superio.c | 2 +- src/superio/winbond/w83627uhg/superio.c | 2 +- src/superio/winbond/w83667hg-a/ps2_controller.asl | 78 +++++++++++++++++ src/superio/winbond/w83667hg-a/superio.c | 20 ++++- src/superio/winbond/w83977tf/superio.c | 2 +- src/superio/winbond/wpcd376i/superio.c | 2 +- 58 files changed, 233 insertions(+), 79 deletions(-) diff --git a/src/drivers/pc80/keyboard.c b/src/drivers/pc80/keyboard.c index 3e61a51..56b1fce 100644 --- a/src/drivers/pc80/keyboard.c +++ b/src/drivers/pc80/keyboard.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2015 Raptor Engineering * Copyright (C) 2009 coresystems GmbH * Copyright (C) 2008 Advanced Micro Devices, Inc. * Copyright (C) 2003 Ollie Lo <ollielo(a)hotmail.com> @@ -32,6 +33,8 @@ // Keyboard Controller Commands #define KBC_CMD_READ_COMMAND 0x20 // Read command byte #define KBC_CMD_WRITE_COMMAND 0x60 // Write command byte +#define KBC_CMD_AUX_ENABLE 0xA8 // Auxiliary Interface enable +#define KBC_CMD_AUX_TEST 0xA9 // Auxiliary Interface test #define KBC_CMD_SELF_TEST 0xAA // Controller self-test #define KBC_CMD_KBD_TEST 0xAB // Keyboard Interface test @@ -106,9 +109,14 @@ static int kbc_cleanup_buffers(void) return !!timeout; } -static enum cb_err kbc_self_test(void) +static enum cb_err kbc_self_test(uint8_t probe_aux, uint8_t *aux_probe_result) { - u8 self_test; + uint8_t self_test; + uint8_t byte; + + /* Set initial aux probe output value */ + if (aux_probe_result) + *aux_probe_result = 0; /* Clean up any junk that might have been in the KBC. * Both input and output buffers must be empty. @@ -154,6 +162,48 @@ static enum cb_err kbc_self_test(void) return CB_KBD_INTERFACE_FAILURE; } + if (probe_aux) { + /* aux interface detect */ + outb(KBC_CMD_AUX_ENABLE, KBD_COMMAND); + if (!kbc_input_buffer_empty()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux enable.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + outb(KBC_CMD_READ_COMMAND, KBD_COMMAND); + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Timeout waiting for controller during aux probe.\n"); + return CB_KBD_CONTROLLER_FAILURE; + } + + byte = inb(KBD_DATA); + if (!(byte & (0x1 << 5))) { + printk(BIOS_DEBUG, "PS/2 auxiliary channel detected...\n"); + + /* auxiliary interface test */ + outb(KBC_CMD_AUX_TEST, KBD_COMMAND); + + if (!kbc_output_buffer_full()) { + printk(BIOS_ERR, "Auxiliary channel probe timed out.\n"); + goto aux_failure; + } + + /* read test result, 0x00 should be returned in case of no failures */ + self_test = inb(KBD_DATA); + + if (self_test != 0x00) { + printk(BIOS_ERR, "No device detected on auxiliary channel: 0x%x\n", + self_test); + goto aux_failure; + } + + printk(BIOS_DEBUG, "PS/2 device detected on auxiliary channel\n"); + if (aux_probe_result) + *aux_probe_result = 1; + } + } + +aux_failure: + return CB_SUCCESS; } @@ -187,53 +237,54 @@ static u8 send_keyboard(u8 command) return regval; } -void pc_keyboard_init(void) +uint8_t pc_keyboard_init(uint8_t probe_aux) { u8 retries; u8 regval; enum cb_err err; + uint8_t aux_dev_detected; if (!CONFIG_DRIVERS_PS2_KEYBOARD) - return; + return 0; if (acpi_is_wakeup_s3()) - return; + return 0; printk(BIOS_DEBUG, "Keyboard init...\n"); /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(probe_aux, &aux_dev_detected); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) - return; + return 0; /* Enable keyboard interface - No IRQ */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x20, KBD_DATA); /* send cmd: enable keyboard */ if (!kbc_input_buffer_empty()) { printk(BIOS_INFO, "Timeout while enabling keyboard\n"); - return; + return 0; } /* clean up any junk that might have been in the keyboard */ if (!kbc_cleanup_buffers()) - return; + return 0; /* reset keyboard and self test (keyboard side) */ regval = send_keyboard(0xFF); if (regval == KBD_REPLY_RESEND) { /* keeps sending RESENDs, probably no keyboard. */ printk(BIOS_INFO, "No PS/2 keyboard detected.\n"); - return; + return 0; } if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard reset failed ACK: 0x%x\n", regval); - return; + return 0; } /* the reset command takes some time, so wait a little longer */ @@ -241,14 +292,14 @@ void pc_keyboard_init(void) if (!kbc_output_buffer_full()) { printk(BIOS_ERR, "Timeout waiting for keyboard after reset.\n"); - return; + return 0; } regval = inb(KBD_DATA); if (regval != 0xAA) { printk(BIOS_ERR, "Keyboard reset selftest failed: 0x%x\n", regval); - return; + return 0; } /* @@ -260,7 +311,7 @@ void pc_keyboard_init(void) regval = send_keyboard(0xF5); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard disable failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode command */ @@ -268,34 +319,38 @@ void pc_keyboard_init(void) if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode cmd failed ACK: 0x%x\n", regval); - return; + return 0; } /* Set scancode mode 2 */ regval = send_keyboard(0x02); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard set scancode mode failed ACK: 0x%x\n", regval); - return; + return 0; } /* All is well - enable keyboard interface */ if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x60, KBD_COMMAND); if (!kbc_input_buffer_empty()) - return; + return 0; outb(0x65, KBD_DATA); /* send cmd: enable keyboard and IRQ 1 */ if (!kbc_input_buffer_empty()) { printk(BIOS_ERR, "Timeout during keyboard enable\n"); - return; + return 0; } /* enable the keyboard */ regval = send_keyboard(0xF4); if (regval != KBD_REPLY_ACK) { printk(BIOS_ERR, "Keyboard enable failed ACK: 0x%x\n", regval); - return; + return 0; } + + printk(BIOS_DEBUG, "PS/2 keyboard initialized on primary channel\n"); + + return aux_dev_detected; } /* @@ -308,7 +363,7 @@ void set_kbc_ps2_mode(void) enum cb_err err; /* Run a keyboard controller self-test */ - err = kbc_self_test(); + err = kbc_self_test(0, NULL); /* Ignore iterface failure as it's non-fatal. */ if (err != CB_SUCCESS && err != CB_KBD_INTERFACE_FAILURE) return; diff --git a/src/ec/compal/ene932/ec.c b/src/ec/compal/ene932/ec.c index d1687e9..c21672e 100644 --- a/src/ec/compal/ene932/ec.c +++ b/src/ec/compal/ene932/ec.c @@ -133,7 +133,7 @@ static void ene932_init(struct device *dev) return; printk(BIOS_DEBUG, "Compal ENE932: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(NO_AUX_DEVICE); } diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 9a16906..8a04135 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -403,7 +403,7 @@ static void lpc_ec_init(struct device *dev) if (!dev->enabled) return; - pc_keyboard_init(); + pc_keyboard_init(0); google_chromeec_init(); } diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 3cd30bc..f0ccd48 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -175,7 +175,7 @@ static void h8_smbios_strings(struct device *dev, struct smbios_type11 *t) static void h8_init(device_t dev) { - pc_keyboard_init(); + pc_keyboard_init(0); } struct device_operations h8_dev_ops = { diff --git a/src/ec/quanta/ene_kb3940q/ec.c b/src/ec/quanta/ene_kb3940q/ec.c index 8f23e33..a7d5bd7 100644 --- a/src/ec/quanta/ene_kb3940q/ec.c +++ b/src/ec/quanta/ene_kb3940q/ec.c @@ -142,7 +142,7 @@ static void ene_kb3940q_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta EnE KB3940Q: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(0); ene_kb3940q_log_events(); } diff --git a/src/ec/quanta/it8518/ec.c b/src/ec/quanta/it8518/ec.c index 7388c01..dd7268a 100644 --- a/src/ec/quanta/it8518/ec.c +++ b/src/ec/quanta/it8518/ec.c @@ -157,7 +157,7 @@ static void it8518_init(struct device *dev) return; printk(BIOS_DEBUG, "Quanta IT8518: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(0); } static struct device_operations ops = { diff --git a/src/include/pc80/keyboard.h b/src/include/pc80/keyboard.h index 16cb959..fa45826 100644 --- a/src/include/pc80/keyboard.h +++ b/src/include/pc80/keyboard.h @@ -1,7 +1,10 @@ #ifndef PC80_KEYBOARD_H #define PC80_KEYBOARD_H -void pc_keyboard_init(void); +#define NO_AUX_DEVICE 0 +#define PROBE_AUX_DEVICE 1 + +uint8_t pc_keyboard_init(uint8_t probe_aux); void set_kbc_ps2_mode(void); #endif /* PC80_KEYBOARD_H */ diff --git a/src/mainboard/emulation/qemu-i440fx/mainboard.c b/src/mainboard/emulation/qemu-i440fx/mainboard.c index b2fb46c..e5fb3cb 100644 --- a/src/mainboard/emulation/qemu-i440fx/mainboard.c +++ b/src/mainboard/emulation/qemu-i440fx/mainboard.c @@ -39,7 +39,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(0); /* setup IRQ routing */ for (i = 0; i < 32; i++) diff --git a/src/mainboard/emulation/qemu-q35/mainboard.c b/src/mainboard/emulation/qemu-q35/mainboard.c index 82716c9..0000564 100644 --- a/src/mainboard/emulation/qemu-q35/mainboard.c +++ b/src/mainboard/emulation/qemu-q35/mainboard.c @@ -60,7 +60,7 @@ static void qemu_nb_init(device_t dev) /* This sneaked in here, because Qemu does not * emulate a SuperIO chip */ - pc_keyboard_init(); + pc_keyboard_init(0); /* setup IRQ routing for pci slots */ for (i = 0; i < 25; i++) diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 065ca94..f964c57 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -121,7 +121,7 @@ static void mainboard_enable(device_t dev) /* This sneaked in here, because EasyNote has no SuperIO chip. */ - pc_keyboard_init(); + pc_keyboard_init(0); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/roda/rk9/mainboard.c b/src/mainboard/roda/rk9/mainboard.c index a5465f9..50e9a75 100644 --- a/src/mainboard/roda/rk9/mainboard.c +++ b/src/mainboard/roda/rk9/mainboard.c @@ -46,7 +46,7 @@ static void mainboard_enable(device_t dev) /* We have no driver for the embedded controller since the firmware does most of the job. Hence, initialize keyboards here. */ - pc_keyboard_init(); + pc_keyboard_init(0); } struct chip_operations mainboard_ops = { diff --git a/src/northbridge/via/cx700/lpc.c b/src/northbridge/via/cx700/lpc.c index 9262e40..e19f638 100644 --- a/src/northbridge/via/cx700/lpc.c +++ b/src/northbridge/via/cx700/lpc.c @@ -285,7 +285,7 @@ static void cx700_lpc_init(struct device *dev) isa_dma_init(); /* Initialize keyboard controller */ - pc_keyboard_init(); + pc_keyboard_init(0); } static struct device_operations cx700_lpc_ops = { diff --git a/src/northbridge/via/vx800/lpc.c b/src/northbridge/via/vx800/lpc.c index 8fbb3be..1bdd7b8 100644 --- a/src/northbridge/via/vx800/lpc.c +++ b/src/northbridge/via/vx800/lpc.c @@ -322,7 +322,7 @@ static void southbridge_init(struct device *dev) setup_i8259(); // make sure interupt controller is configured before keyboard init /* turn on keyboard and RTC, no need to visit this reg twice */ - pc_keyboard_init(); + pc_keyboard_init(0); printk(BIOS_DEBUG, "ps2 usb lid, you set who can wakeup system from s3 sleep\n"); S3_ps2_kb_ms_wakeup(dev); diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c index 3ef6a5d..5da7d74 100644 --- a/src/southbridge/dmp/vortex86ex/southbridge.c +++ b/src/southbridge/dmp/vortex86ex/southbridge.c @@ -607,7 +607,7 @@ static void southbridge_init(struct device *dev) retries--; } post_code(POST_DMP_KBD_IS_READY); - pc_keyboard_init(); + pc_keyboard_init(0); } static struct device_operations vortex_sb_ops = { diff --git a/src/southbridge/sis/sis966/lpc.c b/src/southbridge/sis/sis966/lpc.c index 940844b..c40df0a 100644 --- a/src/southbridge/sis/sis966/lpc.c +++ b/src/southbridge/sis/sis966/lpc.c @@ -91,7 +91,7 @@ static void lpc_init(device_t dev) int nmi_option; printk(BIOS_DEBUG, "LPC_INIT -------->\n"); - pc_keyboard_init(); + pc_keyboard_init(0); lpc_usb_legacy_init(dev); lpc_common_init(dev); diff --git a/src/southbridge/via/vt8237r/lpc.c b/src/southbridge/via/vt8237r/lpc.c index b54d494..113ce93 100644 --- a/src/southbridge/via/vt8237r/lpc.c +++ b/src/southbridge/via/vt8237r/lpc.c @@ -625,7 +625,7 @@ static void init_keyboard(struct device *dev) { u8 regval = pci_read_config8(dev, 0x51); if (regval & 0x1) - pc_keyboard_init(); + pc_keyboard_init(0); } static void southbridge_init_common(struct device *dev) diff --git a/src/superio/fintek/f71863fg/superio.c b/src/superio/fintek/f71863fg/superio.c index 8e0a643..bb09d01 100644 --- a/src/superio/fintek/f71863fg/superio.c +++ b/src/superio/fintek/f71863fg/superio.c @@ -34,7 +34,7 @@ static void f71863fg_init(struct device *dev) /* TODO: Might potentially need code for HWM or FDC etc. */ case F71863FG_KBC: res0 = find_resource(dev, PNP_IDX_IO0); - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index f16c37f..8cf9008 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -34,7 +34,7 @@ static void f71869ad_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71869AD_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; case F71869AD_HWM: f71869ad_multifunc_init(dev); diff --git a/src/superio/fintek/f71872/superio.c b/src/superio/fintek/f71872/superio.c index 6b4de2d..a973da8 100644 --- a/src/superio/fintek/f71872/superio.c +++ b/src/superio/fintek/f71872/superio.c @@ -32,7 +32,7 @@ static void f71872_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F71872_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/fintek/f81865f/superio.c b/src/superio/fintek/f81865f/superio.c index 9cd5c95..fa9e23e 100644 --- a/src/superio/fintek/f81865f/superio.c +++ b/src/superio/fintek/f81865f/superio.c @@ -32,7 +32,7 @@ static void f81865f_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case F81865F_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/fintek/f81866d/superio.c b/src/superio/fintek/f81866d/superio.c index ce0e066..2a95219 100644 --- a/src/superio/fintek/f81866d/superio.c +++ b/src/superio/fintek/f81866d/superio.c @@ -34,7 +34,7 @@ static void f81866d_init(struct device *dev) switch (dev->path.pnp.device) { /* TODO: Might potentially need extra code for serial, wdt etc. */ case F81866D_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; case F81866D_HWM: // Fixing temp sensor read out and init Fan control diff --git a/src/superio/ite/it8671f/superio.c b/src/superio/ite/it8671f/superio.c index 72e31f1..907e020 100644 --- a/src/superio/ite/it8671f/superio.c +++ b/src/superio/ite/it8671f/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) case IT8671F_PP: /* TODO. */ break; case IT8671F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; case IT8671F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8712f/superio.c b/src/superio/ite/it8712f/superio.c index 02cbefc..1d87f47 100644 --- a/src/superio/ite/it8712f/superio.c +++ b/src/superio/ite/it8712f/superio.c @@ -39,7 +39,7 @@ static void it8712f_init(struct device *dev) break; case IT8712F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(0); break; case IT8712F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c index 3a9e790..469c255 100644 --- a/src/superio/ite/it8716f/superio.c +++ b/src/superio/ite/it8716f/superio.c @@ -60,7 +60,7 @@ static void it8716f_init(struct device *dev) init_ec(res0->base + EC_INDEX_PORT); break; case IT8716F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/ite/it8718f/superio.c b/src/superio/ite/it8718f/superio.c index 3f03405..ce10dae 100644 --- a/src/superio/ite/it8718f/superio.c +++ b/src/superio/ite/it8718f/superio.c @@ -34,7 +34,7 @@ static void init(struct device *dev) case IT8718F_EC: /* TODO. */ break; case IT8718F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; case IT8718F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8721f/superio.c b/src/superio/ite/it8721f/superio.c index 4fc0562..ae052a3 100644 --- a/src/superio/ite/it8721f/superio.c +++ b/src/superio/ite/it8721f/superio.c @@ -35,7 +35,7 @@ static void init(struct device *dev) case IT8721F_EC: /* TODO. */ break; case IT8721F_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; case IT8721F_KBCM: /* TODO. */ break; diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c index 4591bb1..3849d63 100644 --- a/src/superio/ite/it8728f/superio.c +++ b/src/superio/ite/it8728f/superio.c @@ -38,7 +38,7 @@ static void it8728f_init(struct device *dev) break; case IT8728F_KBCK: set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/ite/it8772f/superio.c b/src/superio/ite/it8772f/superio.c index 400bbbe..fb1e57a 100644 --- a/src/superio/ite/it8772f/superio.c +++ b/src/superio/ite/it8772f/superio.c @@ -246,7 +246,7 @@ static void it8772f_init(struct device *dev) case IT8772F_KBCK: if (!conf->skip_keyboard) { set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(0); } break; case IT8772F_KBCM: diff --git a/src/superio/nsc/pc87309/superio.c b/src/superio/nsc/pc87309/superio.c index ecda1e7..f22566c 100644 --- a/src/superio/nsc/pc87309/superio.c +++ b/src/superio/nsc/pc87309/superio.c @@ -29,7 +29,7 @@ static void init(struct device *dev) switch (dev->path.pnp.device) { case PC87309_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/nsc/pc87360/superio.c b/src/superio/nsc/pc87360/superio.c index 6b6e790..248c793 100644 --- a/src/superio/nsc/pc87360/superio.c +++ b/src/superio/nsc/pc87360/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87360_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/nsc/pc87366/superio.c b/src/superio/nsc/pc87366/superio.c index f9dca21..e5c8ac2 100644 --- a/src/superio/nsc/pc87366/superio.c +++ b/src/superio/nsc/pc87366/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87366_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/nsc/pc87417/superio.c b/src/superio/nsc/pc87417/superio.c index 1855db9..7a8d76f 100644 --- a/src/superio/nsc/pc87417/superio.c +++ b/src/superio/nsc/pc87417/superio.c @@ -32,7 +32,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case PC87417_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/nsc/pc97317/superio.c b/src/superio/nsc/pc97317/superio.c index e8cf842..983c7f1 100644 --- a/src/superio/nsc/pc97317/superio.c +++ b/src/superio/nsc/pc97317/superio.c @@ -33,7 +33,7 @@ static void init(struct device *dev) pnp_set_enable(dev, 0); /* Disable keyboard */ pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ pnp_set_enable(dev, 1); /* Enable keyboard */ - pc_keyboard_init(); + pc_keyboard_init(0); break; default: break; diff --git a/src/superio/nuvoton/nct5572d/superio.c b/src/superio/nuvoton/nct5572d/superio.c index 81a8326..6b5febd 100644 --- a/src/superio/nuvoton/nct5572d/superio.c +++ b/src/superio/nuvoton/nct5572d/superio.c @@ -45,7 +45,7 @@ static void nct5572d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT5572D_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; case NCT5572D_ACPI: /* Set power state after power fail */ diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 5cc5f54..b6ea5ea 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -35,7 +35,7 @@ static void nct6779d_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case NCT6779D_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/nuvoton/wpcm450/superio.c b/src/superio/nuvoton/wpcm450/superio.c index bfc3c5e..c6cb494 100644 --- a/src/superio/nuvoton/wpcm450/superio.c +++ b/src/superio/nuvoton/wpcm450/superio.c @@ -31,7 +31,7 @@ static void init(struct device *dev) switch(dev->path.pnp.device) { case WPCM450_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/renesas/m3885x/superio.c b/src/superio/renesas/m3885x/superio.c index 1f30bfe..84c014c 100644 --- a/src/superio/renesas/m3885x/superio.c +++ b/src/superio/renesas/m3885x/superio.c @@ -33,7 +33,7 @@ static void m3885x_init(struct device *dev) printk(BIOS_DEBUG, "Renesas M3885x: Initializing keyboard.\n"); set_kbc_ps2_mode(); - pc_keyboard_init(); + pc_keyboard_init(0); m3885_configure_multikey(); } diff --git a/src/superio/smsc/dme1737/superio.c b/src/superio/smsc/dme1737/superio.c index 23f2c7d..0e9bd4c 100644 --- a/src/superio/smsc/dme1737/superio.c +++ b/src/superio/smsc/dme1737/superio.c @@ -35,7 +35,7 @@ static void dme1737_init(struct device *dev) switch(dev->path.pnp.device) { case DME1737_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/fdc37n972/fdc37n972.c b/src/superio/smsc/fdc37n972/fdc37n972.c index 0c6b517..cf94912 100644 --- a/src/superio/smsc/fdc37n972/fdc37n972.c +++ b/src/superio/smsc/fdc37n972/fdc37n972.c @@ -31,7 +31,7 @@ static void init(struct device *dev) case FDC37N972_PP: /* TODO. */ break; case FDC37N972_KBDC: - pc_keyboard_init(); + pc_keyboard_init(0); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/kbc1100/superio.c b/src/superio/smsc/kbc1100/superio.c index 81fb394..687691c 100644 --- a/src/superio/smsc/kbc1100/superio.c +++ b/src/superio/smsc/kbc1100/superio.c @@ -68,7 +68,7 @@ static void kbc1100_init(struct device *dev) case KBC1100_KBC: res0 = find_resource(dev, PNP_IDX_IO0); res1 = find_resource(dev, PNP_IDX_IO1); - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/lpc47b272/superio.c b/src/superio/smsc/lpc47b272/superio.c index 6cc4823..e8d4741 100644 --- a/src/superio/smsc/lpc47b272/superio.c +++ b/src/superio/smsc/lpc47b272/superio.c @@ -46,7 +46,7 @@ static void lpc47b272_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B272_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/lpc47b397/superio.c b/src/superio/smsc/lpc47b397/superio.c index 6270d92..76164b5 100644 --- a/src/superio/smsc/lpc47b397/superio.c +++ b/src/superio/smsc/lpc47b397/superio.c @@ -45,7 +45,7 @@ static void lpc47b397_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47B397_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/lpc47m10x/superio.c b/src/superio/smsc/lpc47m10x/superio.c index c3c7feb..bcde524 100644 --- a/src/superio/smsc/lpc47m10x/superio.c +++ b/src/superio/smsc/lpc47m10x/superio.c @@ -44,7 +44,7 @@ static void lpc47m10x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M10X2_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/lpc47m15x/superio.c b/src/superio/smsc/lpc47m15x/superio.c index 166f383..6736621 100644 --- a/src/superio/smsc/lpc47m15x/superio.c +++ b/src/superio/smsc/lpc47m15x/superio.c @@ -66,7 +66,7 @@ static void lpc47m15x_init(struct device *dev) switch(dev->path.pnp.device) { case LPC47M15X_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/lpc47n227/superio.c b/src/superio/smsc/lpc47n227/superio.c index 3885ef32..a5e33fa 100644 --- a/src/superio/smsc/lpc47n227/superio.c +++ b/src/superio/smsc/lpc47n227/superio.c @@ -131,7 +131,7 @@ static void lpc47n227_init(struct device *dev) switch (dev->path.pnp.device) { case LPC47N227_KBDC: printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n"); - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/mec1308/superio.c b/src/superio/smsc/mec1308/superio.c index 2beeec6..aa3d012 100644 --- a/src/superio/smsc/mec1308/superio.c +++ b/src/superio/smsc/mec1308/superio.c @@ -34,7 +34,7 @@ static void mec1308_init(struct device *dev) switch(dev->path.pnp.device) { case MEC1308_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/sch4037/superio.c b/src/superio/smsc/sch4037/superio.c index 0f09914..4906aa2 100644 --- a/src/superio/smsc/sch4037/superio.c +++ b/src/superio/smsc/sch4037/superio.c @@ -33,7 +33,7 @@ static void sch4037_init(struct device *dev) switch(dev->path.pnp.device) { case SCH4037_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/sio10n268.c index 5892f0c..e0b0d99 100644 --- a/src/superio/smsc/sio10n268/sio10n268.c +++ b/src/superio/smsc/sio10n268/sio10n268.c @@ -31,7 +31,7 @@ static void init(struct device *dev) break; case SIO10N268_KBDC: /* TODO: This is still hardcoded. */ - pc_keyboard_init(); + pc_keyboard_init(0); break; // [..] The rest: TODO } diff --git a/src/superio/smsc/smscsuperio/superio.c b/src/superio/smsc/smscsuperio/superio.c index b3238de..fec8157 100644 --- a/src/superio/smsc/smscsuperio/superio.c +++ b/src/superio/smsc/smscsuperio/superio.c @@ -163,7 +163,7 @@ static void smsc_init(struct device *dev) /* A Super I/O was found, so initialize the respective device. */ ld = dev->path.pnp.device; if (ld == logical_device_table[i].devs[LD_KBC]) { - pc_keyboard_init(); + pc_keyboard_init(0); } } diff --git a/src/superio/winbond/w83627dhg/superio.c b/src/superio/winbond/w83627dhg/superio.c index 10dba59..ddda25e 100644 --- a/src/superio/winbond/w83627dhg/superio.c +++ b/src/superio/winbond/w83627dhg/superio.c @@ -43,7 +43,7 @@ static void w83627dhg_init(struct device *dev) w83627dhg_enable_UR2(dev); break; case W83627DHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/winbond/w83627ehg/superio.c b/src/superio/winbond/w83627ehg/superio.c index ea7a982..1060059 100644 --- a/src/superio/winbond/w83627ehg/superio.c +++ b/src/superio/winbond/w83627ehg/superio.c @@ -85,7 +85,7 @@ static void w83627ehg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627EHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; case W83627EHG_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627hf/superio.c b/src/superio/winbond/w83627hf/superio.c index fe250a1..2402ae0 100644 --- a/src/superio/winbond/w83627hf/superio.c +++ b/src/superio/winbond/w83627hf/superio.c @@ -92,7 +92,7 @@ static void w83627hf_init(struct device *dev) switch(dev->path.pnp.device) { case W83627HF_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; case W83627HF_HWM: res0 = find_resource(dev, PNP_IDX_IO0); diff --git a/src/superio/winbond/w83627thg/superio.c b/src/superio/winbond/w83627thg/superio.c index f42f948..da9bab2 100644 --- a/src/superio/winbond/w83627thg/superio.c +++ b/src/superio/winbond/w83627thg/superio.c @@ -33,7 +33,7 @@ static void w83627thg_init(struct device *dev) switch(dev->path.pnp.device) { case W83627THG_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/winbond/w83627uhg/superio.c b/src/superio/winbond/w83627uhg/superio.c index 5192c32..d0e443c 100644 --- a/src/superio/winbond/w83627uhg/superio.c +++ b/src/superio/winbond/w83627uhg/superio.c @@ -79,7 +79,7 @@ static void w83627uhg_init(struct device *dev) set_uart_clock_source(dev, 0); break; case W83627UHG_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/winbond/w83667hg-a/ps2_controller.asl b/src/superio/winbond/w83667hg-a/ps2_controller.asl new file mode 100644 index 0000000..c3b5c75 --- /dev/null +++ b/src/superio/winbond/w83667hg-a/ps2_controller.asl @@ -0,0 +1,78 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2013 Vladimir Serbinenko + * Copyright (c) 2015 Raptor Engineering + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* SuperIO control port */ + Name (SPIO, 0x2E) + + /* SuperIO control map */ + OperationRegion (SPIM, SystemIO, SPIO, 0x02) + Field (SPIM, ByteAcc, NoLock, Preserve) { + SIOI, 8, + SIOD, 8 + } + + /* SuperIO control registers */ + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) { + Offset (0x2A), + CR2A, 8, /* Pin function selection */ + } + + Device (PS2K) // Keyboard + { + Name(_HID, EISAID("PNP0303")) + Name(_CID, EISAID("PNP030B")) + + Name(_CRS, ResourceTemplate() + { + IO (Decode16, 0x60, 0x60, 0x01, 0x01) + IO (Decode16, 0x64, 0x64, 0x01, 0x01) + IRQ (Edge, ActiveHigh, Exclusive) { 0x01 } // IRQ 1 + }) + + Method (_STA, 0) + { + Return (0xf) + } + } + + Device (PS2M) // Mouse + { + Name(_HID, EISAID("PNP0F13")) + Name(_CRS, ResourceTemplate() + { + IRQ (Edge, ActiveHigh, Exclusive) { 0x0c } // IRQ 12 + }) + + Method(_STA, 0) + { + /* Access SuperIO ACPI device */ + Store(0x87, SIOI) + Store(0x87, SIOI) + + /* Read Pin56 function select */ + And(CR2A, 0x2, Local0) + + /* Restore default SuperIO access */ + Store(0xAA, SIOI) + + if (LEqual(Local0, 0x0)) { + /* Mouse function selected */ + Return (0xf) + } + Return (0x0) + } + } diff --git a/src/superio/winbond/w83667hg-a/superio.c b/src/superio/winbond/w83667hg-a/superio.c index 96eddd7..70e3cd0 100644 --- a/src/superio/winbond/w83667hg-a/superio.c +++ b/src/superio/winbond/w83667hg-a/superio.c @@ -23,6 +23,7 @@ #include <pc80/keyboard.h> #include <pc80/mc146818rtc.h> #include <stdlib.h> +#include <arch/acpi.h> #include <superio/conf_mode.h> #include "w83667hg-a.h" @@ -38,6 +39,7 @@ static void w83667hg_a_init(struct device *dev) { uint8_t byte; uint8_t power_status; + uint8_t mouse_detected; if (!dev->enabled) return; @@ -45,7 +47,23 @@ static void w83667hg_a_init(struct device *dev) switch(dev->path.pnp.device) { /* TODO: Might potentially need code for HWM or FDC etc. */ case W83667HG_A_KBC: - pc_keyboard_init(); + /* Enable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte &= ~(0x1 << 1); + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + + mouse_detected = pc_keyboard_init(1); + + if (!mouse_detected && !acpi_is_wakeup_s3()) { + /* Disable mouse controller */ + pnp_enter_conf_mode_8787(dev); + byte = pnp_read_config(dev, 0x2a); + byte |= 0x1 << 1; + pnp_write_config(dev, 0x2a, byte); + pnp_exit_conf_mode_aa(dev); + } break; case W83667HG_A_ACPI: /* Set power state after power fail */ diff --git a/src/superio/winbond/w83977tf/superio.c b/src/superio/winbond/w83977tf/superio.c index f23d7c4..b4fe594 100644 --- a/src/superio/winbond/w83977tf/superio.c +++ b/src/superio/winbond/w83977tf/superio.c @@ -34,7 +34,7 @@ static void w83977tf_init(struct device *dev) switch(dev->path.pnp.device) { case W83977TF_KBC: - pc_keyboard_init(); + pc_keyboard_init(0); break; } } diff --git a/src/superio/winbond/wpcd376i/superio.c b/src/superio/winbond/wpcd376i/superio.c index c455340..3dfb44d 100644 --- a/src/superio/winbond/wpcd376i/superio.c +++ b/src/superio/winbond/wpcd376i/superio.c @@ -41,7 +41,7 @@ static void init(device_t dev) break; case WPCD376I_KBCK: - pc_keyboard_init(); + pc_keyboard_init(0); break; } }

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coreboot-gerrit January 2016