coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: drivers/intel/fsp1_1: Remove extra include references
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13436 -gerrit commit 346691d5b10abcede2dec3e28cfd37770b4d24f2 Author: Lee Leahy <lpleahyjr(a)gmail.com> Date: Fri Jan 1 18:09:50 2016 -0800 drivers/intel/fsp1_1: Remove extra include references Remove include references to the soc include directory which are not required to build the FSP driver. Remove "duplicate" include file definitions from file that include fsp/romstage.h. Move the definition of fill_power_state into soc/pm.h to ensure it is still available. TEST=Build and run on Galileo Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/raminit.c | 5 ++--- src/drivers/intel/fsp1_1/romstage.c | 12 ++---------- src/drivers/intel/fsp1_1/stack.c | 1 - src/soc/intel/braswell/include/soc/pm.h | 2 ++ src/soc/intel/braswell/include/soc/romstage.h | 1 - src/soc/intel/skylake/include/soc/pm.h | 2 ++ src/soc/intel/skylake/include/soc/romstage.h | 2 -- 7 files changed, 8 insertions(+), 17 deletions(-) diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index 2ba77e3..e505b93 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014-2015 Intel Corporation + * Copyright (C) 2014-2016 Intel Corporation * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -16,12 +16,11 @@ #include <cbmem.h> #include <console/console.h> #include <fsp/memmap.h> +#include <fsp/romstage.h> #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> #include <soc/intel/common/mma.h> -#include <soc/pei_data.h> -#include <soc/romstage.h> #include <string.h> #include <timestamp.h> #include <bootmode.h> diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..4402f9d 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,8 +15,6 @@ */ #include <stddef.h> -#include <stdint.h> -#include <arch/cpu.h> #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> @@ -28,17 +26,11 @@ #include <ec/google/chromeec/ec.h> #include <ec/google/chromeec/ec_commands.h> #include <elog.h> -#include <fsp/util.h> -#include <memory_info.h> +#include <fsp/romstage.h> #include <reset.h> #include <romstage_handoff.h> #include <smbios.h> #include <soc/intel/common/mrc_cache.h> -#include <soc/intel/common/util.h> -#include <soc/pei_wrapper.h> -#include <soc/pm.h> -#include <soc/romstage.h> -#include <soc/spi.h> #include <stage_cache.h> #include <timestamp.h> #include <tpm.h> diff --git a/src/drivers/intel/fsp1_1/stack.c b/src/drivers/intel/fsp1_1/stack.c index e5fd9a9..6444ab8 100644 --- a/src/drivers/intel/fsp1_1/stack.c +++ b/src/drivers/intel/fsp1_1/stack.c @@ -20,7 +20,6 @@ #include <fsp/memmap.h> #include <fsp/romstage.h> #include <fsp/stack.h> -#include <soc/intel/common/util.h> #include <stdlib.h> const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..79a6592 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -235,6 +235,8 @@ struct chipset_power_state { int prev_sleep_state; } __attribute__((packed)); +struct chipset_power_state *fill_power_state(void); + /* Power Management Utility Functions. */ uint16_t get_pmbase(void); uint32_t clear_smi_status(void); diff --git a/src/soc/intel/braswell/include/soc/romstage.h b/src/soc/intel/braswell/include/soc/romstage.h index e70510b..262797d 100644 --- a/src/soc/intel/braswell/include/soc/romstage.h +++ b/src/soc/intel/braswell/include/soc/romstage.h @@ -33,7 +33,6 @@ void set_max_freq(void); /* romstage_common.c functions */ void program_base_addresses(void); -struct chipset_power_state *fill_power_state(void); int chipset_prev_sleep_state(struct chipset_power_state *ps); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/skylake/include/soc/pm.h b/src/soc/intel/skylake/include/soc/pm.h index 79861e9..31cf7b4 100644 --- a/src/soc/intel/skylake/include/soc/pm.h +++ b/src/soc/intel/skylake/include/soc/pm.h @@ -159,6 +159,8 @@ struct chipset_power_state { uint32_t prev_sleep_state; } __attribute__ ((packed)); +struct chipset_power_state *fill_power_state(void); + /* PM1_CNT */ void enable_pm1_control(uint32_t mask); void disable_pm1_control(uint32_t mask); diff --git a/src/soc/intel/skylake/include/soc/romstage.h b/src/soc/intel/skylake/include/soc/romstage.h index 5e73e1c..e65bce2 100644 --- a/src/soc/intel/skylake/include/soc/romstage.h +++ b/src/soc/intel/skylake/include/soc/romstage.h @@ -19,8 +19,6 @@ #include <fsp/romstage.h> -struct chipset_power_state; -struct chipset_power_state *fill_power_state(void); void systemagent_early_init(void); void pch_early_init(void); void pch_uart_init(void);

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Patch set updated for coreboot: Provide a gcc-safe zero pointer
by Patrick Georgi 27 Jan '16

27 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12294 -gerrit commit 3fa01f5b580765392ca019d14fadae1e53eaa413 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:18:16 2016 +0100 Provide a gcc-safe zero pointer zeroptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/stddef.h | 8 ++++++++ src/lib/program.ld | 4 ++++ 2 files changed, 12 insertions(+) diff --git a/src/include/stddef.h b/src/include/stddef.h index b58f645..35326ed 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -34,4 +34,12 @@ typedef unsigned int wint_t; #define MAYBE_STATIC static #endif +#ifndef __ROMCC__ +/* Provide a pointer to address 0 that thwarts any "accessing this is + * undefined behaviour and do whatever" trickery in compilers. + * Use when you _really_ need to read32(zeroptr) (ie. read address 0). + */ +extern void *zeroptr; +#endif + #endif /* STDDEF_H */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 865b5f6..9b8c7c9 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -133,6 +133,10 @@ _eprogram = .; /* Discard the sections we don't need/want */ +.zeroptr 0 (NOLOAD) : { + zeroptr = .; +} + /DISCARD/ : { *(.comment) *(.comment.*)

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Patch set updated for coreboot: via/cx700: Use nullptr over 0
by Patrick Georgi 27 Jan '16

27 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13488 -gerrit commit 1aa8bd47625d25c5dcc77866a3e1e36316e43ed5 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:19:36 2016 +0100 via/cx700: Use nullptr over 0 This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/via/cx700/raminit.c | 84 ++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 249f265..2016a87 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -989,7 +989,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 4 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); // Step 5 @@ -1001,7 +1001,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 7 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); /* Step 8. Mode register set. */ @@ -1029,7 +1029,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 12 printk(BIOS_SPEW, "SEND: "); - read32((u32 *)0x0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); /* Step 13. Perform 8 refresh cycles. Wait tRC each time. */ @@ -1040,7 +1040,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 16: Repeat Step 14 and 15 another 7 times for (i = 0; i < 8; i++) { // Step 14 - read32((u32 *)0); + read32(zeroptr); printk(BIOS_SPEW, "."); // Step 15 @@ -1127,45 +1127,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num) u8 ca, ra, ba, reg; ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS); if (ba == 8) { - write8((void *)0, 0x0d); - ra = read8((void *)0); + write8(zeroptr, 0x0d); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c); - ra = read8((void *)0); + ra = read8(zeroptr); - write8((void *)0, 0x0a); - ca = read8((void *)0); + write8(zeroptr, 0x0a); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c); - ca = read8((void *)0); + ca = read8(zeroptr); - write8((void *)0, 0x03); - ba = read8((void *)0); + write8(zeroptr, 0x03); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - ba = read8((void *)0); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - ba = read8((void *)0); + ba = read8(zeroptr); } else { - write8((void *)0, 0x0f); - ra = read8((void *)0); + write8(zeroptr, 0x0f); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_14), 0x0e); - ra = read8((void *)0); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_13), 0x0d); - ra = read8((void *)0); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_12), 0x0c); - ra = read8((void *)0); + ra = read8(zeroptr); - write8((void *)0, 0x0c); - ca = read8((void *)0); + write8(zeroptr, 0x0c); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_12), 0x0b); - ca = read8((void *)0); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_11), 0x0a); - ca = read8((void *)0); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_09), 0x09); - ca = read8((void *)0); + ca = read8(zeroptr); - write8((void *)0, 0x02); - ba = read8((void *)0); + write8(zeroptr, 0x02); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - ba = read8((void *)0); + ba = read8(zeroptr); } if (ra < 10 || ra > 15) @@ -1271,17 +1271,17 @@ static void sdram_enable(const struct mem_controller *ctrl) if (reg8) { sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(zeroptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(zeroptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(zeroptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(zeroptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1304,17 +1304,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(zeroptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(zeroptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(zeroptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(zeroptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1358,17 +1358,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); if (reg8 == 4) { - write8((void *)0, 0x02); - val = read8((void *)0); + write8(zeroptr, 0x02); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - val = read8((void *)0); + val = read8(zeroptr); } else { - write8((void *)0, 0x03); - val = read8((void *)0); + write8(zeroptr, 0x03); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - val = read8((void *)0); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - val = read8((void *)0); + val = read8(zeroptr); } if (val < dl) dl = val;

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Patch merged into coreboot/master: intel/sklrvp: Remove mainboard
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit 4b7a00867aba15f71679d406d140014a03d8e7a0 Author: Martin Roth <martinroth(a)google.com> Date: Tue Jan 26 09:25:09 2016 -0700 intel/sklrvp: Remove mainboard The Intel Skylake RVP3 mainboard is not building, and according to Intel, there is no plan to continue working on it for coreboot. The intel/kunimitsu board is the Skylake reference design for coreboot.org. Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13469 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> See https://review.coreboot.org/13469 for details. -gerrit

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Patch merged into coreboot/master: ectool: fix NetBSD compilation
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit 393d9322ba51feeea33cd08f77945f593cb70e32 Author: Andrey Korolyov <andrey(a)xdel.ru> Date: Tue Jan 5 14:27:59 2016 +0300 ectool: fix NetBSD compilation Since NetBSD does not support uname -o, push check for CygWin inside separate non-failing condition in Makefile. Change-Id: Ibd264384f49b33412f0ef8554bd9c9fb8f60a892 Signed-off-by: Andrey Korolyov <andrey(a)xdel.ru> Reviewed-on: https://review.coreboot.org/12831 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/12831 for details. -gerrit

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Patch merged into coreboot/master: chromeos: vpd: Avoid reading uninitialized VPDs
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit ffc2260d749a1774a79805ec51bcb67021c07c28 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Jan 21 11:12:38 2016 -0800 chromeos: vpd: Avoid reading uninitialized VPDs This patch adds a check to the VPD parsing code to avoid reading the whole thing if the first byte ('type' of the first VPD entry) is 0x00 or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types which should never occur as the first entry, so this usually means that the VPD FMAP section has simply never been initialized correctly. This early abort avoids wasting time to read the whole section from SPI flash (which we'd otherwise have to since we're not going to find a Google VPD 2.0 header either). BRANCH=None BUG=None TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to 1.5ms. Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720 Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322897 Original-Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-on: https://review.coreboot.org/13467 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13467 for details. -gerrit

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Patch merged into coreboot/master: chromeos: Add timestamps to measure VPD read times
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit 4f7a3614cd07acdb6855c32eea38e5585834ee24 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Jan 20 18:01:15 2016 -0800 chromeos: Add timestamps to measure VPD read times This patch adds three timestamps to coreboot and the cbmem utility that track the time required to read in the Chrome OS Vital Product Data (VPD) blocks (RO and RW). It's useful to account for these like all other large flash accesses, since their size is variable. BRANCH=None BUG=None TEST=Booted Oak, found my weird 100ms gap at the start of ramstage properly accounted for. Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234 Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/322831 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: https://review.coreboot.org/13139 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13139 for details. -gerrit

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New patch to review for coreboot: cbfstool: Add compression attribute to ramstage
by Werner Zeh 27 Jan '16

27 Jan '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13489 -gerrit commit 9e788837a042580f8c206f457bc9a44cafbc97e5 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Jan 27 08:19:47 2016 +0100 cbfstool: Add compression attribute to ramstage Currently, compression attribute is added to every cbfs file but ramstage. This patch adds compression attribute for ramstage, too. Change-Id: If66a9d3129740fcd5e703b9f3035a31431afb851 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- util/cbfstool/cbfs-mkstage.c | 3 +++ util/cbfstool/cbfstool.c | 20 +++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs-mkstage.c b/util/cbfstool/cbfs-mkstage.c index 9d88658..2a2d062 100644 --- a/util/cbfstool/cbfs-mkstage.c +++ b/util/cbfstool/cbfs-mkstage.c @@ -5,6 +5,7 @@ * 2009 coresystems GmbH * written by Patrick Georgi <patrick.georgi(a)coresystems.de> * Copyright (C) 2012 Google, Inc. + * Copyright (C) 2016 Siemens AG. All rights reserved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -285,6 +286,8 @@ int parse_elf_to_stage(const struct buffer *input, struct buffer *output, *location -= sizeof(struct cbfs_stage); output->size = sizeof(struct cbfs_stage) + outlen; ret = 0; + if (algo == CBFS_COMPRESS_NONE) + ret = 1; err: parsed_elf_destroy(&pelf); diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 23787d8..c0a4b32 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -504,12 +504,30 @@ static int cbfstool_convert_mkstage(struct buffer *buffer, uint32_t *offset, ret = parse_elf_to_xip_stage(buffer, &output, offset, param.ignore_section); - } else + } else { ret = parse_elf_to_stage(buffer, &output, param.compression, offset, param.ignore_section); + /* Add compression header. Compression was disabled in */ + /* parse_elf_to_stage() when ret == 1, take it into account */ + if (ret == 1) + param.compression = CBFS_COMPRESS_NONE; + struct cbfs_file_attr_compression *attrs = + (struct cbfs_file_attr_compression *) + cbfs_add_file_attr(header, + CBFS_FILE_ATTR_TAG_COMPRESSION, + sizeof(struct cbfs_file_attr_compression)); + if (attrs == NULL) + ret = -1; + else { + attrs->compression = htonl(param.compression); + attrs->decompressed_size = htonl(buffer->size); + ret = 0; + } + } if (ret != 0) return -1; + buffer_delete(buffer); // direct assign, no dupe. memcpy(buffer, &output, sizeof(*buffer));

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New patch to review for coreboot: via/cx700: Use nullptr over 0
by Patrick Georgi 27 Jan '16

27 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13488 -gerrit commit cb3f798fe2ebfba80a65f246b95fbc0d9b721ac8 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:19:36 2016 +0100 via/cx700: Use nullptr over 0 This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/via/cx700/raminit.c | 84 ++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 249f265..4c2c580 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -989,7 +989,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 4 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(nullptr); printk(BIOS_SPEW, "OK\n"); // Step 5 @@ -1001,7 +1001,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 7 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(nullptr); printk(BIOS_SPEW, "OK\n"); /* Step 8. Mode register set. */ @@ -1029,7 +1029,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 12 printk(BIOS_SPEW, "SEND: "); - read32((u32 *)0x0); + read32(nullptr); printk(BIOS_SPEW, "OK\n"); /* Step 13. Perform 8 refresh cycles. Wait tRC each time. */ @@ -1040,7 +1040,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 16: Repeat Step 14 and 15 another 7 times for (i = 0; i < 8; i++) { // Step 14 - read32((u32 *)0); + read32(nullptr); printk(BIOS_SPEW, "."); // Step 15 @@ -1127,45 +1127,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num) u8 ca, ra, ba, reg; ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS); if (ba == 8) { - write8((void *)0, 0x0d); - ra = read8((void *)0); + write8(nullptr, 0x0d); + ra = read8(nullptr); write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c); - ra = read8((void *)0); + ra = read8(nullptr); - write8((void *)0, 0x0a); - ca = read8((void *)0); + write8(nullptr, 0x0a); + ca = read8(nullptr); write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c); - ca = read8((void *)0); + ca = read8(nullptr); - write8((void *)0, 0x03); - ba = read8((void *)0); + write8(nullptr, 0x03); + ba = read8(nullptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - ba = read8((void *)0); + ba = read8(nullptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - ba = read8((void *)0); + ba = read8(nullptr); } else { - write8((void *)0, 0x0f); - ra = read8((void *)0); + write8(nullptr, 0x0f); + ra = read8(nullptr); write8((void *)(1 << SDRAM1X_RA_14), 0x0e); - ra = read8((void *)0); + ra = read8(nullptr); write8((void *)(1 << SDRAM1X_RA_13), 0x0d); - ra = read8((void *)0); + ra = read8(nullptr); write8((void *)(1 << SDRAM1X_RA_12), 0x0c); - ra = read8((void *)0); + ra = read8(nullptr); - write8((void *)0, 0x0c); - ca = read8((void *)0); + write8(nullptr, 0x0c); + ca = read8(nullptr); write8((void *)(1 << SDRAM1X_CA_12), 0x0b); - ca = read8((void *)0); + ca = read8(nullptr); write8((void *)(1 << SDRAM1X_CA_11), 0x0a); - ca = read8((void *)0); + ca = read8(nullptr); write8((void *)(1 << SDRAM1X_CA_09), 0x09); - ca = read8((void *)0); + ca = read8(nullptr); - write8((void *)0, 0x02); - ba = read8((void *)0); + write8(nullptr, 0x02); + ba = read8(nullptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - ba = read8((void *)0); + ba = read8(nullptr); } if (ra < 10 || ra > 15) @@ -1271,17 +1271,17 @@ static void sdram_enable(const struct mem_controller *ctrl) if (reg8) { sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(nullptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(nullptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(nullptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(nullptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1304,17 +1304,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(nullptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(nullptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(nullptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(nullptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1358,17 +1358,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); if (reg8 == 4) { - write8((void *)0, 0x02); - val = read8((void *)0); + write8(nullptr, 0x02); + val = read8(nullptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - val = read8((void *)0); + val = read8(nullptr); } else { - write8((void *)0, 0x03); - val = read8((void *)0); + write8(nullptr, 0x03); + val = read8(nullptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - val = read8((void *)0); + val = read8(nullptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - val = read8((void *)0); + val = read8(nullptr); } if (val < dl) dl = val;

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Patch set updated for coreboot: Provide a gcc-safe null pointer
by Patrick Georgi 27 Jan '16

27 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12294 -gerrit commit d2bf503f8cea28b95ce4fcd4dead9b69b2196ac1 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:18:16 2016 +0100 Provide a gcc-safe null pointer nullptr is a linker object pointing at 0 that can be used to thwart GCC's (and other compilers') "dereferencing NULL is undefined" optimization strategy when it gets in the way. Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/include/stddef.h | 4 ++++ src/lib/program.ld | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/include/stddef.h b/src/include/stddef.h index b58f645..4fe4e05 100644 --- a/src/include/stddef.h +++ b/src/include/stddef.h @@ -34,4 +34,8 @@ typedef unsigned int wint_t; #define MAYBE_STATIC static #endif +#ifndef __ROMCC__ +extern void *nullptr; +#endif + #endif /* STDDEF_H */ diff --git a/src/lib/program.ld b/src/lib/program.ld index 865b5f6..0a966ad 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -133,6 +133,10 @@ _eprogram = .; /* Discard the sections we don't need/want */ +.nullptr 0 (NOLOAD) : { + nullptr = .; +} + /DISCARD/ : { *(.comment) *(.comment.*)

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coreboot-gerrit January 2016