coreboot-gerrit January 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: intel/strago: Fix GPIO config
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit d4b26b29233beea162dd2756cd89bf015411ed08 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:25:23 2016 -0800 intel/strago: Fix GPIO config Fix GPIO config for this board: - SD card detect to GPI - SATA GPI to not used - GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination - I2C4 SDA and SCL from not used to Native Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13431 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13431 for details. -gerrit

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Patch merged into coreboot/master: soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit b11591064bbb395400075c4a4e159cd65a78bce6 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 18 00:22:52 2016 -0800 soc/braswell: Update FspUpdVpd.h for PcdSdDetectChk and PcdCaMirrorEn Change-Id: I42200feafed613136f23e37d4ab4c90931698821 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/13038 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13038 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Rewrite assembly files in ATT syntax
by Alexandru Gagniuc 27 Jan '16

27 Jan '16

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13492 -gerrit commit 459032c984204fbd7ade71483e1fb4b411d7cc65 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed Jan 27 10:06:18 2016 -0800 soc/apollolake: Rewrite assembly files in ATT syntax When we stared development internally, both intel and att syntaxes were accepted. Since our hardware debuggers only work with intel syntax, it proved much more productive with regards to development and debugging time to use intel syntax in the code. Recently, the coreboot leadership has updated the guidelines to converge on att syntax. Rewrite all appololake assembly files to be compliant with this new guideline. Change-Id: Ief78cba4a771fc6549ee204f5df81bc93245a4a1 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/bootblock/cache_as_ram.S | 85 ++++++++++------------ .../apollolake/bootblock/early_chipset_config.S | 44 +++++------ src/soc/intel/apollolake/romstage/entry.inc | 5 +- 3 files changed, 61 insertions(+), 73 deletions(-) diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index 6ecfa86..1713877 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -21,101 +21,96 @@ #define EVICT_CTL_MSR 0x2e0 -.intel_syntax noprefix - -#undef post_code -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al .global cache_as_ram cache_as_ram: post_code(0x21) /* Clear/disable fixed MTRRs */ - mov ebx, offset fixed_mtrr_list_size - xor eax, eax - xor edx, edx + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx clear_fixed_mtrr: - add ebx, -2 - movzxw ecx, word ptr [fixed_mtrr_list + ebx] + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx wrmsr jnz clear_fixed_mtrr post_code(0x22) /* Figure put how many MTRRs we have, and clear them out */ - mov ecx, MTRR_CAP_MSR + mov $MTRR_CAP_MSR, %ecx rdmsr - movzxb ebx, al /* Number of variable MTRRs */ - mov ecx, MTRR_PHYS_BASE(0) - xor eax, eax - xor edx, edx + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + clear_var_mtrr: wrmsr - inc ecx + inc %ecx wrmsr - inc ecx - dec ebx + inc %ecx + dec %ebx jnz clear_var_mtrr post_code(0x23) /* Configure default memory type to uncacheable (UC) */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - and eax, ~0xcff + and $~0xcff, %eax wrmsr post_code(0x24) /* Configure CAR region as write-back (WB) */ - mov ecx, MTRR_PHYS_BASE(0) - mov eax, CONFIG_DCACHE_RAM_BASE /* base */ - or eax, MTRR_TYPE_WRBACK - xor edx, edx + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx wrmsr /* Configure the MTRR mask for the size region */ - mov ecx, MTRR_PHYS_MASK(0) - mov eax, ~(CONFIG_DCACHE_RAM_SIZE - 1) /* size mask */ - or eax, MTRR_PHYS_MASK_VALID + mov $MTRR_PHYS_MASK(0), %ecx + mov $~(CONFIG_DCACHE_RAM_SIZE - 1), %eax /* size mask */ + or $0x800, %eax wrmsr post_code(0x25) /* Enable variable MTRRs */ - mov ecx, MTRR_DEF_TYPE_MSR + mov $MTRR_DEF_TYPE_MSR, %ecx rdmsr - or eax, MTRR_DEF_TYPE_EN + or $MTRR_DEF_TYPE_EN, %eax wrmsr /* Cache tricks */ - mov eax, cr0 - and eax, ~(CR0_CACHE_DISABLE | CR0_NO_WRITE) + mov %cr0, %eax + and $~(CR0_CACHE_DISABLE | CR0_NO_WRITE), %eax invd - mov cr0, eax + mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 1 + or $0x1, %eax wrmsr post_code(0x26) /* Clear the cache memory region. This will also fill up the cache */ - mov edi, CONFIG_DCACHE_RAM_BASE - mov ecx, CONFIG_DCACHE_RAM_SIZE >> 2 - xor eax, eax - rep stos dword ptr es:[edi], eax + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) post_code(0x27) /* Disable cache eviction (run stage) */ - mov ecx, EVICT_CTL_MSR + mov $EVICT_CTL_MSR, %ecx rdmsr - or eax, 2 + or $0x2, %eax wrmsr post_code(0x28) @@ -123,13 +118,13 @@ clear_var_mtrr: car_init_done: /* Setup bootblock stack */ - mov esp, CONFIG_DCACHE_RAM_BASE - add esp, CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE + mov $CONFIG_DCACHE_RAM_BASE, %esp + add $CONFIG_DCACHE_RAM_BOOTBLOCK_STACK_SIZE, %esp /* Make sure CAR region is executable */ - mov ecx, 0x120 + mov $0x120, %ecx rdmsr - or ah, 0x1 + or $0x1, %ah wrmsr before_carstage: diff --git a/src/soc/intel/apollolake/bootblock/early_chipset_config.S b/src/soc/intel/apollolake/bootblock/early_chipset_config.S index a673a28..4f35211 100644 --- a/src/soc/intel/apollolake/bootblock/early_chipset_config.S +++ b/src/soc/intel/apollolake/bootblock/early_chipset_config.S @@ -10,6 +10,7 @@ * (at your option) any later version. */ +#include <cpu/x86/post_code.h> #include <soc/gpio_defs.h> /* Definitions used only here, for getting the MMIO base of LPC pad registers */ @@ -17,47 +18,40 @@ #define PAD_MMIO_ADDR(pad) (CONFIG_IOSF_BASE_ADDRESS + XLATE_LPC(pad)) -.intel_syntax noprefix -.extern cache_as_ram - -#define post_code(value) \ - mov al, value; \ - outb CONFIG_POST_IO_PORT, al - .global bootblock_pre_c_entry bootblock_pre_c_entry: /* * eax: BIST value */ - movd mm2, eax + movd %eax, %mm2 post_code(0x20) enable_pciex_bar: - mov eax, 0x80000060 /* ROOT PCI device reg60 PCIEX_BAR_*/ - mov dx, 0xcf8 - out dx, eax - mov eax, (CONFIG_MMCONF_BASE_ADDRESS | 1) - mov dx, 0xcfc - out dx, eax + mov $0x80000060, %eax /* ROOT PCI device reg60 PCIEX_BAR_*/ + mov $0xcf8, %dx + out %eax, %dx + mov $(CONFIG_MMCONF_BASE_ADDRESS | 1), %eax + mov $0xcfc, %dx + out %eax, %dx enable_iosf_bar: - mov ebp, 0xe0068000 /* IOSF PCI device */ - mov dword ptr [ebp + 0x10], CONFIG_IOSF_BASE_ADDRESS /* BAR 0 */ - mov word ptr [ebp + 0x04], 0x06 /* PCI command */ + mov $0xe0068000, %ebp /* IOSF PCI device */ + movl $CONFIG_IOSF_BASE_ADDRESS, 0x10(%ebp) /* BAR 0 */ + movl $0x06, 0x04(%ebp) /* PCI command */ /* We need LPC for port80, but it won't work if the pads are not configured */ configure_lpc_pads: - mov ecx, offset num_lpc_pads /* Number of pads to configure */ - lea esi, lpc_pad_params + mov $num_lpc_pads, %ecx /* Number of pads to configure */ + lea lpc_pad_params, %esi init_lpc_pad: - mov edi, [esi + 0x00] /* MMIO addr of pad config registers */ - mov eax, [esi + 0x04] /* Pad CONF0 value */ - mov edx, [esi + 0x08] /* Pad CONF1 value */ - mov [edi + 0x00], eax /* Write CONF0 to config register */ - mov [edi + 0x04], edx /* Write CONF1 to config register */ - add esi, 0x0c + mov 0x00(%esi), %edi /* MMIO addr of pad config registers */ + mov 0x04(%esi), %eax /* Pad CONF0 value */ + mov 0x08(%esi), %edx /* Pad CONF1 value */ + mov %eax, 0x00(%edi) /* Write CONF0 to config register */ + mov %edx, 0x04(%edi) /* Write CONF1 to config register */ + add $0x0c, %esi loop init_lpc_pad jmp cache_as_ram diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc index 2c6dfd6..2e018ae 100644 --- a/src/soc/intel/apollolake/romstage/entry.inc +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -10,13 +10,12 @@ * (at your option) any later version. */ -.intel_syntax noprefix apollolake_entry: /* * TODO: Make sure the stack does not clash with .car.data. */ - mov esp, (CONFIG_DCACHE_RAM_BASE + 0x4000) + mov $(CONFIG_DCACHE_RAM_BASE + 0x4000), %esp call romstage_entry @@ -25,7 +24,7 @@ apollolake_entry: * to use as stack. The old stack is empty at this point, so we don't * have to relocate anything. */ - mov esp, eax + mov %eax, %esp /* * TODO: set up temporary cache for RAM

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Patch set updated for coreboot: board_status/getrevision.sh: get rid of colons in dir names
by Martin Roth 27 Jan '16

27 Jan '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13490 -gerrit commit 69c614541bce6c16cf3080759717aa239af16957 Author: Martin Roth <martinroth(a)google.com> Date: Wed Jan 27 09:53:45 2016 -0700 board_status/getrevision.sh: get rid of colons in dir names Gnu make won't build in directories that have a colon in their name. When the makefile expands a variable containing a dirctory name that has colons in it, it seems to interpret that as a makefile target, and fails the build. Many other characters also confuse the makefiles, including spaces, ampersand symbols, dollar signs, etc. I've started including scripts into the board-status directories to do the build of the rom that was tested, and this is preventing them from working without renaming the directory before doing the build. Change-Id: I9dd8e4027be21363015cd8df9918610e206afce2 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/board_status/getrevision.sh | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/board_status/getrevision.sh b/util/board_status/getrevision.sh index 6559df3..168c972 100755 --- a/util/board_status/getrevision.sh +++ b/util/board_status/getrevision.sh @@ -96,7 +96,10 @@ timestamp() { if [ -z "$t" ]; then echo "Warning: Could not determine timestamp." 2>/dev/null fi - echo "${t}" + + # output the time, changing colons to underscores. + # gnu make doesn't work in directories with colons + echo "${t}" | tr ':' '_' } # Retrieve local SCM revision info. This is useful if we're working in a different SCM than upstream and/or

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Patch set updated for coreboot: Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled.
by Jean Lucas 27 Jan '16

27 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit b5965be45e45cf97cdfc537daeecdc7f15227e49 Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled. Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db --- src/mainboard/google/peppy/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..9eb4910 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15

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New patch to review for coreboot: Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled.
by Jean Lucas 27 Jan '16

27 Jan '16

Jean Lucas (jean(a)4ray.co) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13493 -gerrit commit 89713e5cb2890acda30539ce2e5189fa3cfcfc43 Author: Jean Lucas <jean(a)4ray.co> Date: Wed Jan 27 16:04:43 2016 -0500 Remove the default select of "Use native graphics initialization" for Peppy as not all build targets require this option enabled. Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db --- src/mainboard/google/peppy/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig index 428d293..9eb4910 100644 --- a/src/mainboard/google/peppy/Kconfig +++ b/src/mainboard/google/peppy/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_DO_NATIVE_VGA_INIT select INTEL_DP select INTEL_DDI select INTEL_INT15

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Patch merged into coreboot/master: drivers/intel/fsp1_1: Enable builds without MRC cache
by gerrit＠coreboot.org 27 Jan '16

27 Jan '16

the following patch was just integrated into master: commit a608969ebbc556499a20edbb25c2ef45a7434871 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 5 16:34:58 2016 -0800 drivers/intel/fsp1_1: Enable builds without MRC cache Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13437 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13437 for details. -gerrit

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Patch set updated for coreboot: via/cx700: Use zeroptr over 0
by Patrick Georgi 27 Jan '16

27 Jan '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13488 -gerrit commit 4da0fcb53a354861317c970597e3922c88785410 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed Jan 27 08:19:36 2016 +0100 via/cx700: Use zeroptr over 0 This eliminates all "ud2" instances from romstage disassembly. Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/northbridge/via/cx700/raminit.c | 84 ++++++++++++++++++------------------- 1 file changed, 42 insertions(+), 42 deletions(-) diff --git a/src/northbridge/via/cx700/raminit.c b/src/northbridge/via/cx700/raminit.c index 249f265..2016a87 100644 --- a/src/northbridge/via/cx700/raminit.c +++ b/src/northbridge/via/cx700/raminit.c @@ -989,7 +989,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 4 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); // Step 5 @@ -1001,7 +1001,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 7 printk(BIOS_SPEW, "SEND: "); - read32((void *)0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); /* Step 8. Mode register set. */ @@ -1029,7 +1029,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 12 printk(BIOS_SPEW, "SEND: "); - read32((u32 *)0x0); + read32(zeroptr); printk(BIOS_SPEW, "OK\n"); /* Step 13. Perform 8 refresh cycles. Wait tRC each time. */ @@ -1040,7 +1040,7 @@ static void step_2_19(const struct mem_controller *ctrl) // Step 16: Repeat Step 14 and 15 another 7 times for (i = 0; i < 8; i++) { // Step 14 - read32((u32 *)0); + read32(zeroptr); printk(BIOS_SPEW, "."); // Step 15 @@ -1127,45 +1127,45 @@ static void sdram_calc_size(const struct mem_controller *ctrl, u8 num) u8 ca, ra, ba, reg; ba = pci_read_config8(PCI_DEV(0, 0, 4), SCRATCH_FLAGS); if (ba == 8) { - write8((void *)0, 0x0d); - ra = read8((void *)0); + write8(zeroptr, 0x0d); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_12_8bk), 0x0c); - ra = read8((void *)0); + ra = read8(zeroptr); - write8((void *)0, 0x0a); - ca = read8((void *)0); + write8(zeroptr, 0x0a); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_09_8bk), 0x0c); - ca = read8((void *)0); + ca = read8(zeroptr); - write8((void *)0, 0x03); - ba = read8((void *)0); + write8(zeroptr, 0x03); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - ba = read8((void *)0); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - ba = read8((void *)0); + ba = read8(zeroptr); } else { - write8((void *)0, 0x0f); - ra = read8((void *)0); + write8(zeroptr, 0x0f); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_14), 0x0e); - ra = read8((void *)0); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_13), 0x0d); - ra = read8((void *)0); + ra = read8(zeroptr); write8((void *)(1 << SDRAM1X_RA_12), 0x0c); - ra = read8((void *)0); + ra = read8(zeroptr); - write8((void *)0, 0x0c); - ca = read8((void *)0); + write8(zeroptr, 0x0c); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_12), 0x0b); - ca = read8((void *)0); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_11), 0x0a); - ca = read8((void *)0); + ca = read8(zeroptr); write8((void *)(1 << SDRAM1X_CA_09), 0x09); - ca = read8((void *)0); + ca = read8(zeroptr); - write8((void *)0, 0x02); - ba = read8((void *)0); + write8(zeroptr, 0x02); + ba = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - ba = read8((void *)0); + ba = read8(zeroptr); } if (ra < 10 || ra > 15) @@ -1271,17 +1271,17 @@ static void sdram_enable(const struct mem_controller *ctrl) if (reg8) { sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(zeroptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(zeroptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(zeroptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(zeroptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1304,17 +1304,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); - write32((void *)0, 0x55555555); + write32(zeroptr, 0x55555555); write32((void *)4, 0x55555555); udelay(15); - if (read32((void *)0) != 0x55555555) + if (read32(zeroptr) != 0x55555555) break; if (read32((void *)4) != 0x55555555) break; - write32((void *)0, 0xaaaaaaaa); + write32(zeroptr, 0xaaaaaaaa); write32((void *)4, 0xaaaaaaaa); udelay(15); - if (read32((void *)0) != 0xaaaaaaaa) + if (read32(zeroptr) != 0xaaaaaaaa) break; if (read32((void *)4) != 0xaaaaaaaa) break; @@ -1358,17 +1358,17 @@ static void sdram_enable(const struct mem_controller *ctrl) sdram_set_vr(ctrl, i); sdram_ending_addr(ctrl, i); if (reg8 == 4) { - write8((void *)0, 0x02); - val = read8((void *)0); + write8(zeroptr, 0x02); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1), 0x01); - val = read8((void *)0); + val = read8(zeroptr); } else { - write8((void *)0, 0x03); - val = read8((void *)0); + write8(zeroptr, 0x03); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA2_8bk), 0x02); - val = read8((void *)0); + val = read8(zeroptr); write8((void *)(1 << SDRAM1X_BA1_8bk), 0x01); - val = read8((void *)0); + val = read8(zeroptr); } if (val < dl) dl = val;

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Patch set updated for coreboot: drivers/intel/fsp1_1: Enable builds without MRC cache
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13437 -gerrit commit 751ab585ebc1c603f04d5c3009f8fa61bef4b604 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 5 16:34:58 2016 -0800 drivers/intel/fsp1_1: Enable builds without MRC cache Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/romstage.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..b17927a 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -128,8 +128,9 @@ void romstage_common(struct romstage_params *params) /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current_with_version(&cache, - params->fsp_version)) { + } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) + && (!mrc_cache_get_current_with_version(&cache, + params->fsp_version))) { /* MRC cache found */ params->pei_data->saved_data_size = cache->size; params->pei_data->saved_data = &cache->data[0]; @@ -150,16 +151,16 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); /* Save MRC output */ - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); - if (params->pei_data->boot_mode != SLEEP_STATE_S3) { - if (params->pei_data->data_to_save_size != 0 && - params->pei_data->data_to_save != NULL) { - mrc_cache_stash_data_with_version( - params->pei_data->data_to_save, - params->pei_data->data_to_save_size, - params->fsp_version); - } + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", + pei_data->data_to_save, pei_data->data_to_save_size); + if ((params->pei_data->boot_mode != SLEEP_STATE_S3) + && (params->pei_data->data_to_save_size != 0) + && (params->pei_data->data_to_save != NULL)) + mrc_cache_stash_data_with_version( + params->pei_data->data_to_save, + params->pei_data->data_to_save_size, + params->fsp_version); } /* Save DIMM information */

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Patch set updated for coreboot: FSP 1.1: Enable builds without MRC cache
by Leroy P Leahy 27 Jan '16

27 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13437 -gerrit commit 450f78e4395fa0f1a93ae9f3c3267712e83b4358 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue Jan 5 16:34:58 2016 -0800 FSP 1.1: Enable builds without MRC cache Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to cache the MRC settings. BRANCH=none BUG=None TEST=Build and run on Galileo Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/romstage.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 16db4df..b17927a 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2016 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -128,8 +128,9 @@ void romstage_common(struct romstage_params *params) /* Recovery mode does not use MRC cache */ printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); - } else if (!mrc_cache_get_current_with_version(&cache, - params->fsp_version)) { + } else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) + && (!mrc_cache_get_current_with_version(&cache, + params->fsp_version))) { /* MRC cache found */ params->pei_data->saved_data_size = cache->size; params->pei_data->saved_data = &cache->data[0]; @@ -150,16 +151,16 @@ void romstage_common(struct romstage_params *params) timestamp_add_now(TS_AFTER_INITRAM); /* Save MRC output */ - printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", pei_data->data_to_save, - pei_data->data_to_save_size); - if (params->pei_data->boot_mode != SLEEP_STATE_S3) { - if (params->pei_data->data_to_save_size != 0 && - params->pei_data->data_to_save != NULL) { - mrc_cache_stash_data_with_version( - params->pei_data->data_to_save, - params->pei_data->data_to_save_size, - params->fsp_version); - } + if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { + printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", + pei_data->data_to_save, pei_data->data_to_save_size); + if ((params->pei_data->boot_mode != SLEEP_STATE_S3) + && (params->pei_data->data_to_save_size != 0) + && (params->pei_data->data_to_save != NULL)) + mrc_cache_stash_data_with_version( + params->pei_data->data_to_save, + params->pei_data->data_to_save_size, + params->fsp_version); } /* Save DIMM information */

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coreboot-gerrit January 2016