coreboot-gerrit January 2016

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Patch set updated for coreboot: intel/strago: Enable native mode on sd card cd line
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741 -gerrit commit 84f496b990e1cecceb83b1eb723f2258cb7cfad1 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Nov 4 14:25:15 2015 -0800 intel/strago: Enable native mode on sd card cd line Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 4b58eac..11e2553 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,8 +74,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */

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Patch set updated for coreboot: intel/strago: Remove support for older rev boards
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13434 -gerrit commit 8eedcc7154aad724973d75589fea0658c6375add Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Jan 25 14:36:56 2016 -0800 intel/strago: Remove support for older rev boards Cleaning up code to remove support for early revs of Strago board Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/Makefile.inc | 2 - src/mainboard/intel/strago/acpi/mainboard.asl | 49 +---- src/mainboard/intel/strago/acpi_tables.c | 5 +- src/mainboard/intel/strago/gpio.c | 9 +- src/mainboard/intel/strago/gpio.h | 21 -- src/mainboard/intel/strago/gpio_bcrd2.c | 268 -------------------------- src/mainboard/intel/strago/gpio_dvt.c | 265 ------------------------- src/mainboard/intel/strago/onboard.h | 7 +- src/mainboard/intel/strago/ramstage.c | 6 +- src/mainboard/intel/strago/smihandler.c | 8 +- 10 files changed, 13 insertions(+), 627 deletions(-) diff --git a/src/mainboard/intel/strago/Makefile.inc b/src/mainboard/intel/strago/Makefile.inc index 9c21bed..5ba7bcc 100755 --- a/src/mainboard/intel/strago/Makefile.inc +++ b/src/mainboard/intel/strago/Makefile.inc @@ -22,8 +22,6 @@ ramstage-y += boardid.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += chromeos.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += ec.c ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_dvt.c -ramstage-$(CONFIG_MAINBOARD_HAS_CHROMEOS) += gpio_bcrd2.c ramstage-y += irqroute.c ramstage-y += ramstage.c ramstage-y += w25q64.c diff --git a/src/mainboard/intel/strago/acpi/mainboard.asl b/src/mainboard/intel/strago/acpi/mainboard.asl index 48cabff..0353eed 100755 --- a/src/mainboard/intel/strago/acpi/mainboard.asl +++ b/src/mainboard/intel/strago/acpi/mainboard.asl @@ -68,25 +68,7 @@ Scope (\_SB.I2C1) BOARD_TOUCH_IRQ } }) - Name (BUF1, ResourceTemplate () - { - I2cSerialBus( - 0x26, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_DVT_TOUCH_IRQ - } - }) - If (LEqual (\BDID, BOARD_EVT)) { - Return (BUF0) - } Else { - Return (BUF1) - } + Return (BUF0) } Method (_STA) @@ -125,25 +107,7 @@ Scope (\_SB.I2C1) BOARD_TOUCH_IRQ } }) - Name (BUF1, ResourceTemplate () - { - I2cSerialBus( - 0x4b, /* SlaveAddress */ - ControllerInitiated, /* SlaveMode */ - 400000, /* ConnectionSpeed */ - AddressingMode7Bit, /* AddressingMode */ - "\\_SB.I2C1", /* ResourceSource */ - ) - Interrupt (ResourceConsumer, Edge, ActiveLow) - { - BOARD_DVT_TOUCH_IRQ - } - }) - If (LEqual (\BDID, BOARD_EVT)) { - Return (BUF0) - } Else { - Return (BUF1) - } + Return (BUF0) } Method (_STA) @@ -164,7 +128,6 @@ Scope (\_SB.I2C1) Scope (\_SB.I2C5) { - /* Realtek Audio Codec */ Device (RTEK) /* Audio Codec driver I2C */ { @@ -186,7 +149,6 @@ Scope (\_SB.I2C5) "\\_SB.I2C5", /* ResourceSource: I2C bus controller name */ ) - /* Jack Detect (index 0) */ GpioInt (Edge, ActiveLow, ExclusiveAndWake, PullNone,, "\\_SB.GPSW") { JACK_DETECT_GPIO_INDEX } @@ -196,12 +158,7 @@ Scope (\_SB.I2C5) Method (_STA) { - If (LEqual (\S5EN, 1)) { - If (LEqual (\BDID, BOARD_BCRD2)) { - Return (0xF) - } - } - Return (0x0) + Return (0xF) } } } diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index 72538b7..591d934 100755 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -47,8 +47,9 @@ void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable DPTF */ gnvs->dpte = 1; - if (board_id() == BOARD_BCRD2) - gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; + + /* PMIC is configured in I2C1, hidden it from OS */ + gnvs->dev.lpss_en[LPSS_NVS_I2C2] = 0; } unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 2157c8d..5331eba 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -262,12 +262,5 @@ static struct soc_gpio_config gpio_config = { struct soc_gpio_config *mainboard_get_gpios(void) { - switch (board_id()) { - case BOARD_DVT: - return get_override_gpios_dvt(); - case BOARD_BCRD2: - return get_override_gpios_bcrd2(); - default: - return &gpio_config; - } + return &gpio_config; } diff --git a/src/mainboard/intel/strago/gpio.h b/src/mainboard/intel/strago/gpio.h deleted file mode 100644 index c775995..0000000 --- a/src/mainboard/intel/strago/gpio.h +++ /dev/null @@ -1,21 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ -#ifndef _BOARD_GPIO_H_ -#define _BOARD_GPIO_H_ - -struct soc_gpio_config *get_override_gpios_dvt(void); -struct soc_gpio_config *get_override_gpios_bcrd2(void); -#endif diff --git a/src/mainboard/intel/strago/gpio_bcrd2.c b/src/mainboard/intel/strago/gpio_bcrd2.c deleted file mode 100644 index 4cd622b..0000000 --- a/src/mainboard/intel/strago/gpio_bcrd2.c +++ /dev/null @@ -1,268 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include <soc/gpio.h> -#include <stdlib.h> -#include "gpio.h" - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), - /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 46 I2C4_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPIO_NC, - /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ - GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, - en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPIO_NC, /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - Native_M1, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - - -static struct soc_gpio_config gpio_config = { - /* BSW */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *get_override_gpios_bcrd2(void) -{ - return &gpio_config; - -} diff --git a/src/mainboard/intel/strago/gpio_dvt.c b/src/mainboard/intel/strago/gpio_dvt.c deleted file mode 100755 index 24c6b3d..0000000 --- a/src/mainboard/intel/strago/gpio_dvt.c +++ /dev/null @@ -1,265 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright(C) 2013 Google Inc. - * Copyright (C) 2015 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "irqroute.h" -#include <soc/gpio.h> -#include <stdlib.h> -#include "gpio.h" - -/* South East Community */ -static const struct soc_gpio_map gpse_gpio_map[] = { - Native_M1,/* MF_PLT_CLK0 */ - GPIO_NC, /* 01 PWM1 */ - GPIO_INPUT_NO_PULL, /* 02 MF_PLT_CLK1, RAMID2 */ - GPIO_NC, /* 03 MF_PLT_CLK4 */ - GPIO_NC, /* 04 MF_PLT_CLK3 */ - GPIO_NC, /* PWM0 05 */ - GPIO_NC, /* 06 MF_PLT_CLK5 */ - GPIO_NC, /* 07 MF_PLT_CLK2 */ - GPIO_NC, /* 15 SDMMC2_D3_CD_B */ - Native_M1, /* 16 SDMMC1_CLK */ - NATIVE_PU20K(1), /* 17 SDMMC1_D0 */ - GPIO_NC, /* 18 SDMMC2_D1 */ - GPIO_NC, /* 19 SDMMC2_CLK */ - NATIVE_PU20K(1),/* 20 SDMMC1_D2 */ - GPIO_NC, /* 21 SDMMC2_D2 */ - GPIO_NC, /* 22 SDMMC2_CMD */ - NATIVE_PU20K(1), /* 23 SDMMC1_CMD */ - NATIVE_PU20K(1), /* 24 SDMMC1_D1 */ - GPIO_NC, /* 25 SDMMC2_D0 */ - NATIVE_PU20K(1), /* 26 SDMMC1_D3_CD_B */ - NATIVE_PU20K(1), /* 30 SDMMC3_D1 */ - Native_M1, /* 31 SDMMC3_CLK */ - NATIVE_PU20K(1), /* 32 SDMMC3_D3 */ - NATIVE_PU20K(1), /* 33 SDMMC3_D2 */ - NATIVE_PU20K(1), /* 34 SDMMC3_CMD */ - NATIVE_PU20K(1), /* 35 SDMMC3_D0 */ - NATIVE_PU20K(1), /* 45 MF_LPC_AD2 */ - Native_M1, /* 46 LPC_CLKRUNB */ - NATIVE_PU20K(1), /* 47 MF_LPC_AD0 */ - Native_M1, /* 48 LPC_FRAMEB */ - Native_M1, /* 49 MF_LPC_CLKOUT1 */ - NATIVE_PU20K(1), /* 50 MF_LPC_AD3 */ - Native_M1, /* 51 MF_LPC_CLKOUT0 */ - NATIVE_PU20K(1), /* 52 MF_LPC_AD1 */ - Native_M1,/* SPI1_MISO */ - Native_M1, /* 61 SPI1_CS0_B */ - Native_M1, /* SPI1_CLK */ - NATIVE_PU20K(1), /* 63 MMC1_D6 */ - Native_M1, /* 62 SPI1_MOSI */ - NATIVE_PU20K(1), /* 65 MMC1_D5 */ - GPIO_NC, /* SPI1_CS1_B 66 */ - NATIVE_PU20K(1), /* 67 MMC1_D4_SD_WE */ - NATIVE_PU20K(1), /* 68 MMC1_D7 */ - GPIO_NC, /* 69 MMC1_RCLK */ - Native_M1, /* 75 GPO USB_OC1_B */ - Native_M1, /* 76 PMU_RESETBUTTON_B */ - GPI(trig_edge_both, L0, NA, non_maskable, en_edge_detect, NA , NA), - /* GPIO_ALERT 77 */ - Native_M1, /* 78 SDMMC3_PWR_EN_B */ - GPIO_NC, /* 79 GPI ILB_SERIRQ */ - Native_M1, /* 80 USB_OC0_B */ - NATIVE_INT(1, L1), /* 81 SDMMC3_CD_B */ - GPIO_NC, /* 82 spkr asummed gpio number */ - Native_M1, /* 83 SUSPWRDNACK */ - SPARE_PIN,/* 84 spare pin */ - Native_M1, /* 85 SDMMC3_1P8_EN */ - GPIO_END -}; - - -/* South West Community */ -static const struct soc_gpio_map gpsw_gpio_map[] = { - GPIO_NC, /* 00 FST_SPI_D2 */ - Native_M1, /* 01 FST_SPI_D0 */ - Native_M1, /* 02 FST_SPI_CLK */ - GPIO_NC, /* 03 FST_SPI_D3 */ - GPIO_NC, /* GPO FST_SPI_CS1_B */ - Native_M1, /* 05 FST_SPI_D1 */ - Native_M1, /* 06 FST_SPI_CS0_B */ - GPIO_NC, /* 07 FST_SPI_CS2_B */ - GPIO_NC, /* 15 UART1_RTS_B */ - Native_M2, /* 16 UART1_RXD */ - GPIO_NC, /* 17 UART2_RXD */ - GPIO_NC, /* 18 UART1_CTS_B */ - GPIO_NC, /* 19 UART2_RTS_B */ - Native_M2, /* 20 UART1_TXD */ - GPIO_NC, /* 21 UART2_TXD */ - GPIO_NC, /* 22 UART2_CTS_B */ - GPIO_NC, /* 30 MF_HDA_CLK */ - GPIO_NC, /* 31 GPIO_SW31/MF_HDA_RSTB */ - GPIO_NC, /* 32 GPIO_SW32 /MF_HDA_SDI0 */ - GPIO_NC, /* 33 MF_HDA_SDO */ - GPI(trig_edge_both, L3, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 34 MF_HDA_DOCKRSTB */ - GPIO_NC, /* 35 MF_HDA_SYNC */ - GPIO_NC, /* 36 GPIO_SW36 MF_HDA_SDI1 */ - GPI(trig_edge_both, L2, P_1K_H, non_maskable, en_edge_detect, NA, NA), - /* 37 MF_HDA_DOCKENB */ - NATIVE_PU1K_CSEN_INVTX(1), /* 45 I2C5_SDA */ - GPIO_NC, /* 46 I2C4_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 47 I2C6_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 48 I2C5_SCL */ - GPIO_NC, /* 49 I2C_NFC_SDA */ - GPIO_NC, /* 50 I2C4_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 51 I2C6_SCL */ - GPIO_NC, /* 52 I2C_NFC_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 60 I2C1_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 61 I2C0_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 62 I2C2_SDA */ - NATIVE_PU1K_CSEN_INVTX(1), /* 63 I2C1_SCL */ - GPIO_INPUT_NO_PULL, /* 64 I2C3_SDA RAMID3*/ - NATIVE_PU1K_CSEN_INVTX(1), /* 65 I2C0_SCL */ - NATIVE_PU1K_CSEN_INVTX(1), /* 66 I2C2_SCL */ - GPIO_INPUT_NO_PULL,/* 67 I2C3_SCL,RAMID1 */ - GPIO_OUT_HIGH, /* 75 SATA_GP0 */ - GPIO_NC, - /* 76 GPI SATA_GP1 */ - Native_M1, /* 77 SATA_LEDN */ - GPIO_NC, /* 80 SATA_GP3 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - GPIO_INPUT_NO_PULL, /* 80 SATA_GP3,RAMID0 */ - Native_M1, /* 81 NFC_DEV_WAKE , MF_SMB_CLK */ - Native_M1, /* 82 NFC_FW_DOWNLOAD, MF_SMB_DATA */ - /* Per DE request, change PCIE_CLKREQ0123B to GPIO_INPUT */ - Native_M1, /* 90 PCIE_CLKREQ0B */ - GPIO_INPUT_PU_20K, /* 91 GPI PCIE_CLKREQ1B/LTE_WAKE# */ - Native_M1, /* 92 GP_SSP_2_CLK */ - NATIVE_PU20K(1), /* 93 PCIE_CLKREQ2B/PCIE_CLKREQ_WLAN# */ - Native_M1, /* 94 GP_SSP_2_RXD */ - GPI(trig_edge_both, L1, P_5K_H, non_maskable, en_edge_detect, NA, NA), - /* 95 PCIE_CLKREQ3B/AUDIO_CODEC_IRQ */ - Native_M1, /* 96 GP_SSP_2_FS */ - NATIVE_FUNC(1, 0, inv_tx_enable), /* 97 GP_SSP_2f_TXD */ - GPIO_END -}; - - -/* North Community */ -static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ - GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , - UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ - GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ - GPI(trig_edge_low, L0, P_1K_H, non_maskable, NA, NA, NA), - /* 17 GPIO_SUS3 */ - GPI(trig_edge_low, L1, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 18 GPIO_SUS7 */ - GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), - /* 19 GPIO_SUS1 */ - GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ - GPIO_NC, /* 22 GPIO_SUS4 */ - GPIO_NC, - /* 23 SEC_GPIO_SUS8 */ - Native_M6, /* 24 GPIO_SUS2 */ - GPIO_INPUT_PU_5K,/* 25 GPIO_SUS6 */ - Native_M1, /* 26 CX_PREQ_B */ - GPIO_NC, /* 27 SEC_GPIO_SUS9 */ - Native_M1, /* 30 TRST_B */ - Native_M1, /* 31 TCK */ - GPIO_SKIP, /* 32 PROCHOT_B */ - GPIO_SKIP, /* 33 SVID0_DATA */ - Native_M1, /* 34 TMS */ - GPIO_NC, /* 35 CX_PRDY_B_2 */ - GPIO_NC, /* 36 TDO_2 */ - Native_M1, /* 37 CX_PRDY_B */ - GPIO_SKIP, /* 38 SVID0_ALERT_B */ - Native_M1, /* 39 TDO */ - GPIO_SKIP, /* 40 SVID0_CLK */ - Native_M1, /* 41 TDI */ - Native_M2, /* 45 GP_CAMERASB05 */ - Native_M2, /* 46 GP_CAMERASB02 */ - Native_M2, /* 47 GP_CAMERASB08 */ - Native_M2, /* 48 GP_CAMERASB00 */ - Native_M2, /* 49 GP_CAMERASBO6 */ - GPIO_NC, /* 50 GP_CAMERASB10 */ - Native_M2, /* 51 GP_CAMERASB03 */ - GPIO_NC, /* 52 GP_CAMERASB09 */ - Native_M2, /* 53 GP_CAMERASB01 */ - Native_M2, /* 54 GP_CAMERASB07 */ - GPIO_NC, /* 55 GP_CAMERASB11 */ - Native_M2, /* 56 GP_CAMERASB04 */ - GPIO_NC, /* 60 PANEL0_BKLTEN */ - Native_M1, /* 61 HV_DDI0_HPD */ - NATIVE_PU1K_M1, /* 62 HV_DDI2_DDC_SDA */ - Native_M1, /* 63 PANEL1_BKLTCTL */ - NATIVE_TX_RX_EN, /* 64 HV_DDI1_HPD */ - GPIO_NC, /* 65 PANEL0_BKLTCTL */ - GPIO_NC, /* 66 HV_DDI0_DDC_SDA */ - NATIVE_PU1K_M1, /* 67 HV_DDI2_DDC_SCL */ - NATIVE_TX_RX_EN, /* 68 HV_DDI2_HPD */ - Native_M1, /* 69 PANEL1_VDDEN */ - Native_M1, /* 70 PANEL1_BKLTEN */ - GPIO_NC, /* 71 HV_DDI0_DDC_SCL */ - GPIO_NC, /* 72 PANEL0_VDDEN */ - GPIO_END -}; - - -/* East Community */ -static const struct soc_gpio_map gpe_gpio_map[] = { - Native_M1, /* 00 PMU_SLP_S3_B */ - GPIO_NC, /* 01 PMU_BATLOW_B */ - Native_M1, /* 02 SUS_STAT_B */ - Native_M1, /* 03 PMU_SLP_S0IX_B */ - Native_M1, /* 04 PMU_AC_PRESENT */ - Native_M1, /* 05 PMU_PLTRST_B */ - Native_M1, /* 06 PMU_SUSCLK */ - GPIO_NC, /* 07 PMU_SLP_LAN_B */ - Native_M1, /* 08 PMU_PWRBTN_B */ - Native_M1, /* 09 PMU_SLP_S4_B */ - NATIVE_FUNC(M1, P_1K_H, NA), /* 10 PMU_WAKE_B */ - GPIO_NC, /* 11 PMU_WAKE_LAN_B */ - GPIO_NC, /* 15 MF_GPIO_3 */ - GPIO_NC, /* 16 MF_GPIO_7 */ - GPIO_NC, /* 17 MF_I2C1_SCL */ - GPIO_NC, /* 18 MF_GPIO_1 */ - GPIO_NC, /* 19 MF_GPIO_5 */ - GPIO_NC, /* 20 MF_GPIO_9 */ - GPIO_NC, /* 21 MF_GPIO_0 */ - GPIO_NC, /* 22 MF_GPIO_4 */ - GPIO_NC, /* 23 MF_GPIO_8 */ - GPIO_NC, /* 24 MF_GPIO_2 */ - GPIO_NC, /* 25 MF_GPIO_6 */ - GPIO_NC, /* 26 MF_I2C1_SDA */ - GPIO_END -}; - - -static struct soc_gpio_config gpio_config = { - /* BSW */ - .north = gpn_gpio_map, - .southeast = gpse_gpio_map, - .southwest = gpsw_gpio_map, - .east = gpe_gpio_map -}; - -struct soc_gpio_config *get_override_gpios_dvt(void) -{ - return &gpio_config; - -} diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 89c9b69..4527365 100755 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -37,8 +37,7 @@ /* ToDo: change kbd irq to gpio bank index */ #define BOARD_I8042_IRQ 182 -#define BOARD_TOUCH_IRQ 156 -#define BOARD_DVT_TOUCH_IRQ 184 +#define BOARD_TOUCH_IRQ 184 /* Audio: Gpio index in SW bank */ @@ -68,10 +67,6 @@ #define AUDIO_CODEC_DDN "RTEK Codec Controller " #define AUDIO_CODEC_I2C_ADDR 0x1A -#define BOARD_EVT 0x02 -#define BOARD_DVT 0x03 -#define BOARD_BCRD2 0x04 - #define BCRD2_PMIC_I2C_BUS 0x01 #endif diff --git a/src/mainboard/intel/strago/ramstage.c b/src/mainboard/intel/strago/ramstage.c index c5cff68..a05cd90 100644 --- a/src/mainboard/intel/strago/ramstage.c +++ b/src/mainboard/intel/strago/ramstage.c @@ -19,8 +19,6 @@ void mainboard_silicon_init_params(SILICON_INIT_UPD *params) { - if (board_id() == BOARD_BCRD2) { - params->ChvSvidConfig = SVID_PMIC_CONFIG; - params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; - } + params->ChvSvidConfig = SVID_PMIC_CONFIG; + params->PMIC_I2CBus = BCRD2_PMIC_I2C_BUS; } diff --git a/src/mainboard/intel/strago/smihandler.c b/src/mainboard/intel/strago/smihandler.c index b465e3a..0f77bf3 100755 --- a/src/mainboard/intel/strago/smihandler.c +++ b/src/mainboard/intel/strago/smihandler.c @@ -139,11 +139,9 @@ void mainboard_smi_sleep(uint8_t slp_typ) while (google_chromeec_get_event() != 0) ; - if (smm_get_gnvs()->bdid == BOARD_DVT) { - /* Set LPC lines to low power in S3/S5. */ - if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) - lpc_set_low_power(); - } + /* Set LPC lines to low power in S3/S5. */ + if ((slp_typ == SLEEP_STATE_S3) || (slp_typ == SLEEP_STATE_S5)) + lpc_set_low_power(); #endif }

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Patch set updated for coreboot: Braswell: Separate L1 Sub State init procedure for boards.
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12750 -gerrit commit c220eea63bb15693e6cee8f551297f7c90116a85 Author: Kenji Chen <kenji.chen(a)intel.com> Date: Mon Nov 16 17:08:32 2015 +0800 Braswell: Separate L1 Sub State init procedure for boards. Original-Reviewed-on: https://chromium-review.googlesource.com/312743 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Change-Id: Ib0a891f229477cf359bff6cd02f305606468f07f Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> --- src/mainboard/google/cyan/Kconfig | 1 + src/mainboard/intel/strago/Kconfig | 1 + src/soc/intel/braswell/Kconfig | 1 - 3 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/cyan/Kconfig b/src/mainboard/google/cyan/Kconfig index c5a1346..5eb0815 100644 --- a/src/mainboard/google/cyan/Kconfig +++ b/src/mainboard/google/cyan/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_BRASWELL select HAVE_ACPI_RESUME + select PCIEXP_L1_SUB_STATE config CHROMEOS select LID_SWITCH diff --git a/src/mainboard/intel/strago/Kconfig b/src/mainboard/intel/strago/Kconfig index f23a86c..6587d5a 100755 --- a/src/mainboard/intel/strago/Kconfig +++ b/src/mainboard/intel/strago/Kconfig @@ -13,6 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM select SOC_INTEL_BRASWELL + select PCIEXP_L1_SUB_STATE config CHROMEOS select LID_SWITCH diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index c546e40..a64505e 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS select PCIEXP_ASPM select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK - select PCIEXP_L1_SUB_STATE select PLATFORM_USES_FSP1_1 select REG_SCRIPT select SOC_INTEL_COMMON

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Patch set updated for coreboot: Strago: Enable CA Mirror
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12749 -gerrit commit 720d157f06b8fbb0e1d11d6c4793a11132d74100 Author: Shobhit Srivastava <shobhit.srivastava(a)intel.com> Date: Fri Oct 9 17:05:16 2015 +0530 Strago: Enable CA Mirror Configuring UPD PcdCaMirrorEn. This is a board specific parameter. CA mirror is the Command Address mirroring option that is enabled on this board CQ-DEPEND=CL:13038 Original-Reviewed-on: https://chromium-review.googlesource.com/309190 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I05174e18d650332d838e5036c713e91c4840ee75 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/devicetree.cb | 1 + src/soc/intel/braswell/chip.h | 1 + src/soc/intel/braswell/romstage/romstage.c | 1 + 3 files changed, 3 insertions(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 2bca939..5fa613f 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -13,6 +13,7 @@ chip soc/intel/braswell register "PcdApertureSize" = "2" register "PcdGttSize" = "1" register "PcdDvfsEnable" = "0" + register "PcdCaMirrorEn" = "1" ############################################################ # Set the parameters for SiliconInit diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 341ab92..864f214 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -95,6 +95,7 @@ struct soc_intel_braswell_config { UINT8 PcdGttSize; UINT8 PcdLegacySegDecode; UINT8 PcdDvfsEnable; + UINT8 PcdCaMirrorEn; /* Command Address Mirroring Enabled */ /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 71402ac..5c38c18 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -219,6 +219,7 @@ void soc_memory_init_params(struct romstage_params *params, upd->PcdGttSize = config->PcdGttSize; upd->PcdLegacySegDecode = config->PcdLegacySegDecode; upd->PcdDvfsEnable = config->PcdDvfsEnable; + upd->PcdCaMirrorEn = config->PcdCaMirrorEn; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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Patch set updated for coreboot: soc/braswell/acpi: Fix CID1 offset in comment
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13483 -gerrit commit 2bcc0d18a78692365e8fd6428a6213c735d39888 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Tue Jan 26 15:40:24 2016 -0800 soc/braswell/acpi: Fix CID1 offset in comment Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I9fd2ebba985362fe8068c10390bb014cf9015ac5 --- src/soc/intel/braswell/acpi/globalnvs.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/acpi/globalnvs.asl b/src/soc/intel/braswell/acpi/globalnvs.asl index e7fb2ce..5c8a75f 100644 --- a/src/soc/intel/braswell/acpi/globalnvs.asl +++ b/src/soc/intel/braswell/acpi/globalnvs.asl @@ -51,7 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PM1I, 32, /* 0x15 - System Wake Source - PM1 Index */ GPEI, 32, /* 0x19 - GPE Wake Source */ BDID, 8, /* 0x1d - Board ID */ - CID1, 16, /* 0x1A - Wifi Domain Type */ + CID1, 16, /* 0x1e - Wifi Domain Type */ /* Device Config */ Offset (0x20),

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Patch set updated for coreboot: intel/strago: Disable unused lines on Gpio North Bank
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13176 -gerrit commit 4bf19c66d0df9118a7351ebd25f14a38de0f8c9b Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Thu Nov 19 11:10:34 2015 -0800 intel/strago: Disable unused lines on Gpio North Bank The unused lines leads to spurious interrupts on few of the systems. TEST=run suspend_stress test and make sure that kbd is working. Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313417 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 23 ++++++++++------------- 1 file changed, 10 insertions(+), 13 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 11e2553..47588fc 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -153,16 +153,15 @@ static const struct soc_gpio_map gpsw_gpio_map[] = { /* North Community */ static const struct soc_gpio_map gpn_gpio_map[] = { - Native_M5, /* 00 GPIO_DFX0 */ - Native_M5, /* 01 GPIO_DFX3 */ - Native_M1, /* 02 GPIO_DFX7 */ - Native_M5, /* 03 GPIO_DFX1 */ - Native_M1, /* 04 GPIO_DFX5 */ - Native_M1, /* 05 GPIO_DFX4 */ - GPI(trig_edge_low, L5, NA, non_maskable, en_rx_data, NA, NA), - /* 06 GPIO_DFX8 */ - Native_M5, /* 07 GPIO_DFX2 */ - Native_M8, /* 08 GPIO_DFX6 */ + GPIO_NC, /* 00 GPIO_DFX0 */ + GPIO_NC, /* 01 GPIO_DFX3 */ + GPIO_NC, /* 02 GPIO_DFX7 */ + GPIO_NC, /* 03 GPIO_DFX1 */ + GPIO_NC, /* 04 GPIO_DFX5 */ + GPIO_NC, /* 05 GPIO_DFX4 */ + GPIO_NC, /* 06 GPIO_DFX8 */ + GPIO_NC, /* 07 GPIO_DFX2 */ + GPIO_NC, /* 08 GPIO_DFX6 */ GPI(trig_edge_low, L8, NA, non_maskable, en_edge_rx_data , UNMASK_WAKE, SCI), /* 15 GPIO_SUS0 */ GPO_FUNC(NA, NA), /* 16 SEC_GPIO_SUS10 */ @@ -173,9 +172,7 @@ static const struct soc_gpio_map gpn_gpio_map[] = { GPI(trig_edge_low, L3, P_1K_H, non_maskable, NA, UNMASK_WAKE, NA), /* 19 GPIO_SUS1 */ GPIO_NC, /* 20 GPIO_SUS5 */ - GPI(trig_edge_high, L2, P_20K_H, non_maskable, - en_edge_rx_data, NA , NA), - /* 21 SEC_GPIO_SUS11 */ + GPIO_NC, /* 21 SEC_GPIO_SUS11 */ GPIO_NC, /* 22 GPIO_SUS4 */ GPIO_NC, /* 23 SEC_GPIO_SUS8 */

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Patch set updated for coreboot: soc/braswell: Fix DSP clock
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732 -gerrit commit 93d9aa539eab071f2b189820cb402fd78c04d1d7 Author: fdurairx <felixx.durairaj(a)intel.com> Date: Fri Aug 21 15:36:53 2015 -0700 soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 3 +-- src/mainboard/intel/strago/devicetree.cb | 3 +-- src/soc/intel/braswell/chip.h | 8 ++++++-- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- src/soc/intel/braswell/lpe.c | 24 +++++++++++------------- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..8932cf4 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index c2aa47a..2bca939 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..6eb1451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..a4b2e2d 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a1a7c64..4662b43 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev) const char *freq_str; config = dev->chip_info; - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; + switch (config->lpe_codec_clk_src) { + case LPE_CLK_SRC_XTAL: + /* XTAL driven bit2=0 */ + freq_str = "19.2MHz External Crystal"; + reg = CLK_SRC_XTAL; break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; + case LPE_CLK_SRC_PLL: + /* PLL driven bit2=1 */ + freq_str = "19.2MHz PLL"; + reg = CLK_SRC_PLL; break; default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + reg = CLK_SRC_XTAL; + printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); return; } /* Default to always running. */ reg |= CLK_CTL_ON; - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); }

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Patch set updated for coreboot: intel/cyan: Disable SD Card Detect Simulation in FSP
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13036 -gerrit commit 58f766fd272e9237d30b3b00b466590ee051ab38 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:22:12 2016 -0800 intel/cyan: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 8932cf4..9d14ba6 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

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Patch set updated for coreboot: Strago: Disable SD Card Detect Simulation in FSP
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13035 -gerrit commit cdc416f9ccaed1d50c892c1a301ca019a4122ee9 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:11:25 2016 -0800 Strago: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Change-Id: I6c39ffebe407a4ef8555b2f050a96d33709dc624 --- src/mainboard/intel/strago/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index 5fa613f..9133787 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -71,6 +71,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

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Patch set updated for coreboot: soc/braswell/acpi/DPTF: Write TCHG state on AC connect.
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12729 -gerrit commit 8b0134494b9b68ea2115f184063c1bb017704fe3 Author: Jenny TC <jenny.tc(a)intel.com> Date: Fri Jul 24 15:04:06 2015 +0530 soc/braswell/acpi/DPTF: Write TCHG state on AC connect. DPTF should update the charger cooling device state during boot time and every 3 seconds after boot. But 3 seconds polling doesn't seems to be working with current version of DPTF. This impacts charging since DPTF writes states 4 when charger is not connected at boot time. On connecting the charger, DPTF doesn't write 0 to enable charging. This issue is addressed by calling the PPPC function to read cooling device state and passing the value to SPPC to set cooling device state. This doesn't compromise safety since DPTF can override this value later based on the platform thermal condition. Also this provides additional safety measure in the unlikely event that DPTF crashes and is not re-spawned by OS. With this patch even after DPTF crashes, if the power adapter is plugged it would still allow the system to charge correctly. Original-Reviewed-on: https://chromium-review.googlesource.com/288460 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Jenny Tc <jenny.tc(a)intel.com> Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/acpi/dptf/charger.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/acpi/dptf/charger.asl b/src/soc/intel/braswell/acpi/dptf/charger.asl index 7c7f62f..a808591 100644 --- a/src/soc/intel/braswell/acpi/dptf/charger.asl +++ b/src/soc/intel/braswell/acpi/dptf/charger.asl @@ -28,7 +28,7 @@ Device (TCHG) Decrement (Local0) /* Check if charging is disabled (AC removed) */ - If (LEqual (\PWRS, Zero)) { + If (LEqual (\_SB.PCI0.LPCB.EC0.ACEX, Zero)) { /* Return last power state */ Return (Local0) } Else {

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coreboot-gerrit January 2016