coreboot-gerrit January 2016

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Patch set updated for coreboot: Documentation: x86 Enable Serial Output
by Leroy P Leahy 28 Jan '16

28 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13444 -gerrit commit 96524495489550f2aef30ddae8d0fea67df8f402 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jan 27 17:15:38 2016 -0800 Documentation: x86 Enable Serial Output Document the steps necessary to enable serial output TEST=None Change-Id: Ifc0e700d7ef54fb1e28ca9bca34b94cccd3633ac Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Development.html | 11 +++++++++ src/drivers/intel/fsp1_1/fsp1_1.html | 14 ++++++++++++ src/mainboard/intel/board.html | 25 ++++++++++++++++++++ src/soc/intel/soc.html | 44 ++++++++++++++++++++++++++++++++++++ 4 files changed, 94 insertions(+) diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html index 9889fbd..f2789a2 100644 --- a/Documentation/x86Development.html +++ b/Documentation/x86Development.html @@ -45,6 +45,17 @@ <li><a target="_blank" href="../src/soc/intel/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="../src/soc/intel/soc.html#Bootblock">bootblock</a> code</li> <li>Implement and debug the call to <a target="_blank" href="../src/soc/intel/soc.html#TempRamInit">TempRamInit</a></li> + <li>Enable the serial port + <ol type="A"> + <li>Power on, enable and configure GPIOs for the + <a target="_blank" href="../src/mainboard/intel/board.html#SerialOutput">debug serial UART</a> + </li> + <li>Add the <a target="_blank" href="../src/soc/intel/soc.html#SerialOutput">serial outupt</a> + support to romstage + </li> + </ol> + </li> + <li>Enable <a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> </ol> diff --git a/src/drivers/intel/fsp1_1/fsp1_1.html b/src/drivers/intel/fsp1_1/fsp1_1.html index ad02f3e..c65c894 100644 --- a/src/drivers/intel/fsp1_1/fsp1_1.html +++ b/src/drivers/intel/fsp1_1/fsp1_1.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> + <li>Enable <a href="#CorebootFspDebugging">coreboot/FSP Debugging</a></li> </ol> @@ -52,6 +53,19 @@ <hr> +<h1><a name="CorebootFspDebugging">Enable coreboot/FSP Debugging</a></h1> +<p> + Set the following Kconfig values: +</p> +<ul> + <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li> + <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li> + <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li> + <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li> +</ul> + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file diff --git a/src/mainboard/intel/board.html b/src/mainboard/intel/board.html index a7b5b32..c523298 100644 --- a/src/mainboard/intel/board.html +++ b/src/mainboard/intel/board.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Enable <a href="#SerialOutput">Serial Output</a></li> </ol> @@ -78,6 +79,30 @@ <hr> +<h1><a name="SerialOutput">Enable Serial Output</a></h1> +<p> + Use the following steps to enable serial output: +</p> +<ol> + <li>Implement the car_mainboard_pre_console_init routine in the com_init.c + file: + <ol type="A"> + <li>Power on and enable the UART controller</li> + <li>Connect the UART receive and transmit data lines to the + appropriate SoC pins + </li> + </ol> + </li> + <li>Add Makefile.inc + <ol type="A"> + <li>Add com_init.c to romstage</li> + </ol> + </li> +</ol> + + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html index 70bb3e1..ee5c748 100644 --- a/src/soc/intel/soc.html +++ b/src/soc/intel/soc.html @@ -19,6 +19,11 @@ <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#BootBlock">Bootblock</a></li> <li><a href="#TempRamInit">TempRamInit</a></li> + <li><a href="#Romstage">Romstage</a> + <ol type="A"> + <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + </ol> + </li> </ol> @@ -267,6 +272,45 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="Romstage">Romstage</a></h1> + +<h2><a name="SerialOutput">Serial Output</a></h2> +<p> + The following steps add the serial output support for romstage: +</p> +<ol> + <li>Create the romstage subdirectory</li> + <li>Add romstage/romstage.c + <ol type="A"> + <li>Program the necessary base addresses</li> + <li>Disable the TCO</li> + </ol> + </li> + <li>Add romstage/Makefile.inc + <ol type="A"> + <li>Add romstage.c to romstage</li> + </ol> + </li> + <li>Add gpio configuration support if necessary</li> + <li>Add the necessary .h files to support the build</li> + <li>Update Makefile.inc + <ol type="A"> + <li>Add the romstage subdirectory</li> + <li>Add the gpio configuration support file to romstage</li> + </ol> + </li> + <li>Set the necessary Kconfig values to enable serial output: + <ul> + <li>CONFIG_DRIVERS_UART_<driver>=y</li> + <li>CONFIG_CONSOLE_SERIAL=y</li> + <li>CONFIG_UART_FOR_CONSOLE=<port></li> + <li>CONFIG_CONSOLE_SERIAL_115200=y</li> + </ul> + </li> +</ol> + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: Documentation: x86 add sleep state and minimal memory setup
by Leroy P Leahy 28 Jan '16

28 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13446 -gerrit commit 460a7c80a31026afb639f175e04c1251df1b975d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jan 27 17:17:36 2016 -0800 Documentation: x86 add sleep state and minimal memory setup Document how to add the sleep state and minimal memory setup. TEST=None Change-Id: Ibebeef34269dbf2366f1bea6d734f6bade4e4028 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Development.html | 14 +++++++ src/mainboard/intel/board.html | 79 +++++++++++++++++++++++++++++++++++++++ src/soc/intel/soc.html | 53 ++++++++++++++++++++++++++ 3 files changed, 146 insertions(+) diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html index f2789a2..a1a4f20 100644 --- a/Documentation/x86Development.html +++ b/Documentation/x86Development.html @@ -56,6 +56,20 @@ </ol> </li> <li>Enable <a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html#CorebootFspDebugging">coreboot/FSP</a> debugging</li> + <li>Determine the <a target="_blank" href="../src/soc/intel/soc.html#PreviousSleepState">Previous Sleep State</a></li> + <li>Enable DRAM: + <ol type="A"> + <li>Implement the SoC + <a target="_blank" href="../src/soc/intel/soc.html#MemoryInit">MemoryInit</a> + Support + </li> + <li>Implement the board support to read the + <a target="_blank" href="../src/mainboard/intel/board.html#SpdData">Memory Timing Data</a> + </li> + </ol> + </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> + <li>Coreboot should now attempt to load the payload</li> </ol> diff --git a/src/mainboard/intel/board.html b/src/mainboard/intel/board.html index c523298..9830119 100644 --- a/src/mainboard/intel/board.html +++ b/src/mainboard/intel/board.html @@ -15,6 +15,7 @@ <ol> <li><a href="#RequiredFiles">Required Files</a></li> <li>Enable <a href="#SerialOutput">Serial Output</a></li> + <li>Load the <a href="#SpdData">Memory Timing Data</a></li> </ol> @@ -101,6 +102,84 @@ </ol> +<hr> +<h1><a name="SpdData">Memory Timing Data</a></h1> +<p> + Memory timing data is located in the flash. This data is in the format of + <a target="_blank" href="https://en.wikipedia.org/wiki/Serial_presence_detect">serial presence detect</a> + (SPD) data. + Use the following steps to load the SPD data: +</p> +<ol> + <li>Edit Kconfig to add the DISPLAY_SPD_DATA" value which enables the + display of the SPD data being passed to MemoryInit + </li> + <li>Create an "spd" subdirectory</li> + <li>Create an spd/spd.c file for the SPD implementation + <ol type="A"> + <li>Implement the mainboard_fill_spd_data routine + <ol type="i"> + <li>Read the SPD data either from the spd.bin file or using I2C or SMBUS</li> + <li>Fill in the pei_data structure with SPD data for each of the DIMMs</li> + <li>Set the DIMM channel configuration</li> + </ol> + </li> + </ol> + </li> + <li>Add an .spd.hex file containing the memory timing data to the spd subdirectory</li> + <li>Create spd/Makefile.inc + <ol type="A"> + <li>Add spd.c to romstage</li> + <li>Add the .spd.hex file to SPD_SOURCES</li> + </ol> + </li> + <li>Edit Makefile.inc to add the spd subdirectory</li> + <li>Edit romstage.c + <ol type="A"> + <li>Call mainboard_fill_spd_data</li> + <li>Add mainboard_memory_init_params to copy the SPD and DRAM + configuration data from the pei_data structure into the UPDs + for MemoryInit + </li> + </ol> + </li> + <li>Edit devicetree.cb + <ol type="A"> + <li>Include the UPD parameters for MemoryInit except for: + <ul> + <li>Address of SPD data</li> + <li>DRAM configuration set above</li> + </ul> + </li> + </ol> + </li> + <li>A working FSP + <a target="_blank" href="../../drivers/intel/fsp1_1/fsp1_1.html#MemoryInit">MemoryInit</a> + routine is required to complete debugging</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + <li>0x36: + - Just before displaying the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">UPD parameters</a> + for FSP MemoryInit + </li> + <li>0x92: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_MEMORY_INIT</a> + - Just before calling FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + <li>0x37: + - Just after returning from FSP + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">MemoryInit</a> + </li> + </ol> + </li> + <li>Continue debugging with CONFIG_DISPLAY_HOBS enabled until TempRamExit is called</li> +</ol> + <hr> <p>Modified: 27 January 2016</p> diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html index ee5c748..fd65850 100644 --- a/src/soc/intel/soc.html +++ b/src/soc/intel/soc.html @@ -22,6 +22,8 @@ <li><a href="#Romstage">Romstage</a> <ol type="A"> <li>Enable <a href="#SerialOutput">Serial Output"</a></li> + <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> + <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> </ol> </li> </ol> @@ -310,6 +312,57 @@ mv build/coreboot.rom.new build/coreboot.rom </ol> +<h2><a name="PreviousSleepState">Determine Previous Sleep State</a></h2> +<p> + The following steps implement the code to get the previous sleep state: +</p> +<ol> + <li>Implement the fill_power_state routine which determines the previous sleep state</li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x32: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">romstage_common</a> + </li> + <li>0x33 - Just after calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">soc_pre_ram_init</a> + </li> + <li>0x34: + - Just after entering + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">raminit</a> + </li> + </ol> +</ol> + + +<h2><a name="MemoryInit">MemoryInit Support</a></h2> +<p> + The following steps implement the code to support the FSP MemoryInit call: +</p> +<ol> + <li>Add the chip.h header file to define the UPD values which get passed + to MemoryInit. Skip the values containing SPD addresses and DRAM + configuration data which is determined by the board. + <p> + <b>Build Note</b>: The src/mainboard/<Vendor>/<Board>/devicetree.cb + file specifies the default values for these parameters. The build + process creates the static.c module which contains the config data + structure containing these values. + </p> + </li> + <li>Edit romstage/romstage.c + <ol type="A"> + <li>Implement the romstage/romstage.c/soc_memory_init_params routine to + copy the values from the config structure into the UPD structure + </li> + <li>Implement the soc_display_memory_init_params routine to display + the updated UPD parameters by calling fsp_display_upd_value + </li> + </ol> + </li> +</ol> + + <hr> <p>Modified: 27 January 2016</p> </body>

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Patch set updated for coreboot: Documentation: Add x86 bootblock support
by Leroy P Leahy 28 Jan '16

28 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13441 -gerrit commit 37d601cc7f08462ccaab1480766d81c0761ebda3 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jan 27 15:50:40 2016 -0800 Documentation: Add x86 bootblock support Document what is involved with adding the bootblock support. TEST=None Change-Id: I6c8cc38e1b9346b4962588b33ca5e4ab8eac24c3 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Development.html | 1 + src/soc/intel/soc.html | 96 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 97 insertions(+) diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html index e0369e4..d04f08e 100644 --- a/Documentation/x86Development.html +++ b/Documentation/x86Development.html @@ -43,6 +43,7 @@ </li> <li>Get result to start <a target="_blank" href="../src/soc/intel/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="../src/soc/intel/soc.html#EarlyDebug">Early Debug</a></li> + <li>Implement and debug the <a target="_blank" href="../src/soc/intel/soc.html#Bootblock">bootblock</a> code</li> </ol> diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html index 0778c4d..9dd24ec 100644 --- a/src/soc/intel/soc.html +++ b/src/soc/intel/soc.html @@ -17,6 +17,7 @@ <li>SoC <a href="#RequiredFiles">Required Files</a></li> <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> + <li><a href="#BootBlock">Bootblock</a></li> </ol> @@ -100,6 +101,101 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="Bootblock">Bootblock</a></h1> +<p> + Implement the bootblock using the following steps: +</p> +<ol> + <li>Create the directory as src/soc/<Vendor>/<Chip Family>/bootblock</li> + <li>Add the timestamp.inc file which initializes the floating point registers and saves + the initial timestamp. + </li> + <li>Add the bootblock.c file which: + <ol type="A"> + <li>Enables memory-mapped PCI config access</li> + <li>Updates the microcode by calling intel_update_microcode_from_cbfs</li> + <li>Enable ROM caching</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add the BOOTBLOCK_CPU_INIT value to point to the bootblock.c file</li> + <li>Add the CHIPSET_BOOTBLOCK_INCLUDE value to point to the timestamp.inc file</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Makefile.inc file + <ol type="A"> + <li>Add the bootblock subdirectory</li> + </ol> + </li> + <li>Edit the src/soc/<Vendor>/<Chip Family>/memmap.c file + <ol type="A"> + <li>Add the fsp/memmap.h include file</li> + <li>Add the mmap_region_granularity routine</li> + </ol> + </li> + <li>Add the necessary .h files to define the necessary values and structures</li> + <li>When successful port 0x80 will output the following values: + <ol type="A"> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">_start</a> + </li> + <li>0x10: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_ENTER_PROTECTED_MODE</a> + - Bootblock executing in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">32-bit mode</a> + </li> + <li>0x10 - Verstage/romstage reached 32-bit mode</li> + </ol> + </li> +</ol> + +<p> + <b>Build Note:</b> The following files are included into the default bootblock image: +</p> +<ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + and includes the following files: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/prol…">src/arch/x86/prologue.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/reset16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">src/cpu/x86/16bit/entry16.inc</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/32bit…">src/cpu/x86/32bit/entry32.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/boot…">src/arch/x86/bootblock.S</a> + includes src/soc/<Vendor>/<Chip Family>/bootblock/timestamp.inc using the + CONFIG_CHIPSET_BOOTBLOCK_INCLUDE value set above + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/sse_e…">src/cpu/x86/sse_enable.inc</a></li> + <li>The code in + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + invokes the ROMCC tool to convert the following "C" code into assembler as bootblock.inc: + <ul> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/incl…">src/arch/x86/include/arch/bootblock_romcc.h</a></li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/lapic…">src/cpu/x86/lapic/boot_cpu.c</a></li> + <li>The CONFIG_BOOTBLOCK_CPU_INIT value set above typically points to the code in + src/soc/<Vendor>/<Chip Family>/bootblock/bootblock.c + </li> + </ul> + </li> + </ul> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/id.S">src/arch/x86/id.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/fit.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/intel/fit…">src/cpu/intel/fit/Makefile.inc</a> + </li> + <li><a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/walk…">src/arch/x86/walkcbfs.S</a> + added by <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/arch/x86/Make…">src/arch/x86/Makefile.inc</a> + </li> +</ul> + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: Documentation: Add x86 documentation for required files
by Leroy P Leahy 28 Jan '16

28 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13438 -gerrit commit f2b82301b5a0e1df40accee403db2055e1512609 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Jan 7 11:24:24 2016 -0800 Documentation: Add x86 documentation for required files Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Development.html | 52 +++++++++++++++++ src/drivers/intel/fsp1_1/fsp1_1.html | 44 +++++++++++++++ src/mainboard/intel/board.html | 83 +++++++++++++++++++++++++++ src/soc/intel/soc.html | 105 +++++++++++++++++++++++++++++++++++ 4 files changed, 284 insertions(+) diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html new file mode 100644 index 0000000..e0369e4 --- /dev/null +++ b/Documentation/x86Development.html @@ -0,0 +1,52 @@ +<!DOCTYPE html> +<html> + <head> + <title>Development</title> + </head> + <body> + +<h1>Coreboot/FSP Development Process for Intel x86</h1> +<p> + The x86 development process for coreboot is broken into the following components: +</p> +<ul> + <li>Coreboot <a target="_blank" href="../src/soc/intel/soc.html">SoC</a> development</li> + <li>Coreboot <a target="_blank" href="../src/mainboard/intel/board.html">mainboard</a> development</li> + <li><a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html">FSP 1.1</a> integration</li> +</ul> +<p> + The combined steps below describe how to bring up coreboot for a + system-on-a-chip (SoC) and a development board: +</p> +<table> + <tr bgcolor="#ffffc0"> + <td>The initial coreboot steps are single threaded! + The initial minimal FSP development is also single threaded. + Progress can speed up by adding more developers after the minimal coreboot/FSP + implementation reaches the payload. + </td> + </tr> +</table> +<ol> + <li>Get and build the necessary tools: + <ol type="A"> + <li>sudo apt-get install m4 bison flex ncurses-dev</li> + <li>make crossgcc</li> + </ol> + </li> + <li>Get something to build: + <ol type="A"> + <li><a target="_blank" href="../src/drivers/intel/fsp1_1/fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li><a target="_blank" href="../src/soc/intel/soc.html#RequiredFiles">SoC</a> required files</li> + <li><a target="_blank" href="../src/mainboard/intel/board.html#RequiredFiles">Board</a> required files</li> + </ol> + </li> + <li>Get result to start <a target="_blank" href="../src/soc/intel/soc.html#Descriptor">booting</a></li> + <li><a target="_blank" href="../src/soc/intel/soc.html#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/src/drivers/intel/fsp1_1/fsp1_1.html b/src/drivers/intel/fsp1_1/fsp1_1.html new file mode 100644 index 0000000..dcfd588 --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp1_1.html @@ -0,0 +1,44 @@ +<!DOCTYPE html> +<html> + <head> + <title>FSP 1.1</title> + </head> + <body> + +<h1>x86 FSP 1.1 Development</h1> +<p> + Firmware Support Package (FSP) development requires System-on-a-Chip (SoC) + and board support. The combined steps are listed + <a target="_blank" href="../../../../Documentation/x86Development.html">here</a>. + The development steps for FSP are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<h2><a name="CorebootRequiredFiles">Coreboot Required Files</a></h2> +<ol> + <li>Create the directories: + <ul> + <li>src/vendorcode/intel/fsp/fsp1_1/<Chip Family></li> + <li>3rdparty/blobs/mainboard/<Board Vendor>/<Board Name></li> + </ul> + </li> + <li> + The following files need to be copied from the FSP build or release into the + directories above: + <ul> + <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/<Chip Family>/FspUpdVpd.h</li> + <li>FSP.bin: 3rdparty/blobs/mainboard/<Board Vendor>/<Board Name>/fsp.bin</li> + </ul> + </li> +</ol> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/src/mainboard/intel/board.html b/src/mainboard/intel/board.html new file mode 100644 index 0000000..a7b5b32 --- /dev/null +++ b/src/mainboard/intel/board.html @@ -0,0 +1,83 @@ +<!DOCTYPE html> +<html> + <head> + <title>Board</title> + </head> + <body> + +<h1>x86 Board Development</h1> +<p> + Board development requires System-on-a-Chip (SoC) support. + The combined steps are listed + <a target="_blank" href="../../../Documentation/x86Development.html">here</a>. + The development steps for the board are listed below: +</p> +<ol> + <li><a href="#RequiredFiles">Required Files</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the board directory as src/mainboard/<Vendor>/<Board>. +</p> + +<p> + The following files are required to build a new board: +</p> +<ol> + <li>Kconfig.name - Defines the Kconfig value for the board</li> + <li>Kconfig + <ol type="A"> + <li>Selects the SoC for the board and specifies the SPI flash size + <ol type="I"> + <li>BOARD_ROMSIZE_KB_<Size></li> + <li>SOC_<Vendor>_<Chip Family></li> + </ol> + </li> + <li>Declare the Kconfig values for: + <ol type="I"> + <li>MAINBOARD_DIR</li> + <li>MAINBOARD_PART_NUMBER</li> + <li>MAINBOARD_VENDOR</li> + </ol> + </li> + </ol> + </li> + <li>devicetree.cb - Enable root bridge and serial port + <ol type="A"> + <li>The first line must be "chip soc/Intel/<soc family>"; + this path is used by the generated static.c to include the chip.h + header file + </li> + </ol> + </li> + <li>romstage.c + <ol type="A"> + <li>Add routine mainboard_romstage_entry which calls romstage_common</li> + </ol> + </li> + <li>Configure coreboot build: + <ol type="A"> + <li>Set LOCALVERSION</li> + <li>FLASHMAP_OFFSET = 0x00700000</li> + <li>Select vendor for the board</li> + <li>Select the board</li> + <LI>CBFS_SIZE = 0x00100000</li> + <li>Set the CPU_MICROCODE_CBFS_LEN</li> + <li>Set the CPU_MICROCODE_CBFS_LOC</li> + <li>Set the FSP_IMAGE_ID_STRING</li> + <li>Set the FSP_LOC</li> + <li>Disable GOP_SUPPORT</li> + <li>No payload</li> + <li>Choose the default value for all other options</li> + </ol> + </li> +</ol> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> \ No newline at end of file diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html new file mode 100644 index 0000000..0778c4d --- /dev/null +++ b/src/soc/intel/soc.html @@ -0,0 +1,105 @@ +<!DOCTYPE html> +<html> + <head> + <title>SoC</title> + </head> + <body> + +<h1>x86 System on a Chip (SoC) Development</h1> +<p> + SoC development is best done in parallel with development for a specific + board. The combined steps are listed + <a target="_blank" href="../../../Documentation/x86Development.html">here</a>. + The development steps for the SoC are listed below: +</p> +<ol> + <li><a target="_blank" href="../../drivers/intel/fsp1_1/fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li> + <li>SoC <a href="#RequiredFiles">Required Files</a></li> + <li><a href="#Descriptor">Start Booting</a></li> + <li><a href="#EarlyDebug">Early Debug</a></li> +</ol> + + +<hr> +<h1><a name="RequiredFiles">Required Files</a></h1> +<p> + Create the directory as src/soc/<Vendor>/<Chip Family>. +</p> + +<p> + The following files are required to build a new SoC: +</p> +<ul> + <li>Include files + <ul> + <li>include/soc/pei_data.h</li> + <li>include/soc/pm.h</li> + </ul> + </li> + <li>Kconfig - Defines the Kconfig value for the SoC and selects the tool + chains for the various stages: + <ul> + <li>select ARCH_BOOTBLOCK_<Tool Chain></li> + <li>select ARCH_RAMSTAGE_<Tool Chain></li> + <li>select ARCH_ROMSTAGE_<Tool Chain></li> + <li>select ARCH_VERSTAGE_<Tool Chain></li> + </ul> + </li> + <li>Makefile.inc - Specify the include paths</li> + <li>memmap.c - Top of usable RAM</li> +</ul> + + +<hr> +<h1><a name="Descriptor">Start Booting</a></h1> +<p> + Some SoC parts require additional firmware components in the flash. + This section describes how to add those pieces. +</p> + +<h2>Intel Firmware Descriptor</h2> +<p> + The Intel Firmware Descriptor (IFD) is located at the base of the flash part. + The following command overwrites the base of the flash image with the Intel + Firmware Descriptor: +</p> +<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre> + + +<h2><a name="MEB">Management Engine Binary</a></h2> +<p> + Some SoC parts contain and require that the Management Engine (ME) be running + before it is possible to bring the x86 processor out of reset. A binary file + containing the management engine code must be added to the firmware using the + ifdtool. The following commands add this binary blob: +</p> +<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom +mv build/coreboot.rom.new build/coreboot.rom +</code></pre> + + +<h2><a name="EarlyDebug">Early Debug</a></h2> +<p> + Early debugging between the reset vector and the time the serial port is enabled + is most easily done by writing values to port 0x80. +</p> + + +<h2>Success</h2> +<p> + When the reset vector is successfully invoked, port 0x80 will output the following value: +</p> +<ul> + <li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_RESET_VECTOR_CORRECT</a> + - Bootblock successfully executed the + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">reset vector</a> + and entered the 16-bit code at + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit…">_start</a> + </li> +</ul> + + +<hr> +<p>Modified: 27 January 2016</p> + </body> +</html> \ No newline at end of file

1 0

Patch set updated for coreboot: Documentation: Add the x86 FSP Binary
by Leroy P Leahy 28 Jan '16

28 Jan '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13442 -gerrit commit 1534a5d709a6efc40a8ec8bdc324391eff42f95b Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Jan 27 17:12:22 2016 -0800 Documentation: Add the x86 FSP Binary Document how to add the FSP binary to the SPI flash image. TEST=None Change-Id: I51b16600ea69853240282ac2eb0d84935b8e2a71 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/x86Development.html | 1 + src/drivers/intel/fsp1_1/fsp1_1.html | 13 +++++++ src/soc/intel/soc.html | 71 ++++++++++++++++++++++++++++++++++++ 3 files changed, 85 insertions(+) diff --git a/Documentation/x86Development.html b/Documentation/x86Development.html index d04f08e..9889fbd 100644 --- a/Documentation/x86Development.html +++ b/Documentation/x86Development.html @@ -44,6 +44,7 @@ <li>Get result to start <a target="_blank" href="../src/soc/intel/soc.html#Descriptor">booting</a></li> <li><a target="_blank" href="../src/soc/intel/soc.html#EarlyDebug">Early Debug</a></li> <li>Implement and debug the <a target="_blank" href="../src/soc/intel/soc.html#Bootblock">bootblock</a> code</li> + <li>Implement and debug the call to <a target="_blank" href="../src/soc/intel/soc.html#TempRamInit">TempRamInit</a></li> </ol> diff --git a/src/drivers/intel/fsp1_1/fsp1_1.html b/src/drivers/intel/fsp1_1/fsp1_1.html index dcfd588..ad02f3e 100644 --- a/src/drivers/intel/fsp1_1/fsp1_1.html +++ b/src/drivers/intel/fsp1_1/fsp1_1.html @@ -14,6 +14,7 @@ </p> <ol> <li><a href="#RequiredFiles">Required Files</a></li> + <li>Add the <a href="#FspBinary">FSP Binary File</a> to the Coreboot File System</li> </ol> @@ -39,6 +40,18 @@ <hr> +<h1><a name="FspBinary">Add the FSP Binary File to Coreboot File System</a></h1> +<p> + Add the FSP binary to the coreboot flash image using the following command: +</p> +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b <base address> -f fsp.bin</code></pre> +<p> + This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the + FSP code for TempRamInit may be executed in place. +</p> + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file diff --git a/src/soc/intel/soc.html b/src/soc/intel/soc.html index 9dd24ec..70bb3e1 100644 --- a/src/soc/intel/soc.html +++ b/src/soc/intel/soc.html @@ -18,6 +18,7 @@ <li><a href="#Descriptor">Start Booting</a></li> <li><a href="#EarlyDebug">Early Debug</a></li> <li><a href="#BootBlock">Bootblock</a></li> + <li><a href="#TempRamInit">TempRamInit</a></li> </ol> @@ -196,6 +197,76 @@ mv build/coreboot.rom.new build/coreboot.rom <hr> +<h1><a name="TempRamInit">TempRamInit</a></h1> +<p> + Enable the call to TempRamInit using the following steps: +</p> +<ol> + <li>Edit the src/soc/<Vendor>/<Chip Family>/Kconfig file + <ol type="A"> + <li>Add "select USE_GENERIC_FSP_CAR_INC" to enable the use of + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">src/drivers/intel/fsp1_1/cache_as_ram.inc</a> + </li> + <li>Add "select SOC_INTEL_COMMON" to enable the use of the files from + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/soc/intel/com…">src/soc/intel/common</a> + specifically building util.c + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xba and 0x01 - The FSP image was not found</li> + </ol> + </li> + <li>Add the <a target="_blank" href="../../drivers/intel/fsp1_1/FSP1_1.html#FspBinary">FSP binary file</a> to the flash image</li> + <li>Set the following Kconfig values: + <ul> + <li>CONFIG_FSP_LOC to the FSP base address specified in the previous step</li> + <li>CONFIG_FSP_IMAGE_ID_STRING</li> + </ul> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>Alternating 0xbb and 0x02 - TempRamInit executed, no CPU microcode update found</li> + </ol> + </li> + <li>Add the CPU microcode update file + <ol type="A"> + <li>Add the microcode file with the following command +<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t microcode -n cpu_microcode_blob.bin -b <base address> -f cpu_microcode_blob.bin</code></pre> + </li> + <li>Set the Kconfig values + <ul> + <li>CONFIG_CPU_MICROCODE_CBFS_LOC set to the value from the previous step</li> + <li>CONFIG_CPU_MICROCODE_CBFS_LEN</li> + </ul> + </li> + </ol> + </li> + <li>Debug the result until port 0x80 outputs + <ol type="A"> + <li>0x90: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/conso…">POST_FSP_TEMP_RAM_INIT</a> + - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">TempRamInit</a> + </li> + <li>0x23 - Just before calling + <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel…">cache_as_ram_main</a> + which is the start of the verstage code which may be part of romstage + </li> + </ol> + </li> +</ol> + + +<hr> <p>Modified: 27 January 2016</p> </body> </html> \ No newline at end of file

1 0

Patch set updated for coreboot: soc/braswell: Fix DSP clock
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12732 -gerrit commit 86cc34a292b6aa7e8c2f9972023513ab3fa75c02 Author: fdurairx <felixx.durairaj(a)intel.com> Date: Fri Aug 21 15:36:53 2015 -0700 soc/braswell: Fix DSP clock The codec clock frequency was incorrectly set to 25MHz. The only available frequency is 19.2MHz through external clock and PLL. Original-Reviewed-on: https://chromium-review.googlesource.com/295768 Original-Tested-by: Hannah Williams <hannah.williams(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5 Signed-off-by: Felix Durairaj <felixx.durairaj(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 3 +-- src/mainboard/intel/strago/devicetree.cb | 3 +-- src/soc/intel/braswell/chip.h | 8 ++++++-- src/soc/intel/braswell/include/soc/pm.h | 4 ++-- src/soc/intel/braswell/lpe.c | 24 +++++++++++------------- 5 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index c36ae3d..8932cf4 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/mainboard/intel/strago/devicetree.cb b/src/mainboard/intel/strago/devicetree.cb index c2aa47a..2bca939 100755 --- a/src/mainboard/intel/strago/devicetree.cb +++ b/src/mainboard/intel/strago/devicetree.cb @@ -72,8 +72,7 @@ chip soc/intel/braswell register "ISPPciDevConfig" = "3" # LPE audio codec settings - register "lpe_codec_clk_freq" = "25" # 25MHz clock - register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock # Enable devices in ACPI mode register "lpss_acpi_mode" = "1" diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 0f3c1d0..6eb1451 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -33,6 +33,11 @@ #define MEM_DDR3 0 #define MEM_LPDDR3 1 +enum lpe_clk_src { + LPE_CLK_SRC_XTAL, + LPE_CLK_SRC_PLL, +}; + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -41,8 +46,7 @@ struct soc_intel_braswell_config { int disable_slp_x_stretch_sus_fail; /* LPE Audio Clock configuration. */ - int lpe_codec_clk_freq; /* 19 or 25 are valid. */ - int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + enum lpe_clk_src lpe_codec_clk_src; /* 0=xtal 1=PLL, Both are 19.2Mhz. */ /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; diff --git a/src/soc/intel/braswell/include/soc/pm.h b/src/soc/intel/braswell/include/soc/pm.h index 9708b39..a4b2e2d 100644 --- a/src/soc/intel/braswell/include/soc/pm.h +++ b/src/soc/intel/braswell/include/soc/pm.h @@ -116,8 +116,8 @@ #define PLT_CLK_CTL_3 0x6c #define PLT_CLK_CTL_4 0x70 #define PLT_CLK_CTL_5 0x74 -# define CLK_FREQ_25MHZ (0x0 << 2) -# define CLK_FREQ_19P2MHZ (0x1 << 2) +# define CLK_SRC_XTAL (0x0 << 2) +# define CLK_SRC_PLL (0x1 << 2) # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) diff --git a/src/soc/intel/braswell/lpe.c b/src/soc/intel/braswell/lpe.c index a1a7c64..4662b43 100644 --- a/src/soc/intel/braswell/lpe.c +++ b/src/soc/intel/braswell/lpe.c @@ -96,32 +96,30 @@ static void setup_codec_clock(device_t dev) const char *freq_str; config = dev->chip_info; - switch (config->lpe_codec_clk_freq) { - case 19: - freq_str = "19.2"; - reg = CLK_FREQ_19P2MHZ; + switch (config->lpe_codec_clk_src) { + case LPE_CLK_SRC_XTAL: + /* XTAL driven bit2=0 */ + freq_str = "19.2MHz External Crystal"; + reg = CLK_SRC_XTAL; break; - case 25: - freq_str = "25"; - reg = CLK_FREQ_25MHZ; + case LPE_CLK_SRC_PLL: + /* PLL driven bit2=1 */ + freq_str = "19.2MHz PLL"; + reg = CLK_SRC_PLL; break; default: - printk(BIOS_DEBUG, "LPE codec clock not required.\n"); + reg = CLK_SRC_XTAL; + printk(BIOS_DEBUG, "LPE codec clock default to using Crystal\n"); return; } /* Default to always running. */ reg |= CLK_CTL_ON; - if (config->lpe_codec_clk_num < 0 || config->lpe_codec_clk_num > 5) { - printk(BIOS_DEBUG, "Invalid LPE codec clock number.\n"); - return; - } printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str); clk_reg = (u32 *) (PMC_BASE_ADDRESS + PLT_CLK_CTL_0); - clk_reg += config->lpe_codec_clk_num; write32(clk_reg, (read32(clk_reg) & ~0x7) | reg); }

1 0

Patch set updated for coreboot: soc/braswell: Add interface to program USB2_COMPBG register
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12739 -gerrit commit efc929c915b5f4ef1f865f6c18d22bc24f5a9fa8 Author: shkim <sh_.kim(a)samsung.com> Date: Tue Sep 22 17:53:58 2015 +0900 soc/braswell: Add interface to program USB2_COMPBG register Add interface to program USB2_COMPBG register to set HS_DISC_BG and HS_SQ reference voltage for each project. TEST=Get build success and do EFT test Original-Reviewed-on: https://chromium-review.googlesource.com/300846 Original-Reviewed-by: Shawn N <shawnn(a)chromium.org> Original-Tested-by: shkim <sh_.kim(a)samsung.com> Change-Id: If2201829e1a16b4f9916547f08c24e9291358325 Signed-off-by: Kenji Chen <kenji.chen(a)intel.com> Signed-off-by: shkim <sh_.kim(a)samsung.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/braswell/chip.h | 20 ++++++++++ src/soc/intel/braswell/include/soc/iosf.h | 5 +++ src/soc/intel/braswell/iosf.c | 15 +++++++- src/soc/intel/braswell/xhci.c | 62 +++++++++++++++++++++++++++++++ 4 files changed, 101 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/braswell/chip.h b/src/soc/intel/braswell/chip.h index 6eb1451..fbac84d 100644 --- a/src/soc/intel/braswell/chip.h +++ b/src/soc/intel/braswell/chip.h @@ -38,6 +38,18 @@ enum lpe_clk_src { LPE_CLK_SRC_PLL, }; +enum usb_comp_bg_value { + USB_COMP_BG_575_MV = 7, + USB_COMP_BG_650_MV = 6, + USB_COMP_BG_550_MV = 5, + USB_COMP_BG_537_MV = 4, + USB_COMP_BG_625_MV = 3, + USB_COMP_BG_700_MV = 2, + USB_COMP_BG_600_MV = 1, + USB_COMP_BG_675_MV = 0, +}; + + struct soc_intel_braswell_config { uint8_t enable_xdp_tap; uint8_t clkreq_enable; @@ -61,6 +73,14 @@ struct soc_intel_braswell_config { /* Allow PCIe devices to wake system from suspend. */ int pcie_wake_enable; + /* Program USB2_COMPBG register. + * [10:7] - select vref to AFE port + * x111 - 575mV, x110 - 650mV, x101 - 550mV, x100 - 537.5mV, + * x011 - 625mV, x010 - 700mV, x001 - 600mV, x000 - 675mV + */ + enum usb_comp_bg_value usb_comp_bg; + + /* * The following fields come from fsp_vpd.h .aka. VpdHeader.h. * These are configuration values that are passed to FSP during diff --git a/src/soc/intel/braswell/include/soc/iosf.h b/src/soc/intel/braswell/include/soc/iosf.h index add602f..e6758a6 100644 --- a/src/soc/intel/braswell/include/soc/iosf.h +++ b/src/soc/intel/braswell/include/soc/iosf.h @@ -69,6 +69,8 @@ uint32_t iosf_port58_read(int reg); void iosf_port58_write(int reg, uint32_t val); uint32_t iosf_scc_read(int reg); void iosf_scc_write(int reg, uint32_t val); +uint32_t iosf_usbphy_read(int reg); +void iosf_usbphy_write(int reg, uint32_t val); #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx); @@ -91,6 +93,7 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_PORT_0x5a 0x5a #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ #define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ +#define IOSF_PORT_USBPHY 0x43 /* USB PHY */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_0xa2 0xa2 #define IOSF_PORT_SSUS 0xa8 /* SUS */ @@ -109,6 +112,8 @@ void reg_script_write_iosf(struct reg_script_context *ctx); #define IOSF_OP_WRITE_0x58 (IOSF_OP_READ_0x58 | 1) #define IOSF_OP_READ_SCC 0x06 #define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) +#define IOSF_OP_READ_USBPHY 0x06 +#define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) /* * BUNIT Registers. diff --git a/src/soc/intel/braswell/iosf.c b/src/soc/intel/braswell/iosf.c index 1e7b924..98d1610 100644 --- a/src/soc/intel/braswell/iosf.c +++ b/src/soc/intel/braswell/iosf.c @@ -122,6 +122,15 @@ void iosf_scc_write(int reg, uint32_t val) return iosf_write_port(IOSF_WRITE(SCC), reg, val); } +uint32_t iosf_usbphy_read(int reg) +{ + return iosf_read_port(IOSF_READ(USBPHY), reg); +} + +void iosf_usbphy_write(int reg, uint32_t val) +{ + return iosf_write_port(IOSF_WRITE(USBPHY), reg, val); +} #if ENV_RAMSTAGE uint64_t reg_script_read_iosf(struct reg_script_context *ctx) @@ -140,6 +149,8 @@ uint64_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_port58_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); + case IOSF_PORT_USBPHY: + return iosf_usbphy_read(step->reg); default: printk(BIOS_DEBUG, "No read support for IOSF port 0x%x.\n", step->id); @@ -169,7 +180,9 @@ void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_SCC: iosf_scc_write(step->reg, step->value); break; - + case IOSF_PORT_USBPHY: + iosf_usbphy_write(step->reg, step->value); + break; default: printk(BIOS_DEBUG, "No write support for IOSF port 0x%x.\n", step->id); diff --git a/src/soc/intel/braswell/xhci.c b/src/soc/intel/braswell/xhci.c new file mode 100644 index 0000000..e3e3462 --- /dev/null +++ b/src/soc/intel/braswell/xhci.c @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <arch/acpi.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdint.h> +#include <reg_script.h> + +#include <soc/iomap.h> +#include <soc/iosf.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> +#include <soc/xhci.h> + +#include "chip.h" + +static void xhci_init(device_t dev) +{ + struct soc_intel_braswell_config *config = dev->chip_info; + + if (config && config->usb_comp_bg) { + struct reg_script ops[] = { + REG_IOSF_WRITE(IOSF_PORT_USBPHY, USBPHY_COMPBG, + config->usb_comp_bg), + REG_SCRIPT_END + }; + printk(BIOS_INFO, "Override USB2_COMPBG to: 0x%X\n", config->usb_comp_bg); + reg_script_run(ops); + } +} + +static struct device_operations xhci_device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xhci_init, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver soc_xhci __pci_driver = { + .ops = &xhci_device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = XHCI_DEVID +};

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Patch set updated for coreboot: intel/cyan: Disable SD Card Detect Simulation in FSP
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13036 -gerrit commit c21e54156d686b1269575530cb1cbd01190d26a5 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Sun Jan 17 23:22:12 2016 -0800 intel/cyan: Disable SD Card Detect Simulation in FSP CQ-DEPEND=CL:12742 Change-Id: Ifc95809e342d87f863dd60967f5b3a6ca5c0f7b3 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/google/cyan/devicetree.cb | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/cyan/devicetree.cb b/src/mainboard/google/cyan/devicetree.cb index 8932cf4..9d14ba6 100755 --- a/src/mainboard/google/cyan/devicetree.cb +++ b/src/mainboard/google/cyan/devicetree.cb @@ -70,6 +70,7 @@ chip soc/intel/braswell register "PMIC_I2CBus" = "0" register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" + register "PcdSdDetectChk" = "0" # Disable SD card detect # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock

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Patch set updated for coreboot: intel/strago: Enable native mode on sd card cd line
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12741 -gerrit commit 675b001e6fdf3ef59a4ed270b9413e25319fd537 Author: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Date: Wed Nov 4 14:25:15 2015 -0800 intel/strago: Enable native mode on sd card cd line Configuring Native Mode enables the card present bit in sd card controller register. TEST=Sd Card Plug/Unplug should work in OS and DepthCharge. Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/strago/gpio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/intel/strago/gpio.c b/src/mainboard/intel/strago/gpio.c index 4b58eac..11e2553 100755 --- a/src/mainboard/intel/strago/gpio.c +++ b/src/mainboard/intel/strago/gpio.c @@ -74,8 +74,7 @@ static const struct soc_gpio_map gpse_gpio_map[] = { Native_M1, /* 78 SDMMC3_PWR_EN_B */ GPIO_NC, /* 79 GPI ILB_SERIRQ */ Native_M1, /* 80 USB_OC0_B */ - GPI(trig_edge_both, L1, P_20K_H, non_maskable, - en_edge_detect, NA , NA), + NATIVE_INT_PU20K(1, L1), /* 81 SDMMC3_CD_B */ /* 81 SDMMC3_CD_B */ GPIO_NC, /* 82 spkr asummed gpio number */ Native_M1, /* 83 SUSPWRDNACK */

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Patch set updated for coreboot: intel/strago: Update DPTF parameters to higher temperature.
by Hannah Williams 28 Jan '16

28 Jan '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13484 -gerrit commit 782d816b319e5f015ea86b8f17d2b3a1cb4d62f7 Author: Divagar Mohandass <divagar.mohandass(a)intel.com> Date: Tue Sep 29 15:01:58 2015 +0530 intel/strago: Update DPTF parameters to higher temperature. Fish bowl HTML5 graphics benchmark with 250 fish is not reaching 60 FPS. This change will update the DPTF parameters to accommodate this test. TEST=Run fish bowl benchmark with 250 fish and check for 60 FPS. Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5 Original-Signed-off-by: Divagar Mohandass <divagar.mohandass(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/302208 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/strago/acpi/dptf.asl | 27 ++++++++------------------- src/mainboard/intel/strago/onboard.h | 3 +++ 2 files changed, 11 insertions(+), 19 deletions(-) diff --git a/src/mainboard/intel/strago/acpi/dptf.asl b/src/mainboard/intel/strago/acpi/dptf.asl index b875b93..2a95703 100755 --- a/src/mainboard/intel/strago/acpi/dptf.asl +++ b/src/mainboard/intel/strago/acpi/dptf.asl @@ -16,19 +16,19 @@ #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 49 +#define DPTF_TSR0_CRITICAL 75 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 65 +#define DPTF_TSR1_CRITICAL 85 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 49 +#define DPTF_TSR2_CRITICAL 75 #define DPTF_ENABLE_CHARGER @@ -50,18 +50,7 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.B0DB, \_SB.PCI0.B0DB, 100, 50, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 0 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, - -#ifdef DPTF_ENABLE_CHARGER - /* Charger Effect on Temp Sensor 1 */ - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, -#endif - - /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, - - /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0DB, \_SB.DPTF.TSR0, 100, 100, 0, 0, 0, 0 }, }) Name (MPPC, Package () @@ -69,7 +58,7 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 1600, /* PowerLimitMinimum */ + 2000, /* PowerLimitMinimum */ 6200, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ diff --git a/src/mainboard/intel/strago/onboard.h b/src/mainboard/intel/strago/onboard.h index 89c9b69..d93608b 100755 --- a/src/mainboard/intel/strago/onboard.h +++ b/src/mainboard/intel/strago/onboard.h @@ -74,4 +74,7 @@ #define BCRD2_PMIC_I2C_BUS 0x01 +#define DPTF_CPU_PASSIVE 88 +#define DPTF_CPU_CRITICAL 90 + #endif

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coreboot-gerrit January 2016